Catch a bug in the msp430 disassembler where an add instruction was confused

with an rla instruction.  Add a test for this to the testsuite.
This commit is contained in:
Nick Clifton 2004-01-02 17:26:11 +00:00
parent f0660b7388
commit 3ab4893121
5 changed files with 17 additions and 2 deletions

View file

@ -1,3 +1,7 @@
2004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
* gas/msp430/opcode.s: Add test for an 'add' instruction which
looks similar to an 'rla' instruction.
For older changes see ChangeLog-9303

View file

@ -42,4 +42,4 @@ Disassembly of section .text:
0+05e <[^>]*> 82 4f 00 00 mov r15, &0x0000 ;
0+062 <[^>]*> 3f 40 f0 00 mov #240, r15 ;#0x00f0
0+066 <[^>]*> 30 40 00 00 br #0x0000 ;
0+06a <[^>]*> 92 52 00 02 72 01 add &0x0200,&0x0172 ;0x0200

View file

@ -52,3 +52,6 @@ main:
.comm c,4,2
.comm d,4,2
;; This next instruction triggered a bug which
;; was fixed by a patch to msp430-dis.c on Jan 2, 2004
add &0x200, &0x172

View file

@ -1,3 +1,7 @@
2004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
* msp430-dis.c (msp430_doubleoperand): Check for an 'add'
instruction which looks similar to an 'rla' instruction.
For older changes see ChangeLog-0203

View file

@ -1,5 +1,5 @@
/* Disassemble MSP430 instructions.
Copyright (C) 2002 Free Software Foundation, Inc.
Copyright (C) 2002, 2004 Free Software Foundation, Inc.
Contributed by Dmitry Diky <diwil@mail.ru>
@ -491,6 +491,10 @@ msp430_doubleoperand (info, opcode, addr, insn, op1, op2, comm1, comm2, cycles)
{
/* Absolute. */
dst = msp430dis_opcode (addr + 2, info);
/* If the 'src' field is not the same as the dst
then this is not an rla instruction. */
if (dst != msp430dis_opcode (addr + 4, info))
return 0;
cmd_len += 4;
*cycles = 6;
sprintf (op1, "&0x%04x", PS (dst));