* gas/ppc/altivec_xcoff.s: Do not use .machine pseudo-ops as it overrides gas options.
* gas/ppc/altivec_xcoff64.s: Likewise. * gas/ppc/booke_xcoff64.s: Likewise. * gas/ppc/altivec_xcoff.d: Accept 32bits offsets. * gas/ppc/booke_xcoff.s: Do not use .machine pseudo-op and remove * booke64 opcodes. * gas/ppc/booke_xcoff.d: Accept 32bits offsets and renumber. * gas/ppc/booke_xcoff64.d: Use booke opcodes.
This commit is contained in:
Nick Clifton
parent
7fac7ff4ae
commit
3a9eaa7da6
9 changed files with 33 additions and 31 deletions
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@ -1,3 +1,15 @@
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2007-10-01 Tristan Gingold <gingold@adacore.com>
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* gas/ppc/altivec_xcoff.s: Do not use .machine pseudo-ops as it
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overrides gas options.
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* gas/ppc/altivec_xcoff64.s: Likewise.
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* gas/ppc/booke_xcoff64.s: Likewise.
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* gas/ppc/altivec_xcoff.d: Accept 32bits offsets.
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* gas/ppc/booke_xcoff.s: Do not use .machine pseudo-op and remove
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booke64 opcodes.
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* gas/ppc/booke_xcoff.d: Accept 32bits offsets and renumber.
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* gas/ppc/booke_xcoff64.d: Use booke opcodes.
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2007-09-30 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/5080
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@ -6,7 +6,7 @@
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Disassembly of section .text:
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0000000000000000 <.text>:
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(00000000)?00000000 <.text>:
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0: 7c 60 06 6c dss 3
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4: 7e 00 06 6c dssall
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8: 7c 25 22 ac dst r5,r4,1
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@ -1,6 +1,5 @@
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# PowerPC xcoff AltiVec tests
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#as: -mppc -maltivec
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.machine "ppc"
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.csect .text[PR]
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.csect main[DS]
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main:
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@ -1,6 +1,5 @@
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# PowerPC xcoff64 AltiVec tests
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#as: -a64 -mppc64 -maltivec
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.machine "ppc64"
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.csect .text[PR]
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.csect main[DS]
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main:
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@ -6,23 +6,20 @@
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Disassembly of section .text:
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0000000000000000 <.text>:
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(00000000)?00000000 <.text>:
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0: 7c 22 3f 64 tlbre r1,r2,7
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4: 7c be 1f a4 tlbwe r5,r30,3
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8: 7c a8 48 2c icbt 5,r8,r9
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c: 7c a6 02 26 mfapidi r5,r6
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10: 7c 07 46 24 tlbivax r7,r8
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14: 7c 09 56 26 tlbivaxe r9,r10
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18: 7c 0b 67 24 tlbsx r11,r12
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1c: 7c 0d 77 26 tlbsxe r13,r14
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20: 7e 80 04 40 mcrxr64 cr5
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24: 4c 00 00 66 rfci
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28: 7c 60 01 06 wrtee r3
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2c: 7c 00 81 46 wrteei 1
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30: 7c 85 02 06 mfdcrx r4,r5
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34: 7c aa 3a 86 mfdcr r5,234
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38: 7c e6 03 06 mtdcrx r6,r7
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3c: 7d 10 6b 86 mtdcr 432,r8
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40: 7c 00 04 ac sync
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44: 7c 09 55 ec dcba r9,r10
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48: 7c 00 06 ac eieio
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14: 7c 0b 67 24 tlbsx r11,r12
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18: 4c 00 00 66 rfci
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1c: 7c 60 01 06 wrtee r3
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20: 7c 00 81 46 wrteei 1
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24: 7c 85 02 06 mfdcrx r4,r5
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28: 7c aa 3a 86 mfdcr r5,234
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2c: 7c e6 03 06 mtdcrx r6,r7
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30: 7d 10 6b 86 mtdcr 432,r8
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34: 7c 00 04 ac msync
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38: 7c 09 55 ec dcba r9,r10
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3c: 7c 00 06 ac mbar
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@ -1,6 +1,5 @@
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# Motorola PowerPC BookE tests
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#as: -mppc32 -mbooke32
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.machine "ppc32"
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#as: -mbooke32
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.csect .text[PR]
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.csect main[DS]
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main:
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@ -12,10 +11,7 @@ main:
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icbt 5, 8, 9
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mfapidi 5, 6
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tlbivax 7, 8
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tlbivaxe 9, 10
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tlbsx 11, 12
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tlbsxe 13, 14
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mcrxr64 5
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rfci
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wrtee 3
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wrteei 1
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@ -13,12 +13,12 @@ Disassembly of section .text:
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c: 24 46 00 3d bcel 2,4\*cr1\+eq,48 <.text\+0x48>
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10: 24 67 00 5a bcea 3,4\*cr1\+so,58 <.text\+0x58>
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12: R_BA_16 .text
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14: 24 88 00 7b bcela 4,4\*cr2,78 <.text\+0x78>
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14: 24 88 00 7b bcela 4,4\*cr2\+lt,78 <.text\+0x78>
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16: R_BA_16 .text
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18: 4c a9 00 22 bclre 5,4\*cr2\+gt
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1c: 4c aa 00 23 bclrel 5,4\*cr2\+eq
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20: 4d 0b 04 22 bcctre 8,4\*cr2\+so
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24: 4d 0c 04 23 bcctrel 8,4\*cr3
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24: 4d 0c 04 23 bcctrel 8,4\*cr3\+lt
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28: 58 00 00 74 be 9c <.text\+0x9c>
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2c: 58 00 00 89 bel b4 <.text\+0xb4>
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30: 58 00 00 f2 bea f0 <.text\+0xf0>
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@ -120,6 +120,6 @@ Disassembly of section .text:
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1a8: 7c aa 3a 86 mfdcr r5,234
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1ac: 7c e6 03 06 mtdcrx r6,r7
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1b0: 7d 10 6b 86 mtdcr 432,r8
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1b4: 7c 00 04 ac sync
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1b4: 7c 00 04 ac msync
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1b8: 7c 09 55 ec dcba r9,r10
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1bc: 7c 00 06 ac eieio
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1bc: 7c 00 06 ac mbar
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@ -1,6 +1,5 @@
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# Motorola PowerPC BookE tests
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#as: -a64 -mppc64 -mbooke64
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.machine "ppc64"
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.csect .text[PR]
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.csect main[DS]
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main:
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@ -6,9 +6,9 @@
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 \.text 00000004 0000000000000000 0000000000000000 000000a8 2\*\*2
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0 \.text 00000004 0+0 0+0 000000a8 2\*\*2
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CONTENTS, ALLOC, LOAD, CODE
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1 \.data 00000008 0000000000000004 0000000000000004 000000ac 2\*\*3
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1 \.data 00000008 0+04 0+04 000000ac 2\*\*3
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CONTENTS, ALLOC, LOAD, RELOC, DATA
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2 \.bss 00000000 000000000000000c 000000000000000c 00000000 2\*\*3
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2 \.bss 00000000 0+0c 0+0c 00000000 2\*\*3
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ALLOC
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