darkkirb/old-cross-binutils
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

Delete i960; deleted from GDB long long ago.

Browse source
This commit is contained in:
Andrew Cagney 2004-12-01 15:27:21 +00:00
parent 6e56eb075a
commit 33841fd962
30 changed files with 4 additions and 40714 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
sim/ChangeLog
View file

@ -1,3 +1,7 @@
2004-12-01 Andrew Cagney <cagney@gnu.org>
* i960: Delete directory.
2004-11-12 Andrew Cagney <cagney@gnu.org>
* d30v, fr30, mn10200, z8k: Delete directory.

215
sim/i960/ChangeLog
View file

@ -1,215 +0,0 @@
2004-12-01 Hans-Peter Nilsson <hp@axis.com>
* Makefile.in (stamp-desc): Specify opcfile.
2003-09-08 Dave Brolley <brolley@redhat.com>
On behalf of Doug Evans <dje@sebabeach.org>
* Makefile.in (stamp-arch,stamp-cpu, stamp-desc): Pass archfile to cgen.
2003-02-27 Andrew Cagney <cagney@redhat.com>
* sim-if.c (sim_open, sim_create_inferior): Rename _bfd to bfd.
2002-06-16 Andrew Cagney <ac131313@redhat.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
2001-07-05 Ben Elliston <bje@redhat.com>
* Makefile.in (stamp-arch): Use $(CGEN_CPU_DIR).
(stamp-cpu): Likewise.
(stamp-desc): Likewise.
2001-02-06 DJ Delorie <dj@redhat.com>
* i960-desc.c: Update all the A macro definitions to the new
stdc-sensitive versions that cgen would have used.
2001-01-12 Frank Ch. Eigler <fche@redhat.com>
* configure: Regenerated with sim_scache fix.
2000-11-18 Greg McGary <greg@mcgary.org>
* Makefile.in: remove `@true' commands for rules that have
$(CGEN_MAINT) as a prerequisite.
2000-08-21 Frank Ch. Eigler <fche@redhat.com>
* Makefile.in (i960-clean): Add stamp-arch, stamp-cpu.
(stamp-arch, stamp-cpu): New targets.
Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
2000-03-30 Dave Brolley <brolley@redhat.com>
* configure: Regenerated.
1999-10-04 Doug Evans <devans@casey.cygnus.com>
* sem.c,sem-switch.c: Rebuild.
* traps.c (sim_engine_invalid_insn): New arg `vpc'. Change type of
result to SEM_PC. Return vpc.
Wed Sep 29 14:46:36 1999 Dave Brolley <brolley@cygnus.com>
* traps.c (sim_engine_invalid_insn): Return PC.
Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
1999-08-28 Doug Evans <devans@casey.cygnus.com>
* cpu.h,decode.c,sem-switch.c,sem.c: Rebuild.
1999-08-09 Doug Evans <devans@casey.cygnus.com>
* cpu.h,decode.c,decode.h,model.c,sem-switch.c,sem.c: Rebuild.
1999-08-04 Doug Evans <devans@casey.cygnus.com>
* cpu.h,cpuall.h,decode.c,model.c,sem-switch.c,sem.c: Rebuild.
* i960-desc.h: Rebuild.
1999-05-08 Felix Lee <flee@cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
Fri Apr 16 16:50:31 1999 Doug Evans <devans@charmed.cygnus.com>
* devices.c (device_io_read_buffer): New arg `sd'.
(device_io_write_buffer): New arg `sd'.
(device_error): Give proper arg spec.
1999-04-14 Doug Evans <devans@casey.cygnus.com>
* i960-desc.c,i960-desc.h: Rebuild.
Sun Apr 11 00:25:17 1999 Jim Wilson <wilson@cygnus.com>
* TODO: Document more toolchain problems.
* cpu.h, decode.c, model.c, sem-switch.c, sem.c: Rebuild.
1999-04-10 Doug Evans <devans@casey.cygnus.com>
* cpu.h,decode.c,sem-switch.c,sem.c: Rebuild.
Fri Apr 9 19:30:05 1999 Jim Wilson <wilson@cygnus.com>
* README, TODO: Clean up and update.
* sim-if.c: s/m32r/i960. s/sparc32/i960.
* decode.c, decode.h, i960-desc.c, i960-desc.h, i960-opc.h, model.c,
sem-switch.c, sem.c: Rebuild.
1999-03-27 Doug Evans <devans@casey.cygnus.com>
* decode.c: Rebuild.
1999-03-22 Doug Evans <devans@casey.cygnus.com>
* arch.c,arch.h,model.c,i960-desc.c,i960-desc.h,i960-opc.h: Rebuild.
* i960-sim.h (a_i960_h_gr_get,a_i960_h_gr_set): Declare.
(a_i960_h_pc_get,a_i960_h_pc_set): Declare.
* i960.c (a_i960_h_gr_get,a_i960_h_gr_set): New functions.
(a_i960_h_pc_get,a_i960_h_pc_set): Ditto.
* sim-if.c (sim_open): Update call to i960_cgen_cpu_open.
1999-03-11 Doug Evans <devans@casey.cygnus.com>
* arch.c,arch.h,cpu.c,i960-desc.c,i960-desc.h: Rebuild.
* sim-if.c (sim_open): Update call to i960_cgen_cpu_open.
1999-02-25 Doug Evans <devans@casey.cygnus.com>
* i960-desc.c,i960-desc.h: Rebuild.
1999-02-09 Doug Evans <devans@casey.cygnus.com>
* Makefile.in (I960_OBJS): Add i960-desc.o.
(SIM_EXTRA_DEPS): Replace cpu-opc.h with i960-desc.h,i960-opc.h.
* configure.in (sim_link_files,sim_link_links): Delete.
* configure: Rebuild.
* decode.c,decode.h,model.c,sem-switch.c,sem.c: Rebuild.
* devices.c: s/m32r/i960/.
* i960-desc.c: New file.
* i960-desc.h: New file.
* i960-opc.h: New file.
* i960-sim.h (I960_MISC_PROFILE): Delete.
* i960.c (i960base_model_insn_before): Delete unused code.
(i960base_model_insn_after): Ditto.
(i960_model_init_insn_cycles,i960_model_update_insn_cycles): Ditto.
(i960_model_record_cycles): Ditto.
* mloop.in (execute): CGEN_INSN_ATTR renamed to CGEN_INSN_ATTR_VALUE.
(extract-pbb): Use idesc->length to get insn length.
* sim-if.c (i960_disassemble_insn): New function.
(sim_open): Delete misc. profiling support. i960_cgen_cpu_open renamed
from i960_cgen_opcode_open. Set disassembler.
(sim_close): i960_cgen_cpu_open renamed from i960_cgen_opcode_open.
* sim-main.h: Don't include cpu-opc.h,cpu-sim.h. Include
i960-desc.h,i960-opc.h,i960-sim.h.
(struct _sim_cpu): Delete member i960_misc_profile.
1999-01-27 Doug Evans <devans@casey.cygnus.com>
* cpu.h,decode.c,model.c,sem-switch.c,sem.c: Rebuild.
1999-01-14 Doug Evans <devans@casey.cygnus.com>
* arch.c,arch.c,cpuall.h: Regenerate.
* cpu.c,cpu.h,decode.c,decode.h,model.c,sem-switch.c,sem.c: Regenerate.
1999-01-11 Doug Evans <devans@casey.cygnus.com>
* Makefile.in (i960-clean): rm eng.h.
* sim-main.h: Delete inclusion of ansidecl.h.
Delete inclusion of cgen-scache.h,cgen-cpu.h,cgen-trace.h,cpuall.h.
(SIM_CORE_SIGNAL): m32r -> i960.
* cpu.h: Regenerate.
* traps.c: m32r -> i960.
1999-01-05 Doug Evans <devans@casey.cygnus.com>
* Makefile.in (SIM_EXTRA_DEPS): Use CGEN_INCLUDE_DEPS.
(MAIN_INCLUDE_DEPS,INCLUDE_DEPS,OPS_INCLUDE_DEPS): Delete.
(sim-if.o): Use SIM_MAIN_DEPS.
(arch.o): Ditto.
(traps.o): Ditto.
(devices.o): Ditto.
(I960BASE_INCLUDE_DEPS): Use CGEN_MAIN_CPU_DEPS.
(i960.o): Use I960BASE_INCLUDE_DEPS.
(mloop.o,cpu.o,decode.o,sem.o,model.o): Ditto.
(stamp-arch): Pass mach=all to cgen-arch.
* cpu.c,cpu.h,decode.c,model.c,sem-switch.c,sem.c: Regenerate.
* sim-if.c (sim_open): Model probing code moved to sim-model.c.
1998-12-14 James E Wilson <wilson@wilson-pc.cygnus.com>
* cpu.h, decode.c, sem-switch.c, sem.c: Rebuilt.
* traps.c (i960_trap): Store syscall results in regs 16 to 18 instead
of regs 0 to 2.
Mon Dec 14 22:33:38 1998 Jim Wilson <wilson@cygnus.com>
* mloop.in (extract32): Add calls to @cpu@_fill_argbuf and
@cpu@_fil_argbuf_tp.
1998-12-14 Doug Evans <devans@casey.cygnus.com>
* configure.in: --enable-cgen-maint support moved to common/aclocal.m4.
* configure: Regenerate.
* sem-switch.c,sem.c: Regenerate.
1998-12-09 James E Wilson <wilson@wilson-pc.cygnus.com>
* mloop.in execute): Test ARGBUF_PROFILE_P before profiling.
Update calls to TRACE_INSN_INIT,TRACE_INSN_FINI.
* cpu.h, cpuall.h, decode.c, sem-switch.c, sem.c: Regenerate.
1998-12-08 James E Wilson <wilson@wilson-pc.cygnus.com>
* New directory.

130
sim/i960/Makefile.in
View file

@ -1,130 +0,0 @@
# Makefile template for Configure for the i960 simulator
# Copyright (C) 1996, 1997, 1998, 1999, 2004 Free Software Foundation, Inc.
# Contributed by Cygnus Support.
#
# This file is part of GDB, the GNU debugger.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License along
# with this program; if not, write to the Free Software Foundation, Inc.,
# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
## COMMON_PRE_CONFIG_FRAG
I960_OBJS = i960.o cpu.o decode.o sem.o model.o mloop.o i960-desc.o
CONFIG_DEVICES = dv-sockser.o
CONFIG_DEVICES =
SIM_OBJS = \
$(SIM_NEW_COMMON_OBJS) \
sim-cpu.o \
sim-engine.o \
sim-hload.o \
sim-hrw.o \
sim-model.o \
sim-reason.o \
cgen-utils.o cgen-trace.o cgen-scache.o \
cgen-run.o sim-reason.o sim-engine.o sim-stop.o \
sim-if.o arch.o \
$(I960_OBJS) \
traps.o devices.o \
$(CONFIG_DEVICES)
# Extra headers included by sim-main.h.
SIM_EXTRA_DEPS = \
$(CGEN_INCLUDE_DEPS) \
arch.h cpuall.h i960-sim.h i960-desc.h i960-opc.h
SIM_EXTRA_CFLAGS =
SIM_RUN_OBJS = nrun.o
SIM_EXTRA_CLEAN = i960-clean
# This selects the i960 newlib/libgloss syscall definitions.
#
# ??? This affects what stuff gets included from ../common/nltvals.def.
# For now, we need SYS_exit because of traps.c. If we really need this,
# then we need to add i960 specific definitions to nltvals.def.
NL_TARGET = -DNL_TARGET_i960
## COMMON_POST_CONFIG_FRAG
arch = i960
sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h
arch.o: arch.c $(SIM_MAIN_DEPS)
traps.o: traps.c targ-vals.h $(SIM_MAIN_DEPS)
devices.o: devices.c $(SIM_MAIN_DEPS)
# I960 objs
I960BASE_INCLUDE_DEPS = \
$(CGEN_MAIN_CPU_DEPS) \
cpu.h decode.h eng.h
i960.o: i960.c $(I960BASE_INCLUDE_DEPS)
# FIXME: Use of `mono' is wip.
mloop.c eng.h: stamp-mloop
stamp-mloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile
$(SHELL) $(srccom)/genmloop.sh \
-mono -fast -pbb -switch sem-switch.c \
-cpu i960base -infile $(srcdir)/mloop.in
$(SHELL) $(srcroot)/move-if-change eng.hin eng.h
$(SHELL) $(srcroot)/move-if-change mloop.cin mloop.c
touch stamp-mloop
# $(SHELL) $(srccom)/genmloop.sh \
# -mono -scache -fast i960base $(srcdir)/mloop.in \
# | sed -e 's/@cpu@/i960base/' -e 's/@CPU@/I960BASE/' >mloop.c
mloop.o: mloop.c sem-switch.c $(I960BASE_INCLUDE_DEPS)
cpu.o: cpu.c $(I960BASE_INCLUDE_DEPS)
decode.o: decode.c $(I960BASE_INCLUDE_DEPS)
sem.o: sem.c $(I960BASE_INCLUDE_DEPS)
model.o: model.c $(I960BASE_INCLUDE_DEPS)
i960-clean:
rm -f mloop.c eng.h stamp-mloop
rm -f tmp-*
rm -f stamp-arch stamp-cpu stamp-desc
# cgen support, enable with --enable-cgen-maint
CGEN_MAINT = ; @true
# The following line is commented in or out depending upon --enable-cgen-maint.
@CGEN_MAINT@CGEN_MAINT =
stamp-arch: $(CGEN_READ_SCM) $(CGEN_ARCH_SCM) $(CGEN_CPU_DIR)/i960.cpu
$(MAKE) cgen-arch $(CGEN_FLAGS_TO_PASS) mach=all \
archfile=$(CGEN_CPU_DIR)/i960.cpu \
FLAGS="with-scache with-profile=fn"
touch stamp-arch
arch.h arch.c cpuall.h: $(CGEN_MAINT) stamp-arch
stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(CGEN_CPU_DIR)/i960.cpu
$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
cpu=i960base mach=i960:ka_sa,i960:ca SUFFIX= \
archfile=$(CGEN_CPU_DIR)/i960.cpu \
FLAGS="with-scache with-profile=fn" \
EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"
touch stamp-cpu
cpu.h sem.c sem-switch.c model.c decode.c decode.h: $(CGEN_MAINT) stamp-cpu
stamp-desc: $(CGEN_READ_SCM) $(CGEN_DESC_SCM) \
$(CGEN_CPU_DIR)/sparc.cpu $(CGEN_CPU_DIR)/sparccom.cpu $(CGEN_CPU_DIR)/i960.cpu $(CGEN_CPU_DIR)/i960.cpu
$(MAKE) cgen-desc $(CGEN_FLAGS_TO_PASS) \
cpu=i960 mach=all \
archfile=$(CGEN_CPU_DIR)/i960.cpu opcfile=$(CGEN_CPU_DIR)/i960.opc
touch stamp-desc
i960-desc.c i960-desc.h i960-opc.h: $(CGEN_MAINT) stamp-desc

23
sim/i960/README
View file

@ -1,23 +0,0 @@
This is the i960 simulator directory.
It is still a work in progress. The current sources are reasonably
well tested and lots of features are in. However, there's lots
more yet to come.
---
The simulator only supports the i960KA currently. Not all instructions
are supported yet, only those instructions needed by the gcc/g++ testsuites
have been added so far. There is no profiling support as yet. There is
no pipeline or timing support as yet.
---
There are lots of machine generated files in the source directory!
They are only generated if you configure with --enable-cgen-maint,
similar in behaviour to Makefile.in, configure under automake/autoconf.
For details on the generator, see ../../cgen.
devo/cgen isn't part of the comp-tools module yet.
You'll need to check it out manually (also akin to automake/autoconf).

64
sim/i960/TODO
View file

@ -1,64 +0,0 @@
See ??? comments here and in cgen, and in libgloss/i960.
Simulator:
Update sim/i960 directory from sim/m32r directory. sim/i960 dir was created
by copying the sim/m32r in September 1998, and is missing all sim/m32r updates
since then.
Review, clean up, finish, etc simulator files that are not cgen generated.
This includes devices.c, i960-sim.h, mloop.in, sim-if.c, sim-main.h,
tconfig.in, and traps.c.
Some functions do not show up in trace output. This occasionally happens
for main.
Gdb core dumps if compile without -mka. Apparently a problem with recognizing
"core" machine type.
Get profiling working.
Add pipelining, execution unit, timing, etc info.
Add support for other models, besides KA.
Add support for newer architectures, e.g. v1.1 instructions.
Compiler:
Running gcc gives nm warning from collect about missing a.out file.
The output file is b.out, not a.out. Collect is probably looking for
the wrong file name.
Use of -mca gives lots of linker warnings for ka/ca architecture conflicts,
but the two architectures are compatible.
Need 96 bit long double support in fp-bit.c, otherwise any testcase using
long double arithmetic hits an abort and runtime.
Compiler takes far too much time to compile PlumHall testcases at high
optimization levels.
r2 seems to be an available call-clobbered registers, since it isn't used
until a call occurs, and is dead when the call returns.
BSP:
Libgloss does not check for syscall error returns, which means errno never
gets set.
Libgloss does not use the syscall.h file.
Binutils:
Objdump -d fails on 64-bit host, specifically irix6.
Gdb:
Gdb sometimes prints messages about trace/breakpoint trap when hitting a
breakpoint.
Frame, up, down and related commands don't work.
Gdb fails when next'ing over a leaf function compiled with -mleaf-procedure.
Gdb fails when step'ing over a return from such a leaf function.

15
sim/i960/acconfig.h
View file

@ -1,15 +0,0 @@
/* Define to 1 if NLS is requested. */
#undef ENABLE_NLS
/* Define as 1 if you have catgets and don't want to use GNU gettext. */
#undef HAVE_CATGETS
/* Define as 1 if you have gettext and don't want to use GNU gettext. */
#undef HAVE_GETTEXT
/* Define as 1 if you have the stpcpy function. */
#undef HAVE_STPCPY
/* Define if your locale.h file contains LC_MESSAGES. */
#undef HAVE_LC_MESSAGES

38
sim/i960/arch.c
View file

@ -1,38 +0,0 @@
/* Simulator support for i960.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
This file is part of the GNU Simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include "sim-main.h"
#include "bfd.h"
const MACH *sim_machs[] =
{
#ifdef HAVE_CPU_I960BASE
& i960_ka_sa_mach,
#endif
#ifdef HAVE_CPU_I960BASE
& i960_ca_mach,
#endif
0
};

44
sim/i960/arch.h
View file

@ -1,44 +0,0 @@
/* Simulator header for i960.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
This file is part of the GNU Simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef I960_ARCH_H
#define I960_ARCH_H
#define TARGET_BIG_ENDIAN 1
/* Enum declaration for model types. */
typedef enum model_type {
MODEL_I960KA, MODEL_I960CA, MODEL_MAX
} MODEL_TYPE;
#define MAX_MODELS ((int) MODEL_MAX)
/* Enum declaration for unit types. */
typedef enum unit_type {
UNIT_NONE, UNIT_I960KA_U_EXEC, UNIT_I960CA_U_EXEC, UNIT_MAX
} UNIT_TYPE;
#define MAX_UNITS (1)
#endif /* I960_ARCH_H */

162
sim/i960/config.in
View file

@ -1,162 +0,0 @@
/* config.in. Generated automatically from configure.in by autoheader. */
/* Define if using alloca.c. */
#undef C_ALLOCA
/* Define to empty if the keyword does not work. */
#undef const
/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems.
This function is required for alloca.c support on those systems. */
#undef CRAY_STACKSEG_END
/* Define if you have alloca, as a function or macro. */
#undef HAVE_ALLOCA
/* Define if you have <alloca.h> and it should be used (not on Ultrix). */
#undef HAVE_ALLOCA_H
/* Define if you have a working `mmap' system call. */
#undef HAVE_MMAP
/* Define as __inline if that's what the C compiler calls it. */
#undef inline
/* Define to `long' if <sys/types.h> doesn't define. */
#undef off_t
/* Define if you need to in order for stat and other things to work. */
#undef _POSIX_SOURCE
/* Define as the return type of signal handlers (int or void). */
#undef RETSIGTYPE
/* Define to `unsigned' if <sys/types.h> doesn't define. */
#undef size_t
/* If using the C implementation of alloca, define if you know the
direction of stack growth for your system; otherwise it will be
automatically deduced at run-time.
STACK_DIRECTION > 0 => grows toward higher addresses
STACK_DIRECTION < 0 => grows toward lower addresses
STACK_DIRECTION = 0 => direction of growth unknown
*/
#undef STACK_DIRECTION
/* Define if you have the ANSI C header files. */
#undef STDC_HEADERS
/* Define if your processor stores words with the most significant
byte first (like Motorola and SPARC, unlike Intel and VAX). */
#undef WORDS_BIGENDIAN
/* Define to 1 if NLS is requested. */
#undef ENABLE_NLS
/* Define as 1 if you have gettext and don't want to use GNU gettext. */
#undef HAVE_GETTEXT
/* Define as 1 if you have the stpcpy function. */
#undef HAVE_STPCPY
/* Define if your locale.h file contains LC_MESSAGES. */
#undef HAVE_LC_MESSAGES
/* Define if you have the __argz_count function. */
#undef HAVE___ARGZ_COUNT
/* Define if you have the __argz_next function. */
#undef HAVE___ARGZ_NEXT
/* Define if you have the __argz_stringify function. */
#undef HAVE___ARGZ_STRINGIFY
/* Define if you have the __setfpucw function. */
#undef HAVE___SETFPUCW
/* Define if you have the dcgettext function. */
#undef HAVE_DCGETTEXT
/* Define if you have the getcwd function. */
#undef HAVE_GETCWD
/* Define if you have the getpagesize function. */
#undef HAVE_GETPAGESIZE
/* Define if you have the getrusage function. */
#undef HAVE_GETRUSAGE
/* Define if you have the munmap function. */
#undef HAVE_MUNMAP
/* Define if you have the putenv function. */
#undef HAVE_PUTENV
/* Define if you have the setenv function. */
#undef HAVE_SETENV
/* Define if you have the setlocale function. */
#undef HAVE_SETLOCALE
/* Define if you have the sigaction function. */
#undef HAVE_SIGACTION
/* Define if you have the stpcpy function. */
#undef HAVE_STPCPY
/* Define if you have the strcasecmp function. */
#undef HAVE_STRCASECMP
/* Define if you have the strchr function. */
#undef HAVE_STRCHR
/* Define if you have the time function. */
#undef HAVE_TIME
/* Define if you have the <argz.h> header file. */
#undef HAVE_ARGZ_H
/* Define if you have the <fcntl.h> header file. */
#undef HAVE_FCNTL_H
/* Define if you have the <fpu_control.h> header file. */
#undef HAVE_FPU_CONTROL_H
/* Define if you have the <limits.h> header file. */
#undef HAVE_LIMITS_H
/* Define if you have the <locale.h> header file. */
#undef HAVE_LOCALE_H
/* Define if you have the <malloc.h> header file. */
#undef HAVE_MALLOC_H
/* Define if you have the <nl_types.h> header file. */
#undef HAVE_NL_TYPES_H
/* Define if you have the <stdlib.h> header file. */
#undef HAVE_STDLIB_H
/* Define if you have the <string.h> header file. */
#undef HAVE_STRING_H
/* Define if you have the <strings.h> header file. */
#undef HAVE_STRINGS_H
/* Define if you have the <sys/param.h> header file. */
#undef HAVE_SYS_PARAM_H
/* Define if you have the <sys/resource.h> header file. */
#undef HAVE_SYS_RESOURCE_H
/* Define if you have the <sys/time.h> header file. */
#undef HAVE_SYS_TIME_H
/* Define if you have the <time.h> header file. */
#undef HAVE_TIME_H
/* Define if you have the <unistd.h> header file. */
#undef HAVE_UNISTD_H
/* Define if you have the <values.h> header file. */
#undef HAVE_VALUES_H

4294
sim/i960/configure vendored
View file

File diff suppressed because it is too large Load diff

16
sim/i960/configure.in
View file

@ -1,16 +0,0 @@
dnl Process this file with autoconf to produce a configure script.
sinclude(../common/aclocal.m4)
AC_PREREQ(2.5)dnl
AC_INIT(Makefile.in)
SIM_AC_COMMON
SIM_AC_OPTION_ENDIAN(LITTLE_ENDIAN)
SIM_AC_OPTION_ALIGNMENT(NONSTRICT_ALIGNMENT)
SIM_AC_OPTION_HOSTENDIAN
SIM_AC_OPTION_SCACHE(1024)
SIM_AC_OPTION_DEFAULT_MODEL(i960KA)
SIM_AC_OPTION_ENVIRONMENT
SIM_AC_OPTION_CGEN_MAINT
SIM_AC_OUTPUT

85
sim/i960/cpu.c
View file

@ -1,85 +0,0 @@
/* Misc. support for CPU family i960base.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
This file is part of the GNU Simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#define WANT_CPU i960base
#define WANT_CPU_I960BASE
#include "sim-main.h"
#include "cgen-ops.h"
/* Get the value of h-pc. */
USI
i960base_h_pc_get (SIM_CPU *current_cpu)
{
return CPU (h_pc);
}
/* Set a value for h-pc. */
void
i960base_h_pc_set (SIM_CPU *current_cpu, USI newval)
{
CPU (h_pc) = newval;
}
/* Get the value of h-gr. */
SI
i960base_h_gr_get (SIM_CPU *current_cpu, UINT regno)
{
return CPU (h_gr[regno]);
}
/* Set a value for h-gr. */
void
i960base_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
{
CPU (h_gr[regno]) = newval;
}
/* Get the value of h-cc. */
SI
i960base_h_cc_get (SIM_CPU *current_cpu)
{
return CPU (h_cc);
}
/* Set a value for h-cc. */
void
i960base_h_cc_set (SIM_CPU *current_cpu, SI newval)
{
CPU (h_cc) = newval;
}
/* Record trace results for INSN. */
void
i960base_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
int *indices, TRACE_RECORD *tr)
{
}

601
sim/i960/cpu.h
View file

@ -1,601 +0,0 @@
/* CPU family header for i960base.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
This file is part of the GNU Simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef CPU_I960BASE_H
#define CPU_I960BASE_H
/* Maximum number of instructions that are fetched at a time.
This is for LIW type instructions sets (e.g. m32r). */
#define MAX_LIW_INSNS 1
/* Maximum number of instructions that can be executed in parallel. */
#define MAX_PARALLEL_INSNS 1
/* CPU state information. */
typedef struct {
/* Hardware elements. */
struct {
/* program counter */
USI h_pc;
#define GET_H_PC() CPU (h_pc)
#define SET_H_PC(x) (CPU (h_pc) = (x))
/* general registers */
SI h_gr[32];
#define GET_H_GR(a1) CPU (h_gr)[a1]
#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
/* condition code */
SI h_cc;
#define GET_H_CC() CPU (h_cc)
#define SET_H_CC(x) (CPU (h_cc) = (x))
} hardware;
#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
} I960BASE_CPU_DATA;
/* Cover fns for register access. */
USI i960base_h_pc_get (SIM_CPU *);
void i960base_h_pc_set (SIM_CPU *, USI);
SI i960base_h_gr_get (SIM_CPU *, UINT);
void i960base_h_gr_set (SIM_CPU *, UINT, SI);
SI i960base_h_cc_get (SIM_CPU *);
void i960base_h_cc_set (SIM_CPU *, SI);
/* These must be hand-written. */
extern CPUREG_FETCH_FN i960base_fetch_register;
extern CPUREG_STORE_FN i960base_store_register;
typedef struct {
int empty;
} MODEL_I960KA_DATA;
typedef struct {
int empty;
} MODEL_I960CA_DATA;
/* Instruction argument buffer. */
union sem_fields {
struct { /* no operands */
int empty;
} fmt_empty;
struct { /* */
IADDR i_ctrl_disp;
} sfmt_bno;
struct { /* */
SI* i_br_src1;
unsigned char out_br_src1;
} sfmt_testno_reg;
struct { /* */
IADDR i_br_disp;
SI* i_br_src2;
UINT f_br_src1;
unsigned char in_br_src2;
} sfmt_cmpobe_lit;
struct { /* */
IADDR i_br_disp;
SI* i_br_src1;
SI* i_br_src2;
unsigned char in_br_src1;
unsigned char in_br_src2;
} sfmt_cmpobe_reg;
struct { /* */
SI* i_dst;
UINT f_src1;
UINT f_src2;
UINT f_srcdst;
unsigned char out_dst;
unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_1;
} sfmt_emul3;
struct { /* */
SI* i_dst;
SI* i_src1;
UINT f_src2;
UINT f_srcdst;
unsigned char in_src1;
unsigned char out_dst;
unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_1;
} sfmt_emul2;
struct { /* */
SI* i_dst;
SI* i_src2;
UINT f_src1;
UINT f_srcdst;
unsigned char in_src2;
unsigned char out_dst;
unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_1;
} sfmt_emul1;
struct { /* */
SI* i_dst;
SI* i_src1;
SI* i_src2;
UINT f_srcdst;
unsigned char in_src1;
unsigned char in_src2;
unsigned char out_dst;
unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_1;
} sfmt_emul;
struct { /* */
SI* i_abase;
SI* i_st_src;
UINT f_offset;
UINT f_srcdst;
unsigned char in_abase;
unsigned char in_h_gr_add__DFLT_index_of__DFLT_st_src_1;
unsigned char in_h_gr_add__DFLT_index_of__DFLT_st_src_2;
unsigned char in_h_gr_add__DFLT_index_of__DFLT_st_src_3;
unsigned char in_st_src;
} sfmt_stq_indirect_offset;
struct { /* */
SI* i_abase;
SI* i_dst;
UINT f_offset;
UINT f_srcdst;
unsigned char in_abase;
unsigned char out_dst;
unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_1;
unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_2;
unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_3;
} sfmt_ldq_indirect_offset;
struct { /* */
SI* i_abase;
SI* i_index;
SI* i_st_src;
UINT f_optdisp;
UINT f_scale;
UINT f_srcdst;
unsigned char in_abase;
unsigned char in_h_gr_add__DFLT_index_of__DFLT_st_src_1;
unsigned char in_h_gr_add__DFLT_index_of__DFLT_st_src_2;
unsigned char in_h_gr_add__DFLT_index_of__DFLT_st_src_3;
unsigned char in_index;
unsigned char in_st_src;
} sfmt_stq_indirect_index_disp;
struct { /* */
SI* i_abase;
SI* i_dst;
SI* i_index;
UINT f_optdisp;
UINT f_scale;
UINT f_srcdst;
unsigned char in_abase;
unsigned char in_index;
unsigned char out_dst;
unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_1;
unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_2;
unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_3;
} sfmt_ldq_indirect_index_disp;
struct { /* */
SI* i_dst;
SI* i_src1;
UINT f_src1;
UINT f_srcdst;
unsigned char in_h_gr_add__DFLT_index_of__DFLT_src1_1;
unsigned char in_h_gr_add__DFLT_index_of__DFLT_src1_2;
unsigned char in_h_gr_add__DFLT_index_of__DFLT_src1_3;
unsigned char in_src1;
unsigned char out_dst;
unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_1;
unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_2;
unsigned char out_h_gr_add__DFLT_index_of__DFLT_dst_3;
} sfmt_movq;
struct { /* */
UINT f_optdisp;
unsigned char in_h_gr_0;
unsigned char in_h_gr_1;
unsigned char in_h_gr_10;
unsigned char in_h_gr_11;
unsigned char in_h_gr_12;
unsigned char in_h_gr_13;
unsigned char in_h_gr_14;
unsigned char in_h_gr_15;
unsigned char in_h_gr_2;
unsigned char in_h_gr_3;
unsigned char in_h_gr_31;
unsigned char in_h_gr_4;
unsigned char in_h_gr_5;
unsigned char in_h_gr_6;
unsigned char in_h_gr_7;
unsigned char in_h_gr_8;
unsigned char in_h_gr_9;
unsigned char out_h_gr_0;
unsigned char out_h_gr_1;
unsigned char out_h_gr_10;
unsigned char out_h_gr_11;
unsigned char out_h_gr_12;
unsigned char out_h_gr_13;
unsigned char out_h_gr_14;
unsigned char out_h_gr_15;
unsigned char out_h_gr_2;
unsigned char out_h_gr_3;
unsigned char out_h_gr_31;
unsigned char out_h_gr_4;
unsigned char out_h_gr_5;
unsigned char out_h_gr_6;
unsigned char out_h_gr_7;
unsigned char out_h_gr_8;
unsigned char out_h_gr_9;
} sfmt_callx_disp;
struct { /* */
SI* i_abase;
UINT f_offset;
unsigned char in_abase;
unsigned char in_h_gr_0;
unsigned char in_h_gr_1;
unsigned char in_h_gr_10;
unsigned char in_h_gr_11;
unsigned char in_h_gr_12;
unsigned char in_h_gr_13;
unsigned char in_h_gr_14;
unsigned char in_h_gr_15;
unsigned char in_h_gr_2;
unsigned char in_h_gr_3;
unsigned char in_h_gr_31;
unsigned char in_h_gr_4;
unsigned char in_h_gr_5;
unsigned char in_h_gr_6;
unsigned char in_h_gr_7;
unsigned char in_h_gr_8;
unsigned char in_h_gr_9;
unsigned char out_h_gr_0;
unsigned char out_h_gr_1;
unsigned char out_h_gr_10;
unsigned char out_h_gr_11;
unsigned char out_h_gr_12;
unsigned char out_h_gr_13;
unsigned char out_h_gr_14;
unsigned char out_h_gr_15;
unsigned char out_h_gr_2;
unsigned char out_h_gr_3;
unsigned char out_h_gr_31;
unsigned char out_h_gr_4;
unsigned char out_h_gr_5;
unsigned char out_h_gr_6;
unsigned char out_h_gr_7;
unsigned char out_h_gr_8;
unsigned char out_h_gr_9;
} sfmt_callx_indirect_offset;
#if WITH_SCACHE_PBB
/* Writeback handler. */
struct {
/* Pointer to argbuf entry for insn whose results need writing back. */
const struct argbuf *abuf;
} write;
/* x-before handler */
struct {
/*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
int first_p;
} before;
/* x-after handler */
struct {
int empty;
} after;
/* This entry is used to terminate each pbb. */
struct {
/* Number of insns in pbb. */
int insn_count;
/* Next pbb to execute. */
SCACHE *next;
SCACHE *branch_target;
} chain;
#endif
};
/* The ARGBUF struct. */
struct argbuf {
/* These are the baseclass definitions. */
IADDR addr;
const IDESC *idesc;
char trace_p;
char profile_p;
/* ??? Temporary hack for skip insns. */
char skip_count;
char unused;
/* cpu specific data follows */
union sem semantic;
int written;
union sem_fields fields;
};
/* A cached insn.
??? SCACHE used to contain more than just argbuf. We could delete the
type entirely and always just use ARGBUF, but for future concerns and as
a level of abstraction it is left in. */
struct scache {
struct argbuf argbuf;
};
/* Macros to simplify extraction, reading and semantic code.
These define and assign the local vars that contain the insn's fields. */
#define EXTRACT_IFMT_EMPTY_VARS \
unsigned int length;
#define EXTRACT_IFMT_EMPTY_CODE \
length = 0; \
#define EXTRACT_IFMT_MULO_VARS \
UINT f_opcode; \
UINT f_srcdst; \
UINT f_src2; \
UINT f_m3; \
UINT f_m2; \
UINT f_m1; \
UINT f_opcode2; \
UINT f_zero; \
UINT f_src1; \
unsigned int length;
#define EXTRACT_IFMT_MULO_CODE \
length = 4; \
f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
f_m3 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
f_m2 = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \
f_m1 = EXTRACT_MSB0_UINT (insn, 32, 20, 1); \
f_opcode2 = EXTRACT_MSB0_UINT (insn, 32, 21, 4); \
f_zero = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
#define EXTRACT_IFMT_MULO1_VARS \
UINT f_opcode; \
UINT f_srcdst; \
UINT f_src2; \
UINT f_m3; \
UINT f_m2; \
UINT f_m1; \
UINT f_opcode2; \
UINT f_zero; \
UINT f_src1; \
unsigned int length;
#define EXTRACT_IFMT_MULO1_CODE \
length = 4; \
f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
f_m3 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
f_m2 = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \
f_m1 = EXTRACT_MSB0_UINT (insn, 32, 20, 1); \
f_opcode2 = EXTRACT_MSB0_UINT (insn, 32, 21, 4); \
f_zero = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
#define EXTRACT_IFMT_MULO2_VARS \
UINT f_opcode; \
UINT f_srcdst; \
UINT f_src2; \
UINT f_m3; \
UINT f_m2; \
UINT f_m1; \
UINT f_opcode2; \
UINT f_zero; \
UINT f_src1; \
unsigned int length;
#define EXTRACT_IFMT_MULO2_CODE \
length = 4; \
f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
f_m3 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
f_m2 = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \
f_m1 = EXTRACT_MSB0_UINT (insn, 32, 20, 1); \
f_opcode2 = EXTRACT_MSB0_UINT (insn, 32, 21, 4); \
f_zero = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
#define EXTRACT_IFMT_MULO3_VARS \
UINT f_opcode; \
UINT f_srcdst; \
UINT f_src2; \
UINT f_m3; \
UINT f_m2; \
UINT f_m1; \
UINT f_opcode2; \
UINT f_zero; \
UINT f_src1; \
unsigned int length;
#define EXTRACT_IFMT_MULO3_CODE \
length = 4; \
f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
f_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
f_m3 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
f_m2 = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \
f_m1 = EXTRACT_MSB0_UINT (insn, 32, 20, 1); \
f_opcode2 = EXTRACT_MSB0_UINT (insn, 32, 21, 4); \
f_zero = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
f_src1 = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
#define EXTRACT_IFMT_LDA_OFFSET_VARS \
UINT f_opcode; \
UINT f_srcdst; \
UINT f_abase; \
UINT f_modea; \
UINT f_zeroa; \
UINT f_offset; \
unsigned int length;
#define EXTRACT_IFMT_LDA_OFFSET_CODE \
length = 4; \
f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
f_modea = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
f_zeroa = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \
f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); \
#define EXTRACT_IFMT_LDA_INDIRECT_VARS \
UINT f_opcode; \
UINT f_srcdst; \
UINT f_abase; \
UINT f_modeb; \
UINT f_scale; \
UINT f_zerob; \
UINT f_index; \
unsigned int length;
#define EXTRACT_IFMT_LDA_INDIRECT_CODE \
length = 4; \
f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
f_modeb = EXTRACT_MSB0_UINT (insn, 32, 18, 4); \
f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); \
f_zerob = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
#define EXTRACT_IFMT_LDA_DISP_VARS \
UINT f_opcode; \
UINT f_optdisp; \
UINT f_srcdst; \
UINT f_abase; \
UINT f_modeb; \
UINT f_scale; \
UINT f_zerob; \
UINT f_index; \
/* Contents of trailing part of insn. */ \
UINT word_1; \
unsigned int length;
#define EXTRACT_IFMT_LDA_DISP_CODE \
length = 8; \
word_1 = GETIMEMUSI (current_cpu, pc + 4); \
f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); \
f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
f_modeb = EXTRACT_MSB0_UINT (insn, 32, 18, 4); \
f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); \
f_zerob = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
#define EXTRACT_IFMT_ST_OFFSET_VARS \
UINT f_opcode; \
UINT f_srcdst; \
UINT f_abase; \
UINT f_modea; \
UINT f_zeroa; \
UINT f_offset; \
unsigned int length;
#define EXTRACT_IFMT_ST_OFFSET_CODE \
length = 4; \
f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
f_modea = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
f_zeroa = EXTRACT_MSB0_UINT (insn, 32, 19, 1); \
f_offset = EXTRACT_MSB0_UINT (insn, 32, 20, 12); \
#define EXTRACT_IFMT_ST_INDIRECT_VARS \
UINT f_opcode; \
UINT f_srcdst; \
UINT f_abase; \
UINT f_modeb; \
UINT f_scale; \
UINT f_zerob; \
UINT f_index; \
unsigned int length;
#define EXTRACT_IFMT_ST_INDIRECT_CODE \
length = 4; \
f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
f_modeb = EXTRACT_MSB0_UINT (insn, 32, 18, 4); \
f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); \
f_zerob = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
#define EXTRACT_IFMT_ST_DISP_VARS \
UINT f_opcode; \
UINT f_optdisp; \
UINT f_srcdst; \
UINT f_abase; \
UINT f_modeb; \
UINT f_scale; \
UINT f_zerob; \
UINT f_index; \
/* Contents of trailing part of insn. */ \
UINT word_1; \
unsigned int length;
#define EXTRACT_IFMT_ST_DISP_CODE \
length = 8; \
word_1 = GETIMEMUSI (current_cpu, pc + 4); \
f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
f_optdisp = (0|(EXTRACT_MSB0_UINT (word_1, 32, 0, 32) << 0)); \
f_srcdst = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
f_abase = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
f_modeb = EXTRACT_MSB0_UINT (insn, 32, 18, 4); \
f_scale = EXTRACT_MSB0_UINT (insn, 32, 22, 3); \
f_zerob = EXTRACT_MSB0_UINT (insn, 32, 25, 2); \
f_index = EXTRACT_MSB0_UINT (insn, 32, 27, 5); \
#define EXTRACT_IFMT_CMPOBE_REG_VARS \
UINT f_opcode; \
UINT f_br_src1; \
UINT f_br_src2; \
UINT f_br_m1; \
SI f_br_disp; \
UINT f_br_zero; \
unsigned int length;
#define EXTRACT_IFMT_CMPOBE_REG_CODE \
length = 4; \
f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
f_br_src1 = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
f_br_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
f_br_m1 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
f_br_disp = ((((EXTRACT_MSB0_INT (insn, 32, 19, 11)) << (2))) + (pc)); \
f_br_zero = EXTRACT_MSB0_UINT (insn, 32, 30, 2); \
#define EXTRACT_IFMT_CMPOBE_LIT_VARS \
UINT f_opcode; \
UINT f_br_src1; \
UINT f_br_src2; \
UINT f_br_m1; \
SI f_br_disp; \
UINT f_br_zero; \
unsigned int length;
#define EXTRACT_IFMT_CMPOBE_LIT_CODE \
length = 4; \
f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
f_br_src1 = EXTRACT_MSB0_UINT (insn, 32, 8, 5); \
f_br_src2 = EXTRACT_MSB0_UINT (insn, 32, 13, 5); \
f_br_m1 = EXTRACT_MSB0_UINT (insn, 32, 18, 1); \
f_br_disp = ((((EXTRACT_MSB0_INT (insn, 32, 19, 11)) << (2))) + (pc)); \
f_br_zero = EXTRACT_MSB0_UINT (insn, 32, 30, 2); \
#define EXTRACT_IFMT_BNO_VARS \
UINT f_opcode; \
SI f_ctrl_disp; \
UINT f_ctrl_zero; \
unsigned int length;
#define EXTRACT_IFMT_BNO_CODE \
length = 4; \
f_opcode = EXTRACT_MSB0_UINT (insn, 32, 0, 8); \
f_ctrl_disp = ((((EXTRACT_MSB0_INT (insn, 32, 8, 22)) << (2))) + (pc)); \
f_ctrl_zero = EXTRACT_MSB0_UINT (insn, 32, 30, 2); \
/* Collection of various things for the trace handler to use. */
typedef struct trace_record {
IADDR pc;
/* FIXME:wip */
} TRACE_RECORD;
#endif /* CPU_I960BASE_H */

67
sim/i960/cpuall.h
View file

@ -1,67 +0,0 @@
/* Simulator CPU header for i960.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
This file is part of the GNU Simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef I960_CPUALL_H
#define I960_CPUALL_H
/* Include files for each cpu family. */
#ifdef WANT_CPU_I960BASE
#include "eng.h"
#include "cgen-engine.h"
#include "cpu.h"
#include "decode.h"
#endif
extern const MACH i960_ka_sa_mach;
extern const MACH i960_ca_mach;
#ifndef WANT_CPU
/* The ARGBUF struct. */
struct argbuf {
/* These are the baseclass definitions. */
IADDR addr;
const IDESC *idesc;
char trace_p;
char profile_p;
/* ??? Temporary hack for skip insns. */
char skip_count;
char unused;
/* cpu specific data follows */
};
#endif
#ifndef WANT_CPU
/* A cached insn.
??? SCACHE used to contain more than just argbuf. We could delete the
type entirely and always just use ARGBUF, but for future concerns and as
a level of abstraction it is left in. */
struct scache {
struct argbuf argbuf;
};
#endif
#endif /* I960_CPUALL_H */

5569
sim/i960/decode.c
View file

File diff suppressed because it is too large Load diff

160
sim/i960/decode.h
View file

@ -1,160 +0,0 @@
/* Decode header for i960base.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
This file is part of the GNU Simulators.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef I960BASE_DECODE_H
#define I960BASE_DECODE_H
extern const IDESC *i960base_decode (SIM_CPU *, IADDR,
CGEN_INSN_INT,
ARGBUF *);
extern void i960base_init_idesc_table (SIM_CPU *);
extern void i960base_sem_init_idesc_table (SIM_CPU *);
extern void i960base_semf_init_idesc_table (SIM_CPU *);
/* Enum declaration for instructions in cpu family i960base. */
typedef enum i960base_insn_type {
I960BASE_INSN_X_INVALID, I960BASE_INSN_X_AFTER, I960BASE_INSN_X_BEFORE, I960BASE_INSN_X_CTI_CHAIN
, I960BASE_INSN_X_CHAIN, I960BASE_INSN_X_BEGIN, I960BASE_INSN_MULO, I960BASE_INSN_MULO1
, I960BASE_INSN_MULO2, I960BASE_INSN_MULO3, I960BASE_INSN_REMO, I960BASE_INSN_REMO1
, I960BASE_INSN_REMO2, I960BASE_INSN_REMO3, I960BASE_INSN_DIVO, I960BASE_INSN_DIVO1
, I960BASE_INSN_DIVO2, I960BASE_INSN_DIVO3, I960BASE_INSN_REMI, I960BASE_INSN_REMI1
, I960BASE_INSN_REMI2, I960BASE_INSN_REMI3, I960BASE_INSN_DIVI, I960BASE_INSN_DIVI1
, I960BASE_INSN_DIVI2, I960BASE_INSN_DIVI3, I960BASE_INSN_ADDO, I960BASE_INSN_ADDO1
, I960BASE_INSN_ADDO2, I960BASE_INSN_ADDO3, I960BASE_INSN_SUBO, I960BASE_INSN_SUBO1
, I960BASE_INSN_SUBO2, I960BASE_INSN_SUBO3, I960BASE_INSN_NOTBIT, I960BASE_INSN_NOTBIT1
, I960BASE_INSN_NOTBIT2, I960BASE_INSN_NOTBIT3, I960BASE_INSN_AND, I960BASE_INSN_AND1
, I960BASE_INSN_AND2, I960BASE_INSN_AND3, I960BASE_INSN_ANDNOT, I960BASE_INSN_ANDNOT1
, I960BASE_INSN_ANDNOT2, I960BASE_INSN_ANDNOT3, I960BASE_INSN_SETBIT, I960BASE_INSN_SETBIT1
, I960BASE_INSN_SETBIT2, I960BASE_INSN_SETBIT3, I960BASE_INSN_NOTAND, I960BASE_INSN_NOTAND1
, I960BASE_INSN_NOTAND2, I960BASE_INSN_NOTAND3, I960BASE_INSN_XOR, I960BASE_INSN_XOR1
, I960BASE_INSN_XOR2, I960BASE_INSN_XOR3, I960BASE_INSN_OR, I960BASE_INSN_OR1
, I960BASE_INSN_OR2, I960BASE_INSN_OR3, I960BASE_INSN_NOR, I960BASE_INSN_NOR1
, I960BASE_INSN_NOR2, I960BASE_INSN_NOR3, I960BASE_INSN_XNOR, I960BASE_INSN_XNOR1
, I960BASE_INSN_XNOR2, I960BASE_INSN_XNOR3, I960BASE_INSN_NOT, I960BASE_INSN_NOT1
, I960BASE_INSN_NOT2, I960BASE_INSN_NOT3, I960BASE_INSN_ORNOT, I960BASE_INSN_ORNOT1
, I960BASE_INSN_ORNOT2, I960BASE_INSN_ORNOT3, I960BASE_INSN_CLRBIT, I960BASE_INSN_CLRBIT1
, I960BASE_INSN_CLRBIT2, I960BASE_INSN_CLRBIT3, I960BASE_INSN_SHLO, I960BASE_INSN_SHLO1
, I960BASE_INSN_SHLO2, I960BASE_INSN_SHLO3, I960BASE_INSN_SHRO, I960BASE_INSN_SHRO1
, I960BASE_INSN_SHRO2, I960BASE_INSN_SHRO3, I960BASE_INSN_SHLI, I960BASE_INSN_SHLI1
, I960BASE_INSN_SHLI2, I960BASE_INSN_SHLI3, I960BASE_INSN_SHRI, I960BASE_INSN_SHRI1
, I960BASE_INSN_SHRI2, I960BASE_INSN_SHRI3, I960BASE_INSN_EMUL, I960BASE_INSN_EMUL1
, I960BASE_INSN_EMUL2, I960BASE_INSN_EMUL3, I960BASE_INSN_MOV, I960BASE_INSN_MOV1
, I960BASE_INSN_MOVL, I960BASE_INSN_MOVL1, I960BASE_INSN_MOVT, I960BASE_INSN_MOVT1
, I960BASE_INSN_MOVQ, I960BASE_INSN_MOVQ1, I960BASE_INSN_MODPC, I960BASE_INSN_MODAC
, I960BASE_INSN_LDA_OFFSET, I960BASE_INSN_LDA_INDIRECT_OFFSET, I960BASE_INSN_LDA_INDIRECT, I960BASE_INSN_LDA_INDIRECT_INDEX
, I960BASE_INSN_LDA_DISP, I960BASE_INSN_LDA_INDIRECT_DISP, I960BASE_INSN_LDA_INDEX_DISP, I960BASE_INSN_LDA_INDIRECT_INDEX_DISP
, I960BASE_INSN_LD_OFFSET, I960BASE_INSN_LD_INDIRECT_OFFSET, I960BASE_INSN_LD_INDIRECT, I960BASE_INSN_LD_INDIRECT_INDEX
, I960BASE_INSN_LD_DISP, I960BASE_INSN_LD_INDIRECT_DISP, I960BASE_INSN_LD_INDEX_DISP, I960BASE_INSN_LD_INDIRECT_INDEX_DISP
, I960BASE_INSN_LDOB_OFFSET, I960BASE_INSN_LDOB_INDIRECT_OFFSET, I960BASE_INSN_LDOB_INDIRECT, I960BASE_INSN_LDOB_INDIRECT_INDEX
, I960BASE_INSN_LDOB_DISP, I960BASE_INSN_LDOB_INDIRECT_DISP, I960BASE_INSN_LDOB_INDEX_DISP, I960BASE_INSN_LDOB_INDIRECT_INDEX_DISP
, I960BASE_INSN_LDOS_OFFSET, I960BASE_INSN_LDOS_INDIRECT_OFFSET, I960BASE_INSN_LDOS_INDIRECT, I960BASE_INSN_LDOS_INDIRECT_INDEX
, I960BASE_INSN_LDOS_DISP, I960BASE_INSN_LDOS_INDIRECT_DISP, I960BASE_INSN_LDOS_INDEX_DISP, I960BASE_INSN_LDOS_INDIRECT_INDEX_DISP
, I960BASE_INSN_LDIB_OFFSET, I960BASE_INSN_LDIB_INDIRECT_OFFSET, I960BASE_INSN_LDIB_INDIRECT, I960BASE_INSN_LDIB_INDIRECT_INDEX
, I960BASE_INSN_LDIB_DISP, I960BASE_INSN_LDIB_INDIRECT_DISP, I960BASE_INSN_LDIB_INDEX_DISP, I960BASE_INSN_LDIB_INDIRECT_INDEX_DISP
, I960BASE_INSN_LDIS_OFFSET, I960BASE_INSN_LDIS_INDIRECT_OFFSET, I960BASE_INSN_LDIS_INDIRECT, I960BASE_INSN_LDIS_INDIRECT_INDEX
, I960BASE_INSN_LDIS_DISP, I960BASE_INSN_LDIS_INDIRECT_DISP, I960BASE_INSN_LDIS_INDEX_DISP, I960BASE_INSN_LDIS_INDIRECT_INDEX_DISP
, I960BASE_INSN_LDL_OFFSET, I960BASE_INSN_LDL_INDIRECT_OFFSET, I960BASE_INSN_LDL_INDIRECT, I960BASE_INSN_LDL_INDIRECT_INDEX
, I960BASE_INSN_LDL_DISP, I960BASE_INSN_LDL_INDIRECT_DISP, I960BASE_INSN_LDL_INDEX_DISP, I960BASE_INSN_LDL_INDIRECT_INDEX_DISP
, I960BASE_INSN_LDT_OFFSET, I960BASE_INSN_LDT_INDIRECT_OFFSET, I960BASE_INSN_LDT_INDIRECT, I960BASE_INSN_LDT_INDIRECT_INDEX
, I960BASE_INSN_LDT_DISP, I960BASE_INSN_LDT_INDIRECT_DISP, I960BASE_INSN_LDT_INDEX_DISP, I960BASE_INSN_LDT_INDIRECT_INDEX_DISP
, I960BASE_INSN_LDQ_OFFSET, I960BASE_INSN_LDQ_INDIRECT_OFFSET, I960BASE_INSN_LDQ_INDIRECT, I960BASE_INSN_LDQ_INDIRECT_INDEX
, I960BASE_INSN_LDQ_DISP, I960BASE_INSN_LDQ_INDIRECT_DISP, I960BASE_INSN_LDQ_INDEX_DISP, I960BASE_INSN_LDQ_INDIRECT_INDEX_DISP
, I960BASE_INSN_ST_OFFSET, I960BASE_INSN_ST_INDIRECT_OFFSET, I960BASE_INSN_ST_INDIRECT, I960BASE_INSN_ST_INDIRECT_INDEX
, I960BASE_INSN_ST_DISP, I960BASE_INSN_ST_INDIRECT_DISP, I960BASE_INSN_ST_INDEX_DISP, I960BASE_INSN_ST_INDIRECT_INDEX_DISP
, I960BASE_INSN_STOB_OFFSET, I960BASE_INSN_STOB_INDIRECT_OFFSET, I960BASE_INSN_STOB_INDIRECT, I960BASE_INSN_STOB_INDIRECT_INDEX
, I960BASE_INSN_STOB_DISP, I960BASE_INSN_STOB_INDIRECT_DISP, I960BASE_INSN_STOB_INDEX_DISP, I960BASE_INSN_STOB_INDIRECT_INDEX_DISP
, I960BASE_INSN_STOS_OFFSET, I960BASE_INSN_STOS_INDIRECT_OFFSET, I960BASE_INSN_STOS_INDIRECT, I960BASE_INSN_STOS_INDIRECT_INDEX
, I960BASE_INSN_STOS_DISP, I960BASE_INSN_STOS_INDIRECT_DISP, I960BASE_INSN_STOS_INDEX_DISP, I960BASE_INSN_STOS_INDIRECT_INDEX_DISP
, I960BASE_INSN_STL_OFFSET, I960BASE_INSN_STL_INDIRECT_OFFSET, I960BASE_INSN_STL_INDIRECT, I960BASE_INSN_STL_INDIRECT_INDEX
, I960BASE_INSN_STL_DISP, I960BASE_INSN_STL_INDIRECT_DISP, I960BASE_INSN_STL_INDEX_DISP, I960BASE_INSN_STL_INDIRECT_INDEX_DISP
, I960BASE_INSN_STT_OFFSET, I960BASE_INSN_STT_INDIRECT_OFFSET, I960BASE_INSN_STT_INDIRECT, I960BASE_INSN_STT_INDIRECT_INDEX
, I960BASE_INSN_STT_DISP, I960BASE_INSN_STT_INDIRECT_DISP, I960BASE_INSN_STT_INDEX_DISP, I960BASE_INSN_STT_INDIRECT_INDEX_DISP
, I960BASE_INSN_STQ_OFFSET, I960BASE_INSN_STQ_INDIRECT_OFFSET, I960BASE_INSN_STQ_INDIRECT, I960BASE_INSN_STQ_INDIRECT_INDEX
, I960BASE_INSN_STQ_DISP, I960BASE_INSN_STQ_INDIRECT_DISP, I960BASE_INSN_STQ_INDEX_DISP, I960BASE_INSN_STQ_INDIRECT_INDEX_DISP
, I960BASE_INSN_CMPOBE_REG, I960BASE_INSN_CMPOBE_LIT, I960BASE_INSN_CMPOBNE_REG, I960BASE_INSN_CMPOBNE_LIT
, I960BASE_INSN_CMPOBL_REG, I960BASE_INSN_CMPOBL_LIT, I960BASE_INSN_CMPOBLE_REG, I960BASE_INSN_CMPOBLE_LIT
, I960BASE_INSN_CMPOBG_REG, I960BASE_INSN_CMPOBG_LIT, I960BASE_INSN_CMPOBGE_REG, I960BASE_INSN_CMPOBGE_LIT
, I960BASE_INSN_CMPIBE_REG, I960BASE_INSN_CMPIBE_LIT, I960BASE_INSN_CMPIBNE_REG, I960BASE_INSN_CMPIBNE_LIT
, I960BASE_INSN_CMPIBL_REG, I960BASE_INSN_CMPIBL_LIT, I960BASE_INSN_CMPIBLE_REG, I960BASE_INSN_CMPIBLE_LIT
, I960BASE_INSN_CMPIBG_REG, I960BASE_INSN_CMPIBG_LIT, I960BASE_INSN_CMPIBGE_REG, I960BASE_INSN_CMPIBGE_LIT
, I960BASE_INSN_BBC_REG, I960BASE_INSN_BBC_LIT, I960BASE_INSN_BBS_REG, I960BASE_INSN_BBS_LIT
, I960BASE_INSN_CMPI, I960BASE_INSN_CMPI1, I960BASE_INSN_CMPI2, I960BASE_INSN_CMPI3
, I960BASE_INSN_CMPO, I960BASE_INSN_CMPO1, I960BASE_INSN_CMPO2, I960BASE_INSN_CMPO3
, I960BASE_INSN_TESTNO_REG, I960BASE_INSN_TESTG_REG, I960BASE_INSN_TESTE_REG, I960BASE_INSN_TESTGE_REG
, I960BASE_INSN_TESTL_REG, I960BASE_INSN_TESTNE_REG, I960BASE_INSN_TESTLE_REG, I960BASE_INSN_TESTO_REG
, I960BASE_INSN_BNO, I960BASE_INSN_BG, I960BASE_INSN_BE, I960BASE_INSN_BGE
, I960BASE_INSN_BL, I960BASE_INSN_BNE, I960BASE_INSN_BLE, I960BASE_INSN_BO
, I960BASE_INSN_B, I960BASE_INSN_BX_INDIRECT_OFFSET, I960BASE_INSN_BX_INDIRECT, I960BASE_INSN_BX_INDIRECT_INDEX
, I960BASE_INSN_BX_DISP, I960BASE_INSN_BX_INDIRECT_DISP, I960BASE_INSN_CALLX_DISP, I960BASE_INSN_CALLX_INDIRECT
, I960BASE_INSN_CALLX_INDIRECT_OFFSET, I960BASE_INSN_RET, I960BASE_INSN_CALLS, I960BASE_INSN_FMARK
, I960BASE_INSN_FLUSHREG, I960BASE_INSN_MAX
} I960BASE_INSN_TYPE;
/* Enum declaration for semantic formats in cpu family i960base. */
typedef enum i960base_sfmt_type {
I960BASE_SFMT_EMPTY, I960BASE_SFMT_MULO, I960BASE_SFMT_MULO1, I960BASE_SFMT_MULO2
, I960BASE_SFMT_MULO3, I960BASE_SFMT_NOTBIT, I960BASE_SFMT_NOTBIT1, I960BASE_SFMT_NOTBIT2
, I960BASE_SFMT_NOTBIT3, I960BASE_SFMT_NOT, I960BASE_SFMT_NOT1, I960BASE_SFMT_SHLO
, I960BASE_SFMT_SHLO1, I960BASE_SFMT_SHLO2, I960BASE_SFMT_SHLO3, I960BASE_SFMT_EMUL
, I960BASE_SFMT_EMUL1, I960BASE_SFMT_EMUL2, I960BASE_SFMT_EMUL3, I960BASE_SFMT_MOVL
, I960BASE_SFMT_MOVL1, I960BASE_SFMT_MOVT, I960BASE_SFMT_MOVT1, I960BASE_SFMT_MOVQ
, I960BASE_SFMT_MOVQ1, I960BASE_SFMT_MODPC, I960BASE_SFMT_LDA_OFFSET, I960BASE_SFMT_LDA_INDIRECT_OFFSET
, I960BASE_SFMT_LDA_INDIRECT, I960BASE_SFMT_LDA_INDIRECT_INDEX, I960BASE_SFMT_LDA_DISP, I960BASE_SFMT_LDA_INDIRECT_DISP
, I960BASE_SFMT_LDA_INDEX_DISP, I960BASE_SFMT_LDA_INDIRECT_INDEX_DISP, I960BASE_SFMT_LD_OFFSET, I960BASE_SFMT_LD_INDIRECT_OFFSET
, I960BASE_SFMT_LD_INDIRECT, I960BASE_SFMT_LD_INDIRECT_INDEX, I960BASE_SFMT_LD_DISP, I960BASE_SFMT_LD_INDIRECT_DISP
, I960BASE_SFMT_LD_INDEX_DISP, I960BASE_SFMT_LD_INDIRECT_INDEX_DISP, I960BASE_SFMT_LDL_OFFSET, I960BASE_SFMT_LDL_INDIRECT_OFFSET
, I960BASE_SFMT_LDL_INDIRECT, I960BASE_SFMT_LDL_INDIRECT_INDEX, I960BASE_SFMT_LDL_DISP, I960BASE_SFMT_LDL_INDIRECT_DISP
, I960BASE_SFMT_LDL_INDEX_DISP, I960BASE_SFMT_LDL_INDIRECT_INDEX_DISP, I960BASE_SFMT_LDT_OFFSET, I960BASE_SFMT_LDT_INDIRECT_OFFSET
, I960BASE_SFMT_LDT_INDIRECT, I960BASE_SFMT_LDT_INDIRECT_INDEX, I960BASE_SFMT_LDT_DISP, I960BASE_SFMT_LDT_INDIRECT_DISP
, I960BASE_SFMT_LDT_INDEX_DISP, I960BASE_SFMT_LDT_INDIRECT_INDEX_DISP, I960BASE_SFMT_LDQ_OFFSET, I960BASE_SFMT_LDQ_INDIRECT_OFFSET
, I960BASE_SFMT_LDQ_INDIRECT, I960BASE_SFMT_LDQ_INDIRECT_INDEX, I960BASE_SFMT_LDQ_DISP, I960BASE_SFMT_LDQ_INDIRECT_DISP
, I960BASE_SFMT_LDQ_INDEX_DISP, I960BASE_SFMT_LDQ_INDIRECT_INDEX_DISP, I960BASE_SFMT_ST_OFFSET, I960BASE_SFMT_ST_INDIRECT_OFFSET
, I960BASE_SFMT_ST_INDIRECT, I960BASE_SFMT_ST_INDIRECT_INDEX, I960BASE_SFMT_ST_DISP, I960BASE_SFMT_ST_INDIRECT_DISP
, I960BASE_SFMT_ST_INDEX_DISP, I960BASE_SFMT_ST_INDIRECT_INDEX_DISP, I960BASE_SFMT_STL_OFFSET, I960BASE_SFMT_STL_INDIRECT_OFFSET
, I960BASE_SFMT_STL_INDIRECT, I960BASE_SFMT_STL_INDIRECT_INDEX, I960BASE_SFMT_STL_DISP, I960BASE_SFMT_STL_INDIRECT_DISP
, I960BASE_SFMT_STL_INDEX_DISP, I960BASE_SFMT_STL_INDIRECT_INDEX_DISP, I960BASE_SFMT_STT_OFFSET, I960BASE_SFMT_STT_INDIRECT_OFFSET
, I960BASE_SFMT_STT_INDIRECT, I960BASE_SFMT_STT_INDIRECT_INDEX, I960BASE_SFMT_STT_DISP, I960BASE_SFMT_STT_INDIRECT_DISP
, I960BASE_SFMT_STT_INDEX_DISP, I960BASE_SFMT_STT_INDIRECT_INDEX_DISP, I960BASE_SFMT_STQ_OFFSET, I960BASE_SFMT_STQ_INDIRECT_OFFSET
, I960BASE_SFMT_STQ_INDIRECT, I960BASE_SFMT_STQ_INDIRECT_INDEX, I960BASE_SFMT_STQ_DISP, I960BASE_SFMT_STQ_INDIRECT_DISP
, I960BASE_SFMT_STQ_INDEX_DISP, I960BASE_SFMT_STQ_INDIRECT_INDEX_DISP, I960BASE_SFMT_CMPOBE_REG, I960BASE_SFMT_CMPOBE_LIT
, I960BASE_SFMT_CMPOBL_REG, I960BASE_SFMT_CMPOBL_LIT, I960BASE_SFMT_BBC_REG, I960BASE_SFMT_BBC_LIT
, I960BASE_SFMT_CMPI, I960BASE_SFMT_CMPI1, I960BASE_SFMT_CMPI2, I960BASE_SFMT_CMPI3
, I960BASE_SFMT_CMPO, I960BASE_SFMT_CMPO1, I960BASE_SFMT_CMPO2, I960BASE_SFMT_CMPO3
, I960BASE_SFMT_TESTNO_REG, I960BASE_SFMT_BNO, I960BASE_SFMT_B, I960BASE_SFMT_BX_INDIRECT_OFFSET
, I960BASE_SFMT_BX_INDIRECT, I960BASE_SFMT_BX_INDIRECT_INDEX, I960BASE_SFMT_BX_DISP, I960BASE_SFMT_BX_INDIRECT_DISP
, I960BASE_SFMT_CALLX_DISP, I960BASE_SFMT_CALLX_INDIRECT, I960BASE_SFMT_CALLX_INDIRECT_OFFSET, I960BASE_SFMT_RET
, I960BASE_SFMT_CALLS, I960BASE_SFMT_FMARK, I960BASE_SFMT_FLUSHREG
} I960BASE_SFMT_TYPE;
/* Function unit handlers (user written). */
extern int i960base_model_i960KA_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int i960base_model_i960CA_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
/* Profiling before/after handlers (user written) */
extern void i960base_model_insn_before (SIM_CPU *, int /*first_p*/);
extern void i960base_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
#endif /* I960BASE_DECODE_H */

107
sim/i960/devices.c
View file

@ -1,107 +0,0 @@
/* i960 device support
Copyright (C) 1997, 1998, 1999 Free Software Foundation, Inc.
Contributed by Cygnus Solutions.
This file is part of GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "sim-main.h"
#ifdef HAVE_DV_SOCKSER
#include "dv-sockser.h"
#endif
/* Handling the MSPR register is done by creating a device in the core
mapping that winds up here. */
device i960_devices;
int
device_io_read_buffer (device *me, void *source, int space,
address_word addr, unsigned nr_bytes,
SIM_DESC sd, SIM_CPU *cpu, sim_cia cia)
{
if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
return nr_bytes;
#ifdef HAVE_DV_SOCKSER
if (addr == UART_INCHAR_ADDR)
{
int c = dv_sockser_read (sd);
if (c == -1)
return 0;
*(char *) source = c;
return 1;
}
if (addr == UART_STATUS_ADDR)
{
int status = dv_sockser_status (sd);
unsigned char *p = source;
p[0] = 0;
p[1] = (((status & DV_SOCKSER_INPUT_EMPTY)
#ifdef UART_INPUT_READY0
? UART_INPUT_READY : 0)
#else
? 0 : UART_INPUT_READY)
#endif
+ ((status & DV_SOCKSER_OUTPUT_EMPTY) ? UART_OUTPUT_READY : 0));
return 2;
}
#endif
return nr_bytes;
}
int
device_io_write_buffer (device *me, const void *source, int space,
address_word addr, unsigned nr_bytes,
SIM_DESC sd, SIM_CPU *cpu, sim_cia cia)
{
#if WITH_SCACHE
/* MSPR support is deprecated but is kept in for upward compatibility
with existing overlay support. */
if (addr == MSPR_ADDR)
{
if ((*(const char *) source & MSPR_PURGE) != 0)
scache_flush (sd);
return nr_bytes;
}
if (addr == MCCR_ADDR)
{
if ((*(const char *) source & MCCR_CP) != 0)
scache_flush (sd);
return nr_bytes;
}
#endif
if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
return nr_bytes;
#if HAVE_DV_SOCKSER
if (addr == UART_OUTCHAR_ADDR)
{
int rc = dv_sockser_write (sd, *(char *) source);
return rc == 1;
}
#endif
return nr_bytes;
}
void
device_error (device *me, char *message, ...)
{
}

2106
sim/i960/i960-desc.c
View file

File diff suppressed because it is too large Load diff

317
sim/i960/i960-desc.h
View file

@ -1,317 +0,0 @@
/* CPU data header for i960.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef I960_CPU_H
#define I960_CPU_H
#define CGEN_ARCH i960
/* Given symbol S, return i960_cgen_<S>. */
#define CGEN_SYM(s) CONCAT3 (i960,_cgen_,s)
/* Selected cpu families. */
#define HAVE_CPU_I960BASE
#define CGEN_INSN_LSB0_P 0
/* Minimum size of any insn (in bytes). */
#define CGEN_MIN_INSN_SIZE 4
/* Maximum size of any insn (in bytes). */
#define CGEN_MAX_INSN_SIZE 8
#define CGEN_INT_INSN_P 0
/* FIXME: Need to compute CGEN_MAX_SYNTAX_BYTES. */
/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
we can't hash on everything up to the space. */
#define CGEN_MNEMONIC_OPERANDS
/* Maximum number of operands any insn or macro-insn has. */
#define CGEN_MAX_INSN_OPERANDS 16
/* Maximum number of fields in an instruction. */
#define CGEN_MAX_IFMT_OPERANDS 9
/* Enums. */
/* Enum declaration for insn opcode enums. */
typedef enum insn_opcode {
OPCODE_00, OPCODE_01, OPCODE_02, OPCODE_03
, OPCODE_04, OPCODE_05, OPCODE_06, OPCODE_07
, OPCODE_08, OPCODE_09, OPCODE_0A, OPCODE_0B
, OPCODE_0C, OPCODE_0D, OPCODE_0E, OPCODE_0F
, OPCODE_10, OPCODE_11, OPCODE_12, OPCODE_13
, OPCODE_14, OPCODE_15, OPCODE_16, OPCODE_17
, OPCODE_18, OPCODE_19, OPCODE_1A, OPCODE_1B
, OPCODE_1C, OPCODE_1D, OPCODE_1E, OPCODE_1F
, OPCODE_20, OPCODE_21, OPCODE_22, OPCODE_23
, OPCODE_24, OPCODE_25, OPCODE_26, OPCODE_27
, OPCODE_28, OPCODE_29, OPCODE_2A, OPCODE_2B
, OPCODE_2C, OPCODE_2D, OPCODE_2E, OPCODE_2F
, OPCODE_30, OPCODE_31, OPCODE_32, OPCODE_33
, OPCODE_34, OPCODE_35, OPCODE_36, OPCODE_37
, OPCODE_38, OPCODE_39, OPCODE_3A, OPCODE_3B
, OPCODE_3C, OPCODE_3D, OPCODE_3E, OPCODE_3F
, OPCODE_40, OPCODE_41, OPCODE_42, OPCODE_43
, OPCODE_44, OPCODE_45, OPCODE_46, OPCODE_47
, OPCODE_48, OPCODE_49, OPCODE_4A, OPCODE_4B
, OPCODE_4C, OPCODE_4D, OPCODE_4E, OPCODE_4F
, OPCODE_50, OPCODE_51, OPCODE_52, OPCODE_53
, OPCODE_54, OPCODE_55, OPCODE_56, OPCODE_57
, OPCODE_58, OPCODE_59, OPCODE_5A, OPCODE_5B
, OPCODE_5C, OPCODE_5D, OPCODE_5E, OPCODE_5F
, OPCODE_60, OPCODE_61, OPCODE_62, OPCODE_63
, OPCODE_64, OPCODE_65, OPCODE_66, OPCODE_67
, OPCODE_68, OPCODE_69, OPCODE_6A, OPCODE_6B
, OPCODE_6C, OPCODE_6D, OPCODE_6E, OPCODE_6F
, OPCODE_70, OPCODE_71, OPCODE_72, OPCODE_73
, OPCODE_74, OPCODE_75, OPCODE_76, OPCODE_77
, OPCODE_78, OPCODE_79, OPCODE_7A, OPCODE_7B
, OPCODE_7C, OPCODE_7D, OPCODE_7E, OPCODE_7F
, OPCODE_80, OPCODE_81, OPCODE_82, OPCODE_83
, OPCODE_84, OPCODE_85, OPCODE_86, OPCODE_87
, OPCODE_88, OPCODE_89, OPCODE_8A, OPCODE_8B
, OPCODE_8C, OPCODE_8D, OPCODE_8E, OPCODE_8F
, OPCODE_90, OPCODE_91, OPCODE_92, OPCODE_93
, OPCODE_94, OPCODE_95, OPCODE_96, OPCODE_97
, OPCODE_98, OPCODE_99, OPCODE_9A, OPCODE_9B
, OPCODE_9C, OPCODE_9D, OPCODE_9E, OPCODE_9F
, OPCODE_A0, OPCODE_A1, OPCODE_A2, OPCODE_A3
, OPCODE_A4, OPCODE_A5, OPCODE_A6, OPCODE_A7
, OPCODE_A8, OPCODE_A9, OPCODE_AA, OPCODE_AB
, OPCODE_AC, OPCODE_AD, OPCODE_AE, OPCODE_AF
, OPCODE_B0, OPCODE_B1, OPCODE_B2, OPCODE_B3
, OPCODE_B4, OPCODE_B5, OPCODE_B6, OPCODE_B7
, OPCODE_B8, OPCODE_B9, OPCODE_BA, OPCODE_BB
, OPCODE_BC, OPCODE_BD, OPCODE_BE, OPCODE_BF
, OPCODE_C0, OPCODE_C1, OPCODE_C2, OPCODE_C3
, OPCODE_C4, OPCODE_C5, OPCODE_C6, OPCODE_C7
, OPCODE_C8, OPCODE_C9, OPCODE_CA, OPCODE_CB
, OPCODE_CC, OPCODE_CD, OPCODE_CE, OPCODE_CF
, OPCODE_D0, OPCODE_D1, OPCODE_D2, OPCODE_D3
, OPCODE_D4, OPCODE_D5, OPCODE_D6, OPCODE_D7
, OPCODE_D8, OPCODE_D9, OPCODE_DA, OPCODE_DB
, OPCODE_DC, OPCODE_DD, OPCODE_DE, OPCODE_DF
, OPCODE_E0, OPCODE_E1, OPCODE_E2, OPCODE_E3
, OPCODE_E4, OPCODE_E5, OPCODE_E6, OPCODE_E7
, OPCODE_E8, OPCODE_E9, OPCODE_EA, OPCODE_EB
, OPCODE_EC, OPCODE_ED, OPCODE_EE, OPCODE_EF
, OPCODE_F0, OPCODE_F1, OPCODE_F2, OPCODE_F3
, OPCODE_F4, OPCODE_F5, OPCODE_F6, OPCODE_F7
, OPCODE_F8, OPCODE_F9, OPCODE_FA, OPCODE_FB
, OPCODE_FC, OPCODE_FD, OPCODE_FE, OPCODE_FF
} INSN_OPCODE;
/* Enum declaration for insn opcode2 enums. */
typedef enum insn_opcode2 {
OPCODE2_0, OPCODE2_1, OPCODE2_2, OPCODE2_3
, OPCODE2_4, OPCODE2_5, OPCODE2_6, OPCODE2_7
, OPCODE2_8, OPCODE2_9, OPCODE2_A, OPCODE2_B
, OPCODE2_C, OPCODE2_D, OPCODE2_E, OPCODE2_F
} INSN_OPCODE2;
/* Enum declaration for insn m3 enums. */
typedef enum insn_m3 {
M3_0, M3_1
} INSN_M3;
/* Enum declaration for insn m3 enums. */
typedef enum insn_m2 {
M2_0, M2_1
} INSN_M2;
/* Enum declaration for insn m1 enums. */
typedef enum insn_m1 {
M1_0, M1_1
} INSN_M1;
/* Enum declaration for insn zero enums. */
typedef enum insn_zero {
ZERO_0
} INSN_ZERO;
/* Enum declaration for insn mode a enums. */
typedef enum insn_modea {
MODEA_OFFSET, MODEA_INDIRECT_OFFSET
} INSN_MODEA;
/* Enum declaration for insn zero a enums. */
typedef enum insn_zeroa {
ZEROA_0
} INSN_ZEROA;
/* Enum declaration for insn mode b enums. */
typedef enum insn_modeb {
MODEB_ILL0, MODEB_ILL1, MODEB_ILL2, MODEB_ILL3
, MODEB_INDIRECT, MODEB_IP_DISP, MODEB_RES6, MODEB_INDIRECT_INDEX
, MODEB_ILL8, MODEB_ILL9, MODEB_ILL10, MODEB_ILL11
, MODEB_DISP, MODEB_INDIRECT_DISP, MODEB_INDEX_DISP, MODEB_INDIRECT_INDEX_DISP
} INSN_MODEB;
/* Enum declaration for insn zero b enums. */
typedef enum insn_zerob {
ZEROB_0
} INSN_ZEROB;
/* Enum declaration for insn branch m1 enums. */
typedef enum insn_br_m1 {
BR_M1_0, BR_M1_1
} INSN_BR_M1;
/* Enum declaration for insn branch zero enums. */
typedef enum insn_br_zero {
BR_ZERO_0
} INSN_BR_ZERO;
/* Enum declaration for insn ctrl zero enums. */
typedef enum insn_ctrl_zero {
CTRL_ZERO_0
} INSN_CTRL_ZERO;
/* Attributes. */
/* Enum declaration for machine type selection. */
typedef enum mach_attr {
MACH_BASE, MACH_I960_KA_SA, MACH_I960_CA, MACH_MAX
} MACH_ATTR;
/* Enum declaration for instruction set selection. */
typedef enum isa_attr {
ISA_I960, ISA_MAX
} ISA_ATTR;
/* Number of architecture variants. */
#define MAX_ISAS 1
#define MAX_MACHS ((int) MACH_MAX)
/* Ifield support. */
extern const struct cgen_ifld i960_cgen_ifld_table[];
/* Ifield attribute indices. */
/* Enum declaration for cgen_ifld attrs. */
typedef enum cgen_ifld_attr {
CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
, CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
} CGEN_IFLD_ATTR;
/* Number of non-boolean elements in cgen_ifld_attr. */
#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
/* Enum declaration for i960 ifield types. */
typedef enum ifield_type {
I960_F_NIL, I960_F_OPCODE, I960_F_SRCDST, I960_F_SRC2
, I960_F_M3, I960_F_M2, I960_F_M1, I960_F_OPCODE2
, I960_F_ZERO, I960_F_SRC1, I960_F_ABASE, I960_F_MODEA
, I960_F_ZEROA, I960_F_OFFSET, I960_F_MODEB, I960_F_SCALE
, I960_F_ZEROB, I960_F_INDEX, I960_F_OPTDISP, I960_F_BR_SRC1
, I960_F_BR_SRC2, I960_F_BR_M1, I960_F_BR_DISP, I960_F_BR_ZERO
, I960_F_CTRL_DISP, I960_F_CTRL_ZERO, I960_F_MAX
} IFIELD_TYPE;
#define MAX_IFLD ((int) I960_F_MAX)
/* Hardware attribute indices. */
/* Enum declaration for cgen_hw attrs. */
typedef enum cgen_hw_attr {
CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
, CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
} CGEN_HW_ATTR;
/* Number of non-boolean elements in cgen_hw_attr. */
#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
/* Enum declaration for i960 hardware types. */
typedef enum cgen_hw_type {
HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
, HW_H_IADDR, HW_H_PC, HW_H_GR, HW_H_CC
, HW_MAX
} CGEN_HW_TYPE;
#define MAX_HW ((int) HW_MAX)
/* Operand attribute indices. */
/* Enum declaration for cgen_operand attrs. */
typedef enum cgen_operand_attr {
CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
} CGEN_OPERAND_ATTR;
/* Number of non-boolean elements in cgen_operand_attr. */
#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
/* Enum declaration for i960 operand types. */
typedef enum cgen_operand_type {
I960_OPERAND_PC, I960_OPERAND_SRC1, I960_OPERAND_SRC2, I960_OPERAND_DST
, I960_OPERAND_LIT1, I960_OPERAND_LIT2, I960_OPERAND_ST_SRC, I960_OPERAND_ABASE
, I960_OPERAND_OFFSET, I960_OPERAND_SCALE, I960_OPERAND_INDEX, I960_OPERAND_OPTDISP
, I960_OPERAND_BR_SRC1, I960_OPERAND_BR_SRC2, I960_OPERAND_BR_DISP, I960_OPERAND_BR_LIT1
, I960_OPERAND_CTRL_DISP, I960_OPERAND_MAX
} CGEN_OPERAND_TYPE;
/* Number of operands types. */
#define MAX_OPERANDS ((int) I960_OPERAND_MAX)
/* Maximum number of operands referenced by any insn. */
#define MAX_OPERAND_INSTANCES 8
/* Insn attribute indices. */
/* Enum declaration for cgen_insn attrs. */
typedef enum cgen_insn_attr {
CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
, CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
} CGEN_INSN_ATTR;
/* Number of non-boolean elements in cgen_insn_attr. */
#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
/* cgen.h uses things we just defined. */
#include "opcode/cgen.h"
/* Attributes. */
extern const CGEN_ATTR_TABLE i960_cgen_hardware_attr_table[];
extern const CGEN_ATTR_TABLE i960_cgen_ifield_attr_table[];
extern const CGEN_ATTR_TABLE i960_cgen_operand_attr_table[];
extern const CGEN_ATTR_TABLE i960_cgen_insn_attr_table[];
/* Hardware decls. */
extern CGEN_KEYWORD i960_cgen_opval_h_gr;
extern CGEN_KEYWORD i960_cgen_opval_h_cc;
#endif /* I960_CPU_H */

170
sim/i960/i960-opc.h
View file

@ -1,170 +0,0 @@
/* Instruction opcode header for i960.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef I960_OPC_H
#define I960_OPC_H
/* -- opc.h */
#undef CGEN_DIS_HASH_SIZE
#define CGEN_DIS_HASH_SIZE 256
#undef CGEN_DIS_HASH
#define CGEN_DIS_HASH(buffer, value) ((unsigned char *) (buffer))[3]
/* ??? Until cgen disassembler complete and functioning well, redirect back
to old disassembler. */
#define CGEN_PRINT_INSN(od, pc, info) print_insn_i960_orig (pc, info)
/* -- */
/* Enum declaration for i960 instruction types. */
typedef enum cgen_insn_type {
I960_INSN_INVALID, I960_INSN_MULO, I960_INSN_MULO1, I960_INSN_MULO2
, I960_INSN_MULO3, I960_INSN_REMO, I960_INSN_REMO1, I960_INSN_REMO2
, I960_INSN_REMO3, I960_INSN_DIVO, I960_INSN_DIVO1, I960_INSN_DIVO2
, I960_INSN_DIVO3, I960_INSN_REMI, I960_INSN_REMI1, I960_INSN_REMI2
, I960_INSN_REMI3, I960_INSN_DIVI, I960_INSN_DIVI1, I960_INSN_DIVI2
, I960_INSN_DIVI3, I960_INSN_ADDO, I960_INSN_ADDO1, I960_INSN_ADDO2
, I960_INSN_ADDO3, I960_INSN_SUBO, I960_INSN_SUBO1, I960_INSN_SUBO2
, I960_INSN_SUBO3, I960_INSN_NOTBIT, I960_INSN_NOTBIT1, I960_INSN_NOTBIT2
, I960_INSN_NOTBIT3, I960_INSN_AND, I960_INSN_AND1, I960_INSN_AND2
, I960_INSN_AND3, I960_INSN_ANDNOT, I960_INSN_ANDNOT1, I960_INSN_ANDNOT2
, I960_INSN_ANDNOT3, I960_INSN_SETBIT, I960_INSN_SETBIT1, I960_INSN_SETBIT2
, I960_INSN_SETBIT3, I960_INSN_NOTAND, I960_INSN_NOTAND1, I960_INSN_NOTAND2
, I960_INSN_NOTAND3, I960_INSN_XOR, I960_INSN_XOR1, I960_INSN_XOR2
, I960_INSN_XOR3, I960_INSN_OR, I960_INSN_OR1, I960_INSN_OR2
, I960_INSN_OR3, I960_INSN_NOR, I960_INSN_NOR1, I960_INSN_NOR2
, I960_INSN_NOR3, I960_INSN_XNOR, I960_INSN_XNOR1, I960_INSN_XNOR2
, I960_INSN_XNOR3, I960_INSN_NOT, I960_INSN_NOT1, I960_INSN_NOT2
, I960_INSN_NOT3, I960_INSN_ORNOT, I960_INSN_ORNOT1, I960_INSN_ORNOT2
, I960_INSN_ORNOT3, I960_INSN_CLRBIT, I960_INSN_CLRBIT1, I960_INSN_CLRBIT2
, I960_INSN_CLRBIT3, I960_INSN_SHLO, I960_INSN_SHLO1, I960_INSN_SHLO2
, I960_INSN_SHLO3, I960_INSN_SHRO, I960_INSN_SHRO1, I960_INSN_SHRO2
, I960_INSN_SHRO3, I960_INSN_SHLI, I960_INSN_SHLI1, I960_INSN_SHLI2
, I960_INSN_SHLI3, I960_INSN_SHRI, I960_INSN_SHRI1, I960_INSN_SHRI2
, I960_INSN_SHRI3, I960_INSN_EMUL, I960_INSN_EMUL1, I960_INSN_EMUL2
, I960_INSN_EMUL3, I960_INSN_MOV, I960_INSN_MOV1, I960_INSN_MOVL
, I960_INSN_MOVL1, I960_INSN_MOVT, I960_INSN_MOVT1, I960_INSN_MOVQ
, I960_INSN_MOVQ1, I960_INSN_MODPC, I960_INSN_MODAC, I960_INSN_LDA_OFFSET
, I960_INSN_LDA_INDIRECT_OFFSET, I960_INSN_LDA_INDIRECT, I960_INSN_LDA_INDIRECT_INDEX, I960_INSN_LDA_DISP
, I960_INSN_LDA_INDIRECT_DISP, I960_INSN_LDA_INDEX_DISP, I960_INSN_LDA_INDIRECT_INDEX_DISP, I960_INSN_LD_OFFSET
, I960_INSN_LD_INDIRECT_OFFSET, I960_INSN_LD_INDIRECT, I960_INSN_LD_INDIRECT_INDEX, I960_INSN_LD_DISP
, I960_INSN_LD_INDIRECT_DISP, I960_INSN_LD_INDEX_DISP, I960_INSN_LD_INDIRECT_INDEX_DISP, I960_INSN_LDOB_OFFSET
, I960_INSN_LDOB_INDIRECT_OFFSET, I960_INSN_LDOB_INDIRECT, I960_INSN_LDOB_INDIRECT_INDEX, I960_INSN_LDOB_DISP
, I960_INSN_LDOB_INDIRECT_DISP, I960_INSN_LDOB_INDEX_DISP, I960_INSN_LDOB_INDIRECT_INDEX_DISP, I960_INSN_LDOS_OFFSET
, I960_INSN_LDOS_INDIRECT_OFFSET, I960_INSN_LDOS_INDIRECT, I960_INSN_LDOS_INDIRECT_INDEX, I960_INSN_LDOS_DISP
, I960_INSN_LDOS_INDIRECT_DISP, I960_INSN_LDOS_INDEX_DISP, I960_INSN_LDOS_INDIRECT_INDEX_DISP, I960_INSN_LDIB_OFFSET
, I960_INSN_LDIB_INDIRECT_OFFSET, I960_INSN_LDIB_INDIRECT, I960_INSN_LDIB_INDIRECT_INDEX, I960_INSN_LDIB_DISP
, I960_INSN_LDIB_INDIRECT_DISP, I960_INSN_LDIB_INDEX_DISP, I960_INSN_LDIB_INDIRECT_INDEX_DISP, I960_INSN_LDIS_OFFSET
, I960_INSN_LDIS_INDIRECT_OFFSET, I960_INSN_LDIS_INDIRECT, I960_INSN_LDIS_INDIRECT_INDEX, I960_INSN_LDIS_DISP
, I960_INSN_LDIS_INDIRECT_DISP, I960_INSN_LDIS_INDEX_DISP, I960_INSN_LDIS_INDIRECT_INDEX_DISP, I960_INSN_LDL_OFFSET
, I960_INSN_LDL_INDIRECT_OFFSET, I960_INSN_LDL_INDIRECT, I960_INSN_LDL_INDIRECT_INDEX, I960_INSN_LDL_DISP
, I960_INSN_LDL_INDIRECT_DISP, I960_INSN_LDL_INDEX_DISP, I960_INSN_LDL_INDIRECT_INDEX_DISP, I960_INSN_LDT_OFFSET
, I960_INSN_LDT_INDIRECT_OFFSET, I960_INSN_LDT_INDIRECT, I960_INSN_LDT_INDIRECT_INDEX, I960_INSN_LDT_DISP
, I960_INSN_LDT_INDIRECT_DISP, I960_INSN_LDT_INDEX_DISP, I960_INSN_LDT_INDIRECT_INDEX_DISP, I960_INSN_LDQ_OFFSET
, I960_INSN_LDQ_INDIRECT_OFFSET, I960_INSN_LDQ_INDIRECT, I960_INSN_LDQ_INDIRECT_INDEX, I960_INSN_LDQ_DISP
, I960_INSN_LDQ_INDIRECT_DISP, I960_INSN_LDQ_INDEX_DISP, I960_INSN_LDQ_INDIRECT_INDEX_DISP, I960_INSN_ST_OFFSET
, I960_INSN_ST_INDIRECT_OFFSET, I960_INSN_ST_INDIRECT, I960_INSN_ST_INDIRECT_INDEX, I960_INSN_ST_DISP
, I960_INSN_ST_INDIRECT_DISP, I960_INSN_ST_INDEX_DISP, I960_INSN_ST_INDIRECT_INDEX_DISP, I960_INSN_STOB_OFFSET
, I960_INSN_STOB_INDIRECT_OFFSET, I960_INSN_STOB_INDIRECT, I960_INSN_STOB_INDIRECT_INDEX, I960_INSN_STOB_DISP
, I960_INSN_STOB_INDIRECT_DISP, I960_INSN_STOB_INDEX_DISP, I960_INSN_STOB_INDIRECT_INDEX_DISP, I960_INSN_STOS_OFFSET
, I960_INSN_STOS_INDIRECT_OFFSET, I960_INSN_STOS_INDIRECT, I960_INSN_STOS_INDIRECT_INDEX, I960_INSN_STOS_DISP
, I960_INSN_STOS_INDIRECT_DISP, I960_INSN_STOS_INDEX_DISP, I960_INSN_STOS_INDIRECT_INDEX_DISP, I960_INSN_STL_OFFSET
, I960_INSN_STL_INDIRECT_OFFSET, I960_INSN_STL_INDIRECT, I960_INSN_STL_INDIRECT_INDEX, I960_INSN_STL_DISP
, I960_INSN_STL_INDIRECT_DISP, I960_INSN_STL_INDEX_DISP, I960_INSN_STL_INDIRECT_INDEX_DISP, I960_INSN_STT_OFFSET
, I960_INSN_STT_INDIRECT_OFFSET, I960_INSN_STT_INDIRECT, I960_INSN_STT_INDIRECT_INDEX, I960_INSN_STT_DISP
, I960_INSN_STT_INDIRECT_DISP, I960_INSN_STT_INDEX_DISP, I960_INSN_STT_INDIRECT_INDEX_DISP, I960_INSN_STQ_OFFSET
, I960_INSN_STQ_INDIRECT_OFFSET, I960_INSN_STQ_INDIRECT, I960_INSN_STQ_INDIRECT_INDEX, I960_INSN_STQ_DISP
, I960_INSN_STQ_INDIRECT_DISP, I960_INSN_STQ_INDEX_DISP, I960_INSN_STQ_INDIRECT_INDEX_DISP, I960_INSN_CMPOBE_REG
, I960_INSN_CMPOBE_LIT, I960_INSN_CMPOBNE_REG, I960_INSN_CMPOBNE_LIT, I960_INSN_CMPOBL_REG
, I960_INSN_CMPOBL_LIT, I960_INSN_CMPOBLE_REG, I960_INSN_CMPOBLE_LIT, I960_INSN_CMPOBG_REG
, I960_INSN_CMPOBG_LIT, I960_INSN_CMPOBGE_REG, I960_INSN_CMPOBGE_LIT, I960_INSN_CMPIBE_REG
, I960_INSN_CMPIBE_LIT, I960_INSN_CMPIBNE_REG, I960_INSN_CMPIBNE_LIT, I960_INSN_CMPIBL_REG
, I960_INSN_CMPIBL_LIT, I960_INSN_CMPIBLE_REG, I960_INSN_CMPIBLE_LIT, I960_INSN_CMPIBG_REG
, I960_INSN_CMPIBG_LIT, I960_INSN_CMPIBGE_REG, I960_INSN_CMPIBGE_LIT, I960_INSN_BBC_REG
, I960_INSN_BBC_LIT, I960_INSN_BBS_REG, I960_INSN_BBS_LIT, I960_INSN_CMPI
, I960_INSN_CMPI1, I960_INSN_CMPI2, I960_INSN_CMPI3, I960_INSN_CMPO
, I960_INSN_CMPO1, I960_INSN_CMPO2, I960_INSN_CMPO3, I960_INSN_TESTNO_REG
, I960_INSN_TESTG_REG, I960_INSN_TESTE_REG, I960_INSN_TESTGE_REG, I960_INSN_TESTL_REG
, I960_INSN_TESTNE_REG, I960_INSN_TESTLE_REG, I960_INSN_TESTO_REG, I960_INSN_BNO
, I960_INSN_BG, I960_INSN_BE, I960_INSN_BGE, I960_INSN_BL
, I960_INSN_BNE, I960_INSN_BLE, I960_INSN_BO, I960_INSN_B
, I960_INSN_BX_INDIRECT_OFFSET, I960_INSN_BX_INDIRECT, I960_INSN_BX_INDIRECT_INDEX, I960_INSN_BX_DISP
, I960_INSN_BX_INDIRECT_DISP, I960_INSN_CALLX_DISP, I960_INSN_CALLX_INDIRECT, I960_INSN_CALLX_INDIRECT_OFFSET
, I960_INSN_RET, I960_INSN_CALLS, I960_INSN_FMARK, I960_INSN_FLUSHREG
, I960_INSN_MAX
} CGEN_INSN_TYPE;
/* Index of `invalid' insn place holder. */
#define CGEN_INSN_INVALID I960_INSN_INVALID
/* Total number of insns in table. */
#define MAX_INSNS ((int) I960_INSN_MAX)
/* This struct records data prior to insertion or after extraction. */
struct cgen_fields
{
int length;
long f_nil;
long f_opcode;
long f_srcdst;
long f_src2;
long f_m3;
long f_m2;
long f_m1;
long f_opcode2;
long f_zero;
long f_src1;
long f_abase;
long f_modea;
long f_zeroa;
long f_offset;
long f_modeb;
long f_scale;
long f_zerob;
long f_index;
long f_optdisp;
long f_br_src1;
long f_br_src2;
long f_br_m1;
long f_br_disp;
long f_br_zero;
long f_ctrl_disp;
long f_ctrl_zero;
};
#define CGEN_INIT_PARSE(od) \
{\
}
#define CGEN_INIT_INSERT(od) \
{\
}
#define CGEN_INIT_EXTRACT(od) \
{\
}
#define CGEN_INIT_PRINT(od) \
{\
}
#endif /* I960_OPC_H */

54
sim/i960/i960-sim.h
View file

@ -1,54 +0,0 @@
#ifndef I960_SIM_H
#define I960_SIM_H
/* gdb register numbers */
/* Copied from gdb/config/i960/tc-i960.h. */
#define PCW_REGNUM 32 /* process control word */
#define ACW_REGNUM 33 /* arithmetic control word */
#define TCW_REGNUM 34 /* trace control word */
#define IP_REGNUM 35 /* instruction pointer */
#define FP0_REGNUM 36 /* First floating point register */
/* Some registers have more than one name */
#define PC_REGNUM IP_REGNUM /* GDB refers to ip as the Program Counter */
SI a_i960_h_gr_get (SIM_CPU *, UINT);
void a_i960_h_gr_set (SIM_CPU *, UINT, SI);
IADDR a_i960_h_pc_get (SIM_CPU *);
void a_i960_h_pc_set (SIM_CPU *, IADDR);
#define GETTWI GETTSI
#define SETTWI SETTSI
/* Exception, Interrupt, and Trap addresses */
/* ??? Hack for traps.c. */
#define EIT_TRAP_BASE_ADDR 0x40
/* Special purpose traps. */
/* ??? Hack for traps.c. */
#define TRAP_SYSCALL 0
#define TRAP_BREAKPOINT 1
/* Cache Purge Control (only exists on early versions of chips) */
/* ??? Hack for devices.c. */
#define MSPR_ADDR 0xfffffff7
#define MSPR_PURGE 1
/* Cache Control Register */
/* ??? Hack for devices.c. */
#define MCCR_ADDR 0xffffffff
#define MCCR_CP 0x80
/* Start address and length of all device support. */
/* ??? Hack for sim-if.c. */
#define I960_DEVICE_ADDR 0xff000000
#define I960_DEVICE_LEN 0x00ffffff
/* sim_core_attach device argument. */
/* ??? Hack for sim-if.c. */
extern device i960_devices;
/* FIXME: Temporary, until device support ready. */
/* ??? Hack for devices.c. */
struct _device { int foo; };
#endif I960_SIM_H

205
sim/i960/i960.c
View file

@ -1,205 +0,0 @@
/* i960 simulator support code
Copyright (C) 1998 Free Software Foundation, Inc.
Contributed by Cygnus Support.
This file is part of GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#define WANT_CPU
#define WANT_CPU_I960BASE
#include "sim-main.h"
#include "cgen-mem.h"
#include "cgen-ops.h"
/* The contents of BUF are in target byte order. */
int
i960base_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf,
int len)
{
if (rn < 32)
SETTWI (buf, a_i960_h_gr_get (current_cpu, rn));
else
switch (rn)
{
case PC_REGNUM :
SETTWI (buf, a_i960_h_pc_get (current_cpu));
break;
default :
return 0;
}
return -1; /*FIXME*/
}
/* The contents of BUF are in target byte order. */
int
i960base_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf,
int len)
{
if (rn < 32)
a_i960_h_gr_set (current_cpu, rn, GETTWI (buf));
else
switch (rn)
{
case PC_REGNUM :
a_i960_h_pc_set (current_cpu, GETTWI (buf));
break;
default :
return 0;
}
return -1; /*FIXME*/
}
/* Cover fns for mach independent register accesses. */
SI
a_i960_h_gr_get (SIM_CPU *current_cpu, UINT regno)
{
switch (MACH_NUM (CPU_MACH (current_cpu)))
{
#ifdef HAVE_CPU_I960BASE
case MACH_I960_KA_SA :
case MACH_I960_CA :
return i960base_h_gr_get (current_cpu, regno);
#endif
default :
abort ();
}
}
void
a_i960_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
{
switch (MACH_NUM (CPU_MACH (current_cpu)))
{
#ifdef HAVE_CPU_I960BASE
case MACH_I960_KA_SA :
case MACH_I960_CA :
i960base_h_gr_set (current_cpu, regno, newval);
break;
#endif
default :
abort ();
}
}
IADDR
a_i960_h_pc_get (SIM_CPU *current_cpu)
{
switch (MACH_NUM (CPU_MACH (current_cpu)))
{
#ifdef HAVE_CPU_I960BASE
case MACH_I960_KA_SA :
case MACH_I960_CA :
return i960base_h_pc_get (current_cpu);
#endif
default :
abort ();
}
}
void
a_i960_h_pc_set (SIM_CPU *current_cpu, IADDR newval)
{
switch (MACH_NUM (CPU_MACH (current_cpu)))
{
#ifdef HAVE_CPU_I960BASE
case MACH_I960_KA_SA :
case MACH_I960_CA :
i960base_h_pc_set (current_cpu, newval);
break;
#endif
default :
abort ();
}
}
#if WITH_PROFILE_MODEL_P
/* FIXME: Some of these should be inline or macros. Later. */
/* Initialize cycle counting for an insn.
FIRST_P is non-zero if this is the first insn in a set of parallel
insns. */
void
i960base_model_insn_before (SIM_CPU *cpu, int first_p)
{
}
/* Record the cycles computed for an insn.
LAST_P is non-zero if this is the last insn in a set of parallel insns,
and we update the total cycle count.
CYCLES is the cycle count of the insn. */
void
i960base_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
{
}
/* Initialize cycle counting for an insn.
FIRST_P is non-zero if this is the first insn in a set of parallel
insns. */
void
i960_model_init_insn_cycles (SIM_CPU *cpu, int first_p)
{
}
/* Record the cycles computed for an insn.
LAST_P is non-zero if this is the last insn in a set of parallel insns,
and we update the total cycle count. */
void
i960_model_update_insn_cycles (SIM_CPU *cpu, int last_p)
{
}
void
i960_model_record_cycles (SIM_CPU *cpu, unsigned long cycles)
{
}
void
i960base_model_mark_get_h_gr (SIM_CPU *cpu, ARGBUF *abuf)
{
}
void
i960base_model_mark_set_h_gr (SIM_CPU *cpu, ARGBUF *abuf)
{
}
#endif /* WITH_PROFILE_MODEL_P */
int
i960base_model_i960KA_u_exec (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced)
{
return idesc->timing->units[unit_num].done;
}
int
i960base_model_i960CA_u_exec (SIM_CPU *cpu, const IDESC *idesc,
int unit_num, int referenced)
{
return idesc->timing->units[unit_num].done;
}

301
sim/i960/mloop.in
View file

@ -1,301 +0,0 @@
# Simulator main loop for i960. -*- C -*-
# Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
#
# This file is part of the GNU Simulators.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2, or (at your option)
# any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License along
# with this program; if not, write to the Free Software Foundation, Inc.,
# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
# Syntax:
# /bin/sh mainloop.in command
#
# Command is one of:
#
# init
# support
# extract-{simple,scache,pbb}
# {full,fast}-exec-{simple,scache,pbb}
#
# A target need only provide a "full" version of one of simple,scache,pbb.
# If the target wants it can also provide a fast version of same.
# It can't provide more than this, however for illustration's sake the M32R
# port provides examples of all.
# ??? After a few more ports are done, revisit.
# Will eventually need to machine generate a lot of this.
case "x$1" in
xsupport)
cat <<EOF
/*static INLINE*/ const IDESC *
extract32 (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn,
ARGBUF *abuf, int fast_p)
{
/* ??? wilson, instructions are 32 bits. */
const IDESC *d = @cpu@_decode (current_cpu, pc, (USI) insn, abuf);
@cpu@_fill_argbuf (current_cpu, abuf, d, pc, fast_p);
if (! fast_p)
{
int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
@cpu@_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
}
return d;
}
#if 0
/*static INLINE*/ const IDESC *
/* ??? wilson, Some instructions are 64 bits. */
extract64 (SIM_CPU *current_cpu, PCADDR pc, insn_t insn,
ARGBUF *abuf, int fast_p)
{
const IDESC *d = @cpu@_decode (current_cpu, pc, (UDI) insn >> 32, abuf);
SEM_SET_CODE (abuf, d, fast_p);
abuf->idesc = d;
abuf->addr = pc;
return d;
}
#endif
static INLINE SEM_PC
execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
{
SEM_PC vpc;
if (fast_p)
{
#if ! WITH_SEM_SWITCH_FAST
#if WITH_SCACHE
vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, sc);
#else
vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, &sc->argbuf);
#endif
#else
abort ();
#endif /* WITH_SEM_SWITCH_FAST */
}
else
{
#if ! WITH_SEM_SWITCH_FULL
ARGBUF *abuf = &sc->argbuf;
const IDESC *idesc = abuf->idesc;
const CGEN_INSN *insn = idesc->idata;
#if WITH_SCACHE_PBB
int virtual_p = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_VIRTUAL);
#else
int virtual_p = 0;
#endif
if (! virtual_p)
{
/* FIXME: call x-before */
if (ARGBUF_PROFILE_P (abuf))
PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num);
/* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}. */
if (PROFILE_MODEL_P (current_cpu))
@cpu@_model_insn_before (current_cpu, 1 /*first_p*/);
TRACE_INSN_INIT (current_cpu, abuf, 1);
TRACE_INSN (current_cpu, insn,
(const struct argbuf *) abuf, abuf->addr);
}
#if WITH_SCACHE
vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc);
#else
vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, abuf);
#endif
if (! virtual_p)
{
/* FIXME: call x-after */
if (PROFILE_MODEL_P (current_cpu))
{
int cycles;
cycles = (*idesc->timing->model_fn) (current_cpu, sc);
@cpu@_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
}
TRACE_INSN_FINI (current_cpu, abuf, 1);
}
#else
abort ();
#endif /* WITH_SEM_SWITCH_FULL */
}
return vpc;
}
EOF
;;
xinit)
cat <<EOF
/*xxxinit*/
EOF
;;
xextract-simple | xextract-scache)
cat <<EOF
{
if ((pc & 3) != 0)
{
abort ();
#if 0
/* This only occurs when single stepping.
The test is unnecessary otherwise, but the cost is teensy,
compared with decoding/extraction. */
UHI insn = GETIMEMUHI (current_cpu, pc);
extract16 (current_cpu, pc, insn & 0x7fff, sc, FAST_P);
#endif
}
else
{
USI insn = GETIMEMUSI (current_cpu, pc);
/* ??? wilson, insns are 32 bits, unless MEMB with displacement, which
has high bit set, bit 12 set, and mode of 5, 12, 13, 14, or 15. */
if (((SI) insn > 0)
|| ! (((insn & 0x3000) == 0x3000)
|| ((insn & 0x3C00) == 0x1400)))
{
extract32 (current_cpu, pc, insn, sc, FAST_P);
}
else
{
UDI llinsn = (((UDI) insn << 32) || GETIMEMUSI (current_cpu, pc+4));
extract64 (current_cpu, pc, llinsn, sc, FAST_P);
}
}
}
EOF
;;
xextract-pbb)
# Inputs: current_cpu, pc, sc, max_insns, FAST_P
# Outputs: sc, pc
# sc must be left pointing past the last created entry.
# pc must be left pointing past the last created entry.
# If the pbb is terminated by a cti insn, SET_CTI_VPC(sc) must be called
# to record the vpc of the cti insn.
# SET_INSN_COUNT(n) must be called to record number of real insns.
cat <<EOF
{
const IDESC *idesc;
int icount = 0;
if ((pc & 3) != 0)
{
abort ();
#if 0
/* This only occurs when single stepping.
The test is unnecessary otherwise, but the cost is teensy,
compared with decoding/extraction. */
UHI insn = GETIMEMUHI (current_cpu, pc);
idesc = extract16 (current_cpu, pc, insn & 0x7fff, &sc->argbuf, FAST_P);
++sc;
--max_insns;
++icount;
pc += 2;
if (IDESC_CTI_P (idesc))
{
SET_CTI_VPC (sc - 1);
goto Finish;
}
#endif
}
while (max_insns > 0)
{
USI insn = GETIMEMUSI (current_cpu, pc);
#if 0
/* ??? wilson, insns are 32 bits, unless MEMB with displacement, which
has high bit set, bit 12 set, and mode of 5, 12, 13, 14, or 15. */
if (((SI) insn > 0)
|| ! (((insn & 0x3000) == 0x3000)
|| ((insn & 0x3C00) == 0x1400)))
{
idesc = extract32 (current_cpu, pc, insn, &sc->argbuf, FAST_P);
++sc;
--max_insns;
++icount;
pc += 4;
if (IDESC_CTI_P (idesc))
{
SET_CTI_VPC (sc - 1);
break;
}
}
else
{
idesc = extract64 (current_cpu, pc, insn, &sc->argbuf, FAST_P);
++sc;
--max_insns;
++icount;
pc += 8;
if (IDESC_CTI_P (idesc))
{
SET_CTI_VPC (sc - 1);
break;
}
}
#else
idesc = extract32 (current_cpu, pc, insn, &sc->argbuf, FAST_P);
++sc;
--max_insns;
++icount;
pc += idesc->length;
if (IDESC_CTI_P (idesc))
{
SET_CTI_VPC (sc - 1);
break;
}
}
#endif
Finish:
SET_INSN_COUNT (icount);
}
EOF
;;
xfull-exec-* | xfast-exec-*)
# Inputs: current_cpu, vpc, FAST_P
# Outputs: vpc
# vpc is the virtual program counter.
cat <<EOF
#if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST)
#define DEFINE_SWITCH
#include "sem-switch.c"
#else
vpc = execute (current_cpu, vpc, FAST_P);
#endif
EOF
;;
*)
echo "Invalid argument to mainloop.in: $1" >&2
exit 1
;;
esac

10065
sim/i960/model.c
View file

File diff suppressed because it is too large Load diff

7345
sim/i960/sem-switch.c
View file

File diff suppressed because it is too large Load diff

7918
sim/i960/sem.c
View file

File diff suppressed because it is too large Load diff

311
sim/i960/sim-if.c
View file

@ -1,311 +0,0 @@
/* Main simulator entry points for the i960.
Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
Contributed by Cygnus Support.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "libiberty.h"
#include "bfd.h"
#include "sim-main.h"
#ifdef HAVE_STDLIB_H
#include <stdlib.h>
#endif
#include "sim-options.h"
#include "dis-asm.h"
static void free_state (SIM_DESC);
/* Since we don't build the cgen-opcode table, we use the old
disassembler. */
static CGEN_DISASSEMBLER i960_disassemble_insn;
/* Records simulator descriptor so utilities like i960_dump_regs can be
called from gdb. */
SIM_DESC current_state;
/* Cover function of sim_state_free to free the cpu buffers as well. */
static void
free_state (SIM_DESC sd)
{
if (STATE_MODULES (sd) != NULL)
sim_module_uninstall (sd);
sim_cpu_free_all (sd);
sim_state_free (sd);
}
/* Create an instance of the simulator. */
SIM_DESC
sim_open (kind, callback, abfd, argv)
SIM_OPEN_KIND kind;
host_callback *callback;
struct bfd *abfd;
char **argv;
{
char c;
int i;
SIM_DESC sd = sim_state_alloc (kind, callback);
/* The cpu data is kept in a separately allocated chunk of memory. */
if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
#if 0 /* FIXME: pc is in mach-specific struct */
/* FIXME: watchpoints code shouldn't need this */
{
SIM_CPU *current_cpu = STATE_CPU (sd, 0);
STATE_WATCHPOINTS (sd)->pc = &(PC);
STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
}
#endif
if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
#if 0 /* FIXME: 'twould be nice if we could do this */
/* These options override any module options.
Obviously ambiguity should be avoided, however the caller may wish to
augment the meaning of an option. */
if (extra_options != NULL)
sim_add_option_table (sd, extra_options);
#endif
/* getopt will print the error message so we just have to exit if this fails.
FIXME: Hmmm... in the case of gdb we need getopt to call
print_filtered. */
if (sim_parse_args (sd, argv) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
/* Allocate a handler for the control registers and other devices
if no memory for that range has been allocated by the user.
All are allocated in one chunk to keep things from being
unnecessarily complicated. */
if (sim_core_read_buffer (sd, NULL, read_map, &c, I960_DEVICE_ADDR, 1) == 0)
sim_core_attach (sd, NULL,
0 /*level*/,
access_read_write,
0 /*space ???*/,
I960_DEVICE_ADDR, I960_DEVICE_LEN /*nr_bytes*/,
0 /*modulo*/,
&i960_devices,
NULL /*buffer*/);
/* Allocate core managed memory if none specified by user.
Use address 4 here in case the user wanted address 0 unmapped. */
if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
/* ??? wilson */
sim_do_commandf (sd, "memory region 0x%lx,0x%lx", I960_DEFAULT_MEM_START,
I960_DEFAULT_MEM_SIZE);
/* check for/establish the reference program image */
if (sim_analyze_program (sd,
(STATE_PROG_ARGV (sd) != NULL
? *STATE_PROG_ARGV (sd)
: NULL),
abfd) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
/* Establish any remaining configuration options. */
if (sim_config (sd) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
if (sim_post_argv_init (sd) != SIM_RC_OK)
{
free_state (sd);
return 0;
}
/* Open a copy of the cpu descriptor table. */
{
CGEN_CPU_DESC cd = i960_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
CGEN_ENDIAN_LITTLE);
for (i = 0; i < MAX_NR_PROCESSORS; ++i)
{
SIM_CPU *cpu = STATE_CPU (sd, i);
CPU_CPU_DESC (cpu) = cd;
CPU_DISASSEMBLER (cpu) = i960_disassemble_insn;
}
}
/* Initialize various cgen things not done by common framework.
Must be done after i960_cgen_cpu_open. */
cgen_init (sd);
/* Store in a global so things like i960_dump_regs can be invoked
from the gdb command line. */
current_state = sd;
return sd;
}
void
sim_close (sd, quitting)
SIM_DESC sd;
int quitting;
{
i960_cgen_cpu_close (CPU_CPU_DESC (STATE_CPU (sd, 0)));
sim_module_uninstall (sd);
}
SIM_RC
sim_create_inferior (sd, abfd, argv, envp)
SIM_DESC sd;
struct bfd *abfd;
char **argv;
char **envp;
{
SIM_CPU *current_cpu = STATE_CPU (sd, 0);
SIM_ADDR addr;
if (abfd != NULL)
addr = bfd_get_start_address (abfd);
else
addr = 0;
sim_pc_set (current_cpu, addr);
#if 0
STATE_ARGV (sd) = sim_copy_argv (argv);
STATE_ENVP (sd) = sim_copy_argv (envp);
#endif
return SIM_RC_OK;
}
#if 0
int
sim_stop (SIM_DESC sd)
{
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_i960_ka_sa :
return i960base_engine_stop (sd, NULL, NULL_CIA, sim_stopped, SIM_SIGINT);
default :
abort ();
}
}
/* This isn't part of the official interface.
This is just a good place to put this for now. */
void
sim_sync_stop (SIM_DESC sd, SIM_CPU *cpu, PCADDR pc, enum sim_stop reason, int sigrc)
{
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_i960_ka_sa :
(void) i960base_engine_stop (sd, cpu, pc, reason, sigrc);
break;
default :
abort ();
}
}
void
sim_resume (sd, step, siggnal)
SIM_DESC sd;
int step, siggnal;
{
sim_module_resume (sd);
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_i960_ka_sa :
i960base_engine_run (sd, step, siggnal);
break;
default :
abort ();
}
sim_module_suspend (sd);
}
#endif
/* The contents of BUF are in target byte order. */
int
sim_fetch_register (sd, rn, buf, length)
SIM_DESC sd;
int rn;
unsigned char *buf;
int length;
{
SIM_CPU *cpu = STATE_CPU (sd, 0);
return (* CPU_REG_FETCH (cpu)) (cpu, rn, buf, length);
}
/* The contents of BUF are in target byte order. */
int
sim_store_register (sd, rn, buf, length)
SIM_DESC sd;
int rn;
unsigned char *buf;
int length;
{
SIM_CPU *cpu = STATE_CPU (sd, 0);
return (* CPU_REG_STORE (cpu)) (cpu, rn, buf, length);
}
void
sim_do_command (sd, cmd)
SIM_DESC sd;
char *cmd;
{
if (sim_args_command (sd, cmd) != SIM_RC_OK)
sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
}
/* Disassemble an instruction. */
static void
i960_disassemble_insn (SIM_CPU *cpu, const CGEN_INSN *insn,
const ARGBUF *abuf, IADDR pc, char *buf)
{
struct disassemble_info disasm_info;
SFILE sfile;
SIM_DESC sd = CPU_STATE (cpu);
int insn_length = CGEN_INSN_BITSIZE (insn) / 8;
sfile.buffer = sfile.current = buf;
INIT_DISASSEMBLE_INFO (disasm_info, (FILE *) &sfile,
(fprintf_ftype) sim_disasm_sprintf);
disasm_info.endian =
(bfd_big_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_BIG
: bfd_little_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_LITTLE
: BFD_ENDIAN_UNKNOWN);
disasm_info.read_memory_func = sim_disasm_read_memory;
disasm_info.memory_error_func = sim_disasm_perror_memory;
disasm_info.application_data = (PTR) cpu;
print_insn_i960 (pc, &disasm_info);
}

69
sim/i960/sim-main.h
View file

@ -1,69 +0,0 @@
/* Main header for the i960. */
#define USING_SIM_BASE_H /* FIXME: quick hack */
struct _sim_cpu; /* FIXME: should be in sim-basics.h */
typedef struct _sim_cpu SIM_CPU;
#include "symcat.h"
#include "sim-basics.h"
#include "cgen-types.h"
#include "i960-desc.h"
#include "i960-opc.h"
#include "arch.h"
/* These must be defined before sim-base.h. */
typedef USI sim_cia;
#define CIA_GET(cpu) 0 /* FIXME:(CPU_CGEN_HW (cpu)->h_pc) */
#define CIA_SET(cpu,val) 0 /* FIXME:(CPU_CGEN_HW (cpu)->h_pc = (val)) */
/* FIXME: Shouldn't be required to define these this early. */
#define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA)
#define SIM_ENGINE_RESTART_HOOK(SD, LAST_CPU, CIA)
#include "sim-base.h"
#include "cgen-sim.h"
#include "i960-sim.h"
/* The _sim_cpu struct. */
struct _sim_cpu {
sim_cpu_base base;
/* Static parts of cgen. */
CGEN_CPU cgen_cpu;
/* CPU specific parts go here.
Note that in files that don't need to access these pieces WANT_CPU_FOO
won't be defined and thus these parts won't appear. This is ok.
One has to of course be careful to not take the size of this
struct and no structure members accessed in non-cpu specific files can
go after here. */
#if defined (WANT_CPU_I960BASE)
I960BASE_CPU_DATA cpu_data;
#endif
};
/* The sim_state struct. */
struct sim_state {
sim_cpu *cpu;
#define STATE_CPU(sd, n) (/*&*/ (sd)->cpu)
CGEN_STATE cgen_state;
sim_state_base base;
};
/* Misc. */
/* Catch address exceptions. */
extern SIM_CORE_SIGNAL_FN i960_core_signal;
#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
i960_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
(TRANSFER), (ERROR))
/* Default memory size. */
/* This value comes from the libgloss/i960/mon960.ld linker script. */
#define I960_DEFAULT_MEM_START 0xa0008000
#define I960_DEFAULT_MEM_SIZE 0x800000 /* 8M */

49
sim/i960/tconfig.in
View file

@ -1,49 +0,0 @@
/* I960 target configuration file. -*- C -*- */
/* See sim-hload.c. We properly handle LMA. */
#define SIM_HANDLES_LMA 1
/* For MSPR support. FIXME: revisit. */
#define WITH_DEVICES 1
/* FIXME: Revisit. */
#ifdef HAVE_DV_SOCKSER
MODULE_INSTALL_FN dv_sockser_install;
#define MODULE_LIST dv_sockser_install,
#endif
#if 0
/* Enable watchpoints. */
#define WITH_WATCHPOINTS 1
#endif
/* ??? Temporary hack until model support unified. */
#define SIM_HAVE_MODEL
/* Define this to enable the intrinsic breakpoint mechanism. */
/* FIXME: may be able to remove SIM_HAVE_BREAKPOINT since it essentially
duplicates ifdef SIM_BREAKPOINT (right?) */
#if 0
#define SIM_HAVE_BREAKPOINTS
#define SIM_BREAKPOINT { 0x10, 0xf1 }
#define SIM_BREAKPOINT_SIZE 2
#endif
/* This is a global setting. Different cpu families can't mix-n-match -scache
and -pbb. However some cpu families may use -simple while others use
one of -scache/-pbb. */
#define WITH_SCACHE_PBB 1
#if 0
/* ??? This was obsoleted by the PBB code. */
/* The semantic code should probably always use a switch().
However, in case that's not possible in some circumstance, we allow
the target to choose. Perhaps this can be autoconf'd on whether the
switch is too big? I can't (yet) think of a reason for allowing the
user to choose, though the developer may certainly wish to. */
#ifdef WANT_CPU_I960BASE
#define WITH_FAST 1
#define WITH_SEM_SWITCH_FULL 0
#define WITH_SEM_SWITCH_FAST 1
#endif
#endif

214
sim/i960/traps.c
View file

@ -1,214 +0,0 @@
/* i960 exception, interrupt, and trap (EIT) support
Copyright (C) 1998, 1999 Free Software Foundation, Inc.
Contributed by Cygnus Solutions.
This file is part of GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "sim-main.h"
#include "targ-vals.h"
/* The semantic code invokes this for illegal (unrecognized) instructions. */
SEM_PC
sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc)
{
SIM_DESC sd = CPU_STATE (current_cpu);
#if 0
if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
{
h_bsm_set (current_cpu, h_sm_get (current_cpu));
h_bie_set (current_cpu, h_ie_get (current_cpu));
h_bcond_set (current_cpu, h_cond_get (current_cpu));
/* sm not changed */
h_ie_set (current_cpu, 0);
h_cond_set (current_cpu, 0);
h_bpc_set (current_cpu, cia);
sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
EIT_RSVD_INSN_ADDR);
}
else
#endif
sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
return vpc;
}
/* Process an address exception. */
void
i960_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
unsigned int map, int nr_bytes, address_word addr,
transfer_type transfer, sim_core_signals sig)
{
#if 0
if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
{
h_bsm_set (current_cpu, h_sm_get (current_cpu));
h_bie_set (current_cpu, h_ie_get (current_cpu));
h_bcond_set (current_cpu, h_cond_get (current_cpu));
/* sm not changed */
h_ie_set (current_cpu, 0);
h_cond_set (current_cpu, 0);
h_bpc_set (current_cpu, cia);
sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
EIT_ADDR_EXCP_ADDR);
}
else
#endif
sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr,
transfer, sig);
}
/* Read/write functions for system call interface. */
static int
syscall_read_mem (host_callback *cb, struct cb_syscall *sc,
unsigned long taddr, char *buf, int bytes)
{
SIM_DESC sd = (SIM_DESC) sc->p1;
SIM_CPU *cpu = (SIM_CPU *) sc->p2;
return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes);
}
static int
syscall_write_mem (host_callback *cb, struct cb_syscall *sc,
unsigned long taddr, const char *buf, int bytes)
{
SIM_DESC sd = (SIM_DESC) sc->p1;
SIM_CPU *cpu = (SIM_CPU *) sc->p2;
return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);
}
/* Trap support.
The result is the pc address to continue at.
Preprocessing like saving the various registers has already been done. */
USI
i960_trap (SIM_CPU *current_cpu, PCADDR pc, int num)
{
SIM_DESC sd = CPU_STATE (current_cpu);
host_callback *cb = STATE_CALLBACK (sd);
#ifdef SIM_HAVE_BREAKPOINTS
/* Check for breakpoints "owned" by the simulator first, regardless
of --environment. */
if (num == TRAP_BREAKPOINT)
{
/* First try sim-break.c. If it's a breakpoint the simulator "owns"
it doesn't return. Otherwise it returns and let's us try. */
sim_handle_breakpoint (sd, current_cpu, pc);
/* Fall through. */
}
#endif
#if 0
/* ??? wilson, don't know what this does. */
if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
{
/* The new pc is the trap vector entry.
We assume there's a branch there to some handler. */
USI new_pc = EIT_TRAP_BASE_ADDR + num * 4;
return new_pc;
}
#endif
switch (num)
{
default:
case TRAP_SYSCALL :
{
CB_SYSCALL s;
CB_SYSCALL_INIT (&s);
s.func = num;
s.arg1 = a_i960_h_gr_get (current_cpu, 16);
s.arg2 = a_i960_h_gr_get (current_cpu, 17);
s.arg3 = a_i960_h_gr_get (current_cpu, 18);
if (s.func == TARGET_SYS_exit)
{
sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1);
}
s.p1 = (PTR) sd;
s.p2 = (PTR) current_cpu;
s.read_mem = syscall_read_mem;
s.write_mem = syscall_write_mem;
cb_syscall (cb, &s);
/* ??? This stuff is probably wrong, but libgloss doesn't look at
these values, so it shouldn't matter. */
a_i960_h_gr_set (current_cpu, 18, s.errcode);
a_i960_h_gr_set (current_cpu, 16, s.result);
a_i960_h_gr_set (current_cpu, 17, s.result2);
break;
}
case TRAP_BREAKPOINT:
sim_engine_halt (sd, current_cpu, NULL, NULL_CIA,
sim_stopped, SIM_SIGTRAP);
break;
#if 0
/* ??? wilson, don't know what this does. */
default :
{
USI new_pc = EIT_TRAP_BASE_ADDR + num * 4;
return new_pc;
}
#endif
}
/* Fake an "rte" insn. */
/* FIXME: Should duplicate all of rte processing. */
return (pc & -4) + 4;
}
/* Breakpoint support.
The result is the pc address to continue at. */
/* ??? This is an editted copy of the above. */
USI
i960_breakpoint (SIM_CPU *current_cpu, PCADDR pc)
{
SIM_DESC sd = CPU_STATE (current_cpu);
host_callback *cb = STATE_CALLBACK (sd);
#ifdef SIM_HAVE_BREAKPOINTS
/* Check for breakpoints "owned" by the simulator first, regardless
of --environment. */
if (num == TRAP_BREAKPOINT)
{
/* First try sim-break.c. If it's a breakpoint the simulator "owns"
it doesn't return. Otherwise it returns and let's us try. */
sim_handle_breakpoint (sd, current_cpu, pc);
/* Fall through. */
}
#endif
sim_engine_halt (sd, current_cpu, NULL, NULL_CIA,
sim_stopped, SIM_SIGTRAP);
/* Fake an "rte" insn. */
/* FIXME: Should duplicate all of rte processing. */
return (pc & -4) + 4;
}