Add support for relaxing the 32bit ldc/stc instructions.
This commit is contained in:
Nick Clifton
parent
a8a3b3b21c
commit
3255318a04
10 changed files with 194 additions and 7 deletions
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@ -1,3 +1,8 @@
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2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
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* coff-h8300.c: Added comments about relaxation for ldc.w and stc.w.
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* elf32-h8300.c: Likewise.
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2004-02-09 Christian Vogel <vogelchr@vogel.cx>
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Nick Clifton <nickc@redhat.com>
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@ -780,8 +780,8 @@ h8300_reloc16_extra_cases (bfd *abfd, struct bfd_link_info *link_info,
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instructions:
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"band", "bclr", "biand", "bild", "bior", "bist", "bixor",
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"bld", "bnot", "bor", "bset", "bst", "btst", "bxor", and
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"mov.[bwl]"
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"bld", "bnot", "bor", "bset", "bst", "btst", "bxor", "ldc.w",
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"stc.w" and "mov.[bwl]"
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We may relax this into an 16-bit absolute address if it's in
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the right range. */
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@ -1198,7 +1198,7 @@ elf32_h8_relax_section (bfd *abfd, asection *sec,
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"band", "bclr", "biand", "bild", "bior", "bist",
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"bixor", "bld", "bnot", "bor", "bset", "bst", "btst",
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"bxor", and "mov.[bwl]"
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"bxor", "ldc.w", "stc.w" and "mov.[bwl]"
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We may relax this into an 16-bit absolute address if it's
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in the right range. */
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@ -1,3 +1,7 @@
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2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
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* h8300.h (32bit ldc/stc): Add relaxing support.
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2004-01-12 Anil Paranjpe <anilp1@KPITCummins.com>
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* h8300.h (BITOP): Pass MEMRELAX flag.
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@ -1434,8 +1434,9 @@ struct h8_opcode h8_opcodes[] =
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{O (O_LDC, SW), AV_H8S, 2, "ldc", {{DISP32SRC, EXR | DST, E}}, {{PREFIXLDC, 0x7, 0x8, B30 | DISPREG, 0x0, 0x6, 0xB, 0x2, IGNORE, SRC | DISP32LIST, E}}},
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{O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS16SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, IGNORE, SRC | ABS16LIST, E}}},
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{O (O_LDC, SW), AV_H8S, 2, "ldc", {{ABS16SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x0, IGNORE, SRC | ABS16LIST, E}}},
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{O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | ABS32LIST, E}}},
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{O (O_LDC, SW), AV_H8S, 2, "ldc", {{ABS32SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | ABS32LIST, E}}},
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{O (O_LDC, SW), AV_H8H, 2, "ldc", {{ABS32SRC, CCR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | MEMRELAX | ABS32LIST, E}}},
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{O (O_LDC, SW), AV_H8S, 2, "ldc", {{ABS32SRC, EXR | DST, E}}, {{PREFIXLDC, 0x6, 0xB, 0x2, IGNORE, SRC | MEMRELAX | ABS32LIST, E}}},
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{O (O_LDC, SL), AV_H8SX, 0, "ldc", {{RS32, B30 | VBR_SBR | DST, E}}, {{0x0, 0x3, B30 | VBR_SBR | DST, RS32, E}}},
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@ -1809,8 +1810,8 @@ struct h8_opcode h8_opcodes[] =
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{O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, DISP32DST, E}}, {{PREFIXSTC, 0x7, 0x8, B30 | DSTDISPREG, 0, 0x6, 0xB, 0xA, IGNORE, DSTDISP32LIST, E}}},
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{O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, ABS16DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0x8, IGNORE, DST | ABS16LIST, E}}},
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{O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, ABS16DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0x8, IGNORE, DST | ABS16LIST, E}}},
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{O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, ABS32DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | ABS32LIST, E}}},
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{O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, ABS32DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | ABS32LIST, E}}},
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{O (O_STC, SW), AV_H8H, 2, "stc", {{CCR | SRC, ABS32DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | MEMRELAX | ABS32LIST, E}}},
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{O (O_STC, SW), AV_H8S, 2, "stc", {{EXR | SRC, ABS32DST, E}}, {{PREFIXSTC, 0x6, 0xB, 0xA, IGNORE, DST | MEMRELAX | ABS32LIST, E}}},
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{O (O_STC, SL), AV_H8SX, 0, "stc", {{B30 | VBR_SBR | SRC, RD32, E}}, {{0x0, 0x2, B30 | VBR_SBR | SRC, RD32, E}}},
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@ -1,3 +1,12 @@
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2004-02-09 Anil Paranjpe <anilp1@KPITCummins.com>
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* ld-h8300/relax-5.s: New file: Source for relax-5 test.
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* ld-h8300/relax-5.d: New file: Expected output and commands for
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assembling and linking the relax-5 test.
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* ld-h8300/relax-5-coff.d: New file: Variant for the COFF based
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toolchain.
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* ld-h8300/h8300-exp: Run the relax-5 test.
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2004-01-23 Daniel Jacobowitz <drow@mvista.com>
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* ld-arm/arm-app-abs32.s, ld-arm/arm-app-abs32.r,
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@ -30,7 +30,9 @@ if {[istarget *-elf]} {
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run_dump_test relax-2
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run_dump_test relax-3
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run_dump_test relax-4
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run_dump_test relax-5
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} else {
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run_dump_test relax-3-coff
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run_dump_test relax-4-coff
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run_dump_test relax-5-coff
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}
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50
ld/testsuite/ld-h8300/relax-5-coff.d
Normal file
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ld/testsuite/ld-h8300/relax-5-coff.d
Normal file
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@ -0,0 +1,50 @@
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# name: H8300 Relaxation Test 5
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# source: relax-5.s
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# ld: --relax -m h8300s
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# objdump: -d --no-show-raw-insn
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.*: file format .*-h8300
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Disassembly of section .text:
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00000100 <_start>:
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100: 01 40 6b 00 00 00 ldc @0x0:16,ccr
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106: 01 40 6b 00 7f ff ldc @0x7fff:16,ccr
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10c: 01 40 6b 20 00 00 80 00 ldc @0x8000:32,ccr
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114: 01 40 6b 20 00 00 ff 00 ldc @0xff00:32,ccr
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11c: 01 40 6b 20 00 ff ff 00 ldc @0xffff00:32,ccr
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124: 01 40 6b 20 ff ff 7f ff ldc @0xffff7fff:32,ccr
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12c: 01 40 6b 00 80 00 ldc @0x8000:16,ccr
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132: 01 40 6b 00 fe ff ldc @0xfeff:16,ccr
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138: 01 40 6b 00 ff 00 ldc @0xff00:16,ccr
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13e: 01 40 6b 00 ff ff ldc @0xffff:16,ccr
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144: 01 40 6b 80 00 00 stc ccr,@0x0:16
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14a: 01 40 6b 80 7f ff stc ccr,@0x7fff:16
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150: 01 40 6b a0 00 00 80 00 stc ccr,@0x8000:32
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158: 01 40 6b a0 00 00 ff 00 stc ccr,@0xff00:32
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160: 01 40 6b a0 00 ff ff 00 stc ccr,@0xffff00:32
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168: 01 40 6b a0 ff ff 7f ff stc ccr,@0xffff7fff:32
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170: 01 40 6b 80 80 00 stc ccr,@0x8000:16
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176: 01 40 6b 80 fe ff stc ccr,@0xfeff:16
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17c: 01 40 6b 80 ff 00 stc ccr,@0xff00:16
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182: 01 40 6b 80 ff ff stc ccr,@0xffff:16
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188: 01 41 6b 00 00 00 ldc @0x0:16,exr
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18e: 01 41 6b 00 7f ff ldc @0x7fff:16,exr
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194: 01 41 6b 20 00 00 80 00 ldc @0x8000:32,exr
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19c: 01 41 6b 20 00 00 ff 00 ldc @0xff00:32,exr
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1a4: 01 41 6b 20 00 ff ff 00 ldc @0xffff00:32,exr
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1ac: 01 41 6b 20 ff ff 7f ff ldc @0xffff7fff:32,exr
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1b4: 01 41 6b 00 80 00 ldc @0x8000:16,exr
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1ba: 01 41 6b 00 fe ff ldc @0xfeff:16,exr
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1c0: 01 41 6b 00 ff 00 ldc @0xff00:16,exr
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1c6: 01 41 6b 00 ff ff ldc @0xffff:16,exr
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1cc: 01 41 6b 80 00 00 stc exr,@0x0:16
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1d2: 01 41 6b 80 7f ff stc exr,@0x7fff:16
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1d8: 01 41 6b a0 00 00 80 00 stc exr,@0x8000:32
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1e0: 01 41 6b a0 00 00 ff 00 stc exr,@0xff00:32
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1e8: 01 41 6b a0 00 ff ff 00 stc exr,@0xffff00:32
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1f0: 01 41 6b a0 ff ff 7f ff stc exr,@0xffff7fff:32
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1f8: 01 41 6b 80 80 00 stc exr,@0x8000:16
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1fe: 01 41 6b 80 fe ff stc exr,@0xfeff:16
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204: 01 41 6b 80 ff 00 stc exr,@0xff00:16
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20a: 01 41 6b 80 ff ff stc exr,@0xffff:16
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50
ld/testsuite/ld-h8300/relax-5.d
Normal file
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ld/testsuite/ld-h8300/relax-5.d
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@ -0,0 +1,50 @@
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# name: H8300 Relaxation Test 5
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# source: relax-5.s
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# ld: --relax -m h8300self
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# objdump: -d --no-show-raw-insn
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.*: file format .*-h8300
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Disassembly of section .text:
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00000100 <_start>:
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100: 01 40 6b 00 00 00 ldc @0x0:16,ccr
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106: 01 40 6b 00 7f ff ldc @0x7fff:16,ccr
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10c: 01 40 6b 20 00 00 80 00 ldc @0x8000:32,ccr
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114: 01 40 6b 20 00 00 ff 00 ldc @0xff00:32,ccr
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11c: 01 40 6b 20 00 ff ff 00 ldc @0xffff00:32,ccr
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124: 01 40 6b 20 ff ff 7f ff ldc @0xffff7fff:32,ccr
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12c: 01 40 6b 00 80 00 ldc @0x8000:16,ccr
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132: 01 40 6b 00 fe ff ldc @0xfeff:16,ccr
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138: 01 40 6b 00 ff 00 ldc @0xff00:16,ccr
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13e: 01 40 6b 00 ff ff ldc @0xffff:16,ccr
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144: 01 40 6b 80 00 00 stc ccr,@0x0:16
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14a: 01 40 6b 80 7f ff stc ccr,@0x7fff:16
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150: 01 40 6b a0 00 00 80 00 stc ccr,@0x8000:32
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158: 01 40 6b a0 00 00 ff 00 stc ccr,@0xff00:32
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160: 01 40 6b a0 00 ff ff 00 stc ccr,@0xffff00:32
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168: 01 40 6b a0 ff ff 7f ff stc ccr,@0xffff7fff:32
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170: 01 40 6b 80 80 00 stc ccr,@0x8000:16
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176: 01 40 6b 80 fe ff stc ccr,@0xfeff:16
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17c: 01 40 6b 80 ff 00 stc ccr,@0xff00:16
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182: 01 40 6b 80 ff ff stc ccr,@0xffff:16
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188: 01 41 6b 00 00 00 ldc @0x0:16,exr
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18e: 01 41 6b 00 7f ff ldc @0x7fff:16,exr
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194: 01 41 6b 20 00 00 80 00 ldc @0x8000:32,exr
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19c: 01 41 6b 20 00 00 ff 00 ldc @0xff00:32,exr
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1a4: 01 41 6b 20 00 ff ff 00 ldc @0xffff00:32,exr
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1ac: 01 41 6b 20 ff ff 7f ff ldc @0xffff7fff:32,exr
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1b4: 01 41 6b 00 80 00 ldc @0x8000:16,exr
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1ba: 01 41 6b 00 fe ff ldc @0xfeff:16,exr
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1c0: 01 41 6b 00 ff 00 ldc @0xff00:16,exr
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1c6: 01 41 6b 00 ff ff ldc @0xffff:16,exr
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1cc: 01 41 6b 80 00 00 stc exr,@0x0:16
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1d2: 01 41 6b 80 7f ff stc exr,@0x7fff:16
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1d8: 01 41 6b a0 00 00 80 00 stc exr,@0x8000:32
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1e0: 01 41 6b a0 00 00 ff 00 stc exr,@0xff00:32
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1e8: 01 41 6b a0 00 ff ff 00 stc exr,@0xffff00:32
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1f0: 01 41 6b a0 ff ff 7f ff stc exr,@0xffff7fff:32
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1f8: 01 41 6b 80 80 00 stc exr,@0x8000:16
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1fe: 01 41 6b 80 fe ff stc exr,@0xfeff:16
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204: 01 41 6b 80 ff 00 stc exr,@0xff00:16
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20a: 01 41 6b 80 ff ff stc exr,@0xffff:16
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66
ld/testsuite/ld-h8300/relax-5.s
Normal file
66
ld/testsuite/ld-h8300/relax-5.s
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@ -0,0 +1,66 @@
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; Relaxation is possible from @aa:32 to @aa:16 for following instructions
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; ldc.w @@aa:32,ccr
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; stc.w ccr,@@aa:32
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; ldc.w @aa:32,exr
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; stc.w exr,@aa:32
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.h8300s
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.globl _start
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;
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; Relaxation of aa:32
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;
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_start:
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ldc @s1:32,ccr
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ldc @s2:32,ccr
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ldc @s3:32,ccr
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ldc @s4:32,ccr
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ldc @s5:32,ccr
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ldc @s6:32,ccr
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ldc @s7:32,ccr
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ldc @s8:32,ccr
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ldc @s9:32,ccr
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ldc @s10:32,ccr
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stc ccr,@s1:32
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stc ccr,@s2:32
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stc ccr,@s3:32
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stc ccr,@s4:32
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stc ccr,@s5:32
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stc ccr,@s6:32
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stc ccr,@s7:32
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stc ccr,@s8:32
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stc ccr,@s9:32
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stc ccr,@s10:32
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ldc @s1:32,exr
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ldc @s2:32,exr
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ldc @s3:32,exr
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ldc @s4:32,exr
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ldc @s5:32,exr
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ldc @s6:32,exr
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ldc @s7:32,exr
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ldc @s8:32,exr
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ldc @s9:32,exr
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ldc @s10:32,exr
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stc exr,@s1:32
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stc exr,@s2:32
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stc exr,@s3:32
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stc exr,@s4:32
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stc exr,@s5:32
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stc exr,@s6:32
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stc exr,@s7:32
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stc exr,@s8:32
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stc exr,@s9:32
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stc exr,@s10:32
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.equ s1,0
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.equ s2,0x7fff
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.equ s3,0x8000
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.equ s4,0xff00
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.equ s5,0xffff00
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.equ s6,0xffff7fff
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.equ s7,0xffff8000
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.equ s8,0xfffffeff
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.equ s9,0xffffff00
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.equ s10,0xffffffff
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.end
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