gas:
2000-08-08 Jason Eckhardt <jle@cygnus.com> * config/tc-i860.h: Rework completely for BFD_ASSEMBLER. (i860_fix_info): New enum. (MD_APPLY_FIX3): Define. (WORKING_DOT_WORD): Define. (TC_HANDLES_FX_DONE): Define. (DIFF_EXPR_OK): Define. (LISTING_HEADER): Define. (TARGET_FORMAT): Select target format based on endian flag. (TARGET_BYTES_BIG_ENDIAN): Default to little endian. (target_big_endian): Add external declaration. * config/tc-i860.c: All existing code reworked completely. Other new code shown below. (SYNTAX_SVR4): Define. (target_warn_expand): New variable. (md_shortopts): Declare and define (-Qy, -Qn, and -V options). (md_longopts): Declare and define with new options (-EL, -EB, and -mwarn-expand). (md_show_usage): New function. (md_operand): New function. (obtain_reloc_for_imm16): New function. (md_apply_fix3): New function. (tc_gen_reloc): New function. include: 2000-08-08 Jason Eckhardt <jle@cygnus.com> * opcode/i860.h: Small formatting adjustments. opcode: 2000-08-08 Jason Eckhardt <jle@cygnus.com> * i860-dis.c (print_br_address): Change third argument from int to long. bfd: 2000-08-08 Jason Eckhardt <jle@cygnus.com> * elf32-i860.c (elf32_i860_howto_table): Updated some fields.
This commit is contained in:
Jason Eckhardt
parent
e374f1d977
commit
305d537e30
8 changed files with 913 additions and 697 deletions
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@ -1,3 +1,7 @@
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2000-08-08 Jason Eckhardt <jle@cygnus.com>
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* elf32-i860.c (elf32_i860_howto_table): Updated some fields.
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2000-08-07 Kazu Hirata <kazu@hxi.com>
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* ieee.c (ieee_write_debug_part): Rewrite a comment.
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@ -166,8 +166,8 @@ static reloc_howto_type elf32_i860_howto_table [] =
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bfd_elf_generic_reloc, /* special_function */
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"R_860_PC16", /* name */
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false, /* partial_inplace */
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0xffff, /* src_mask */
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0xffff, /* dst_mask */
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0x1f07ff, /* src_mask */
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0x1f07ff, /* dst_mask */
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true), /* pcrel_offset */
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HOWTO (R_860_LOW0, /* type */
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@ -222,8 +222,8 @@ static reloc_howto_type elf32_i860_howto_table [] =
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bfd_elf_generic_reloc, /* special_function */
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"R_860_SPLIT1", /* name */
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false, /* partial_inplace */
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0x1f07ff, /* src_mask */
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0x1f07ff, /* dst_mask */
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0x1f07fe, /* src_mask */
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0x1f07fe, /* dst_mask */
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false), /* pcrel_offset */
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HOWTO (R_860_LOW2, /* type */
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@ -250,8 +250,8 @@ static reloc_howto_type elf32_i860_howto_table [] =
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bfd_elf_generic_reloc, /* special_function */
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"R_860_SPLIT2", /* name */
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false, /* partial_inplace */
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0x1f07ff, /* src_mask */
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0x1f07ff, /* dst_mask */
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0x1f07fc, /* src_mask */
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0x1f07fc, /* dst_mask */
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false), /* pcrel_offset */
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HOWTO (R_860_LOW3, /* type */
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@ -1,3 +1,29 @@
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2000-08-08 Jason Eckhardt <jle@cygnus.com>
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* config/tc-i860.h: Rework completely for BFD_ASSEMBLER.
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(i860_fix_info): New enum.
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(MD_APPLY_FIX3): Define.
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(WORKING_DOT_WORD): Define.
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(TC_HANDLES_FX_DONE): Define.
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(DIFF_EXPR_OK): Define.
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(LISTING_HEADER): Define.
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(TARGET_FORMAT): Select target format based on endian flag.
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(TARGET_BYTES_BIG_ENDIAN): Default to little endian.
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(target_big_endian): Add external declaration.
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* config/tc-i860.c: All existing code reworked completely. Other
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new code shown below.
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(SYNTAX_SVR4): Define.
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(target_warn_expand): New variable.
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(md_shortopts): Declare and define (-Qy, -Qn, and -V options).
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(md_longopts): Declare and define with new options (-EL, -EB,
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and -mwarn-expand).
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(md_show_usage): New function.
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(md_operand): New function.
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(obtain_reloc_for_imm16): New function.
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(md_apply_fix3): New function.
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(tc_gen_reloc): New function.
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2000-08-09 Kazu Hirata <kazu@hxi.com>
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* hash.c: Fix formatting.
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1423
gas/config/tc-i860.c
1423
gas/config/tc-i860.c
File diff suppressed because it is too large
Load diff
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@ -1,5 +1,9 @@
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/* tc-i860.h -- Header file for the I860
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Copyright (C) 1991, 92, 95, 1998 Free Software Foundation, Inc.
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/* tc-i860.h -- Header file for the i860.
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Copyright (C) 1991, 1992, 1995, 1998, 2000
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Free Software Foundation, Inc.
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Brought back from the dead and completely reworked
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by Jason Eckhardt <jle@cygnus.com>.
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This file is part of GAS, the GNU Assembler.
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@ -17,23 +21,68 @@
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with GAS; see the file COPYING. If not, write to the Free Software
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Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#ifndef TC_I860
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#define TC_I860 1
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#define TARGET_BYTES_BIG_ENDIAN 1
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#ifndef BFD_ASSEMBLER
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#error i860 support requires BFD_ASSEMBLER
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#endif
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enum i860_fix_info
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{
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OP_NONE = 0x00000,
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OP_IMM_U5 = 0x00001,
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OP_IMM_S16 = 0x00002,
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OP_IMM_U16 = 0x00004,
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OP_IMM_SPLIT16 = 0x00008,
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OP_IMM_BR26 = 0x00010,
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OP_IMM_BR16 = 0x00020,
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OP_ENCODE1 = 0x00040,
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OP_ENCODE2 = 0x00080,
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OP_ENCODE3 = 0x00100,
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OP_SEL_HA = 0x00200,
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OP_SEL_H = 0x00400,
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OP_SEL_L = 0x00800,
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OP_SEL_GOT = 0x01000,
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OP_SEL_GOTOFF = 0x02000,
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OP_SEL_PLT = 0x04000,
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OP_ALIGN2 = 0x08000,
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OP_ALIGN4 = 0x10000,
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OP_ALIGN8 = 0x20000,
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OP_ALIGN16 = 0x40000
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};
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/* Set the endianness we are using. Default to little endian. */
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#ifndef TARGET_BYTES_BIG_ENDIAN
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#define TARGET_BYTES_BIG_ENDIAN 0
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#endif
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/* Whether or not the target is big endian. */
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extern int target_big_endian;
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/* BFD target architecture. */
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#define TARGET_ARCH bfd_arch_i860
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/* The target BFD format. */
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#ifdef OBJ_ELF
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#define TARGET_FORMAT (target_big_endian ? "elf32-i860" : "elf32-i860-little")
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#else
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#error i860 GAS currently supports only the ELF object format
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#endif
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#define WORKING_DOT_WORD
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#define MD_APPLY_FIX3
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#define TC_HANDLES_FX_DONE
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#define DIFF_EXPR_OK
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#define tc_headers_hook(a) {;} /* not used */
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#define tc_crawl_symbol_chain(a) {;} /* not used */
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#define tc_aout_pre_write_hook(x) {;} /* not used */
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/* Permit temporary numeric labels. */
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#define LOCAL_LABELS_FB 1
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#define LISTING_HEADER "GAS for i860"
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#define md_operand(x)
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#define md_convert_frag(b,s,f) as_fatal (_("i860_convert_frag\n"));
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/*
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* Local Variables:
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* comment-column: 0
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* fill-column: 131
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* End:
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*/
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#endif /* TC_I860 */
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/* end of tc-i860.h */
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@ -1,3 +1,7 @@
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2000-08-08 Jason Eckhardt <jle@cygnus.com>
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* opcode/i860.h: Small formatting adjustments.
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2000-07-29 Nick Clifton <nickc@cygnus.com>
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* os9k.h: Add copyright notice.
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@ -15,32 +15,36 @@ GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GAS or GDB; see the file COPYING. If not, write to
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the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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the Free Software Foundation, 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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#if !defined(__STDC__) && !defined(const)
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#define const
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#endif
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/*
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* Structure of an opcode table entry.
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*/
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/* Structure of an opcode table entry. */
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struct i860_opcode
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{
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/* The opcode name. */
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const char *name;
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unsigned long match; /* Bits that must be set. */
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unsigned long lose; /* Bits that must not be set. */
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/* Bits that must be set. */
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unsigned long match;
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/* Bits that must not be set. */
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unsigned long lose;
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const char *args;
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/* Nonzero if this is a possible expand-instruction. */
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char expand;
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};
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enum expand_type
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{
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E_MOV = 1, E_ADDR, E_U32, E_AND, E_S32, E_DELAY
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};
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/*
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All i860 opcodes are 32 bits, except for the pseudoinstructions
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/* All i860 opcodes are 32 bits, except for the pseudo-instructions
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and the operations utilizing a 32-bit address expression, an
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unsigned 32-bit constant, or a signed 32-bit constant.
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These opcodes are expanded into a two-instruction sequence for
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@ -83,21 +87,18 @@ Kinds of operands:
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U split 16 bit immediate, aligned 2^2. (st.l)
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e src1 floating point register.
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f src2 floating point register.
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g dest floating point register.
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g dest floating point register. */
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*/
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/* The order of the opcodes in this table is significant:
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/* The order of the opcodes in this table is significant. The assembler
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requires that all instances of the same mnemonic must be consecutive.
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If they aren't, the assembler will not function properly.
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* The assembler requires that all instances of the same mnemonic must be
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consecutive. If they aren't, the assembler will bomb at runtime.
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* The disassembler should not care about the order of the opcodes. */
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The order of opcodes does not affect the disassembler. */
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static struct i860_opcode i860_opcodes[] =
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{
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/* REG-Format Instructions */
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/* REG-Format Instructions. */
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{ "ld.c", 0x30000000, 0xcc000000, "c,d", 0 }, /* ld.c csrc2,idest */
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{ "ld.b", 0x00000000, 0xfc000000, "1(2),d", 0 }, /* ld.b isrc1(isrc2),idest */
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{ "ld.b", 0x04000000, 0xf8000000, "I(2),d", E_ADDR }, /* ld.b #const(isrc2),idest */
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@ -212,7 +213,7 @@ static struct i860_opcode i860_opcodes[] =
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{ "bnc", 0x78000000, 0x84000000, "l", 0 }, /* bnc lbroff */
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{ "bnc.t", 0x7c000000, 0x80000000, "l", E_DELAY }, /* bnc.t lbroff */
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/* Floating Point Escape Instruction Format - pfam.p fsrc1,fsrc2,fdest */
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/* Floating Point Escape Instruction Format - pfam.p fsrc1,fsrc2,fdest. */
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{ "r2p1.ss", 0x48000400, 0xb40001ff, "e,f,g", 0 },
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{ "r2p1.sd", 0x48000480, 0xb400017f, "e,f,g", 0 },
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{ "r2p1.dd", 0x48000580, 0xb400007f, "e,f,g", 0 },
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@ -262,7 +263,7 @@ static struct i860_opcode i860_opcodes[] =
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{ "m12tpa.sd", 0x4800048f, 0xb4000170, "e,f,g", 0 },
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{ "m12tpa.dd", 0x4800058f, 0xb4000070, "e,f,g", 0 },
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/* Floating Point Escape Instruction Format - pfsm.p fsrc1,fsrc2,fdest */
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/* Floating Point Escape Instruction Format - pfsm.p fsrc1,fsrc2,fdest. */
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{ "r2s1.ss", 0x48000410, 0xb40001ef, "e,f,g", 0 },
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{ "r2s1.sd", 0x48000490, 0xb400016f, "e,f,g", 0 },
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{ "r2s1.dd", 0x48000590, 0xb400006f, "e,f,g", 0 },
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@ -312,7 +313,7 @@ static struct i860_opcode i860_opcodes[] =
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{ "m12tsa.sd", 0x4800049f, 0xb4000160, "e,f,g", 0 },
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{ "m12tsa.dd", 0x4800059f, 0xb4000060, "e,f,g", 0 },
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/* Floating Point Escape Instruction Format - pfmam.p fsrc1,fsrc2,fdest */
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/* Floating Point Escape Instruction Format - pfmam.p fsrc1,fsrc2,fdest. */
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{ "mr2p1.ss", 0x48000000, 0xb40005ff, "e,f,g", 0 },
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{ "mr2p1.sd", 0x48000080, 0xb400057f, "e,f,g", 0 },
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{ "mr2p1.dd", 0x48000180, 0xb400047f, "e,f,g", 0 },
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@ -359,7 +360,7 @@ static struct i860_opcode i860_opcodes[] =
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{ "mim1p2.sd", 0x4800008e, 0xb4000571, "e,f,g", 0 },
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{ "mim1p2.dd", 0x4800018e, 0xb4000471, "e,f,g", 0 },
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/* Floating Point Escape Instruction Format - pfmsm.p fsrc1,fsrc2,fdest */
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/* Floating Point Escape Instruction Format - pfmsm.p fsrc1,fsrc2,fdest. */
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{ "mr2s1.ss", 0x48000010, 0xb40005ef, "e,f,g", 0 },
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{ "mr2s1.sd", 0x48000090, 0xb400056f, "e,f,g", 0 },
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{ "mr2s1.dd", 0x48000190, 0xb400046f, "e,f,g", 0 },
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@ -406,7 +407,6 @@ static struct i860_opcode i860_opcodes[] =
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{ "mim1s2.sd", 0x4800009e, 0xb4000561, "e,f,g", 0 },
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{ "mim1s2.dd", 0x4800019e, 0xb4000461, "e,f,g", 0 },
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{ "fmul.ss", 0x48000020, 0xb40005df, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */
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{ "fmul.sd", 0x480000a0, 0xb400055f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */
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{ "fmul.dd", 0x480001a0, 0xb400045f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */
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@ -447,10 +447,10 @@ static struct i860_opcode i860_opcodes[] =
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{ "pfamov.ds", 0x48000533, 0xb40000cc, "e,g", 0 }, /* pfamov.p fsrc1,fdest */
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{ "pfamov.sd", 0x480004b3, 0xb400014c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */
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{ "pfamov.dd", 0x480005b3, 0xb400004c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */
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/* pfgt has R bit cleared; pfle has R bit set */
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/* Opcode pfgt has R bit cleared; pfle has R bit set. */
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{ "pfgt.ss", 0x48000434, 0xb40001cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */
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{ "pfgt.dd", 0x48000534, 0xb40000cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */
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/* pfgt has R bit cleared; pfle has R bit set */
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/* Opcode pfgt has R bit cleared; pfle has R bit set. */
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{ "pfle.ss", 0x480004b4, 0xb400014b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */
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{ "pfle.dd", 0x480005b4, 0xb400004b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */
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{ "pfeq.ss", 0x48000435, 0xb40001ca, "e,f,g", 0 }, /* pfeq.p fsrc1,fsrc2,fdest */
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@ -481,7 +481,7 @@ static struct i860_opcode i860_opcodes[] =
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{ "form", 0x480001da, 0xb4000425, "e,g", 0 }, /* form fsrc1,fdest */
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{ "pform", 0x480005da, 0xb4000025, "e,g", 0 }, /* pform fsrc1,fdest */
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/* Floating point pseudo-instructions */
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/* Floating point pseudo-instructions. */
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{ "fmov.ss", 0x48000049, 0xb7e005b6, "e,g", 0 }, /* fiadd.ss fsrc1,f0,fdest */
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{ "fmov.dd", 0x480001c9, 0xb7e00436, "e,g", 0 }, /* fiadd.dd fsrc1,f0,fdest */
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{ "fmov.sd", 0x480000b0, 0xb7e0054f, "e,g", 0 }, /* fadd.sd fsrc1,f0,fdest */
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@ -44,7 +44,7 @@ static const char *const crnames[] =
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/* Prototypes. */
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static int sign_ext PARAMS((unsigned int, int));
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static void print_br_address PARAMS((disassemble_info *, bfd_vma, int));
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static void print_br_address PARAMS((disassemble_info *, bfd_vma, long));
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/* True if opcode is xor, xorh, and, andh, or, orh, andnot, andnoth. */
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@ -75,10 +75,10 @@ static void
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print_br_address (info, memaddr, val)
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disassemble_info *info;
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bfd_vma memaddr;
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int val;
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long val;
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{
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int adj = memaddr + 4 + (val << 2);
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long adj = (long)memaddr + 4 + (val << 2);
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(*info->fprintf_func) (info->stream, "0x%08x", adj);
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