2000-08-08  Jason Eckhardt  <jle@cygnus.com>

	* config/tc-i860.h: Rework completely for BFD_ASSEMBLER.
	(i860_fix_info): New enum.
	(MD_APPLY_FIX3): Define.
	(WORKING_DOT_WORD): Define.
	(TC_HANDLES_FX_DONE): Define.
	(DIFF_EXPR_OK): Define.
	(LISTING_HEADER): Define.
	(TARGET_FORMAT): Select target format based on endian flag.
	(TARGET_BYTES_BIG_ENDIAN): Default to little endian.
	(target_big_endian): Add external declaration.

	* config/tc-i860.c: All existing code reworked completely. Other
	new code shown below.
	(SYNTAX_SVR4): Define.
	(target_warn_expand): New variable.
	(md_shortopts): Declare and define (-Qy, -Qn, and -V options).
	(md_longopts): Declare and define with new options (-EL, -EB,
	and -mwarn-expand).
	(md_show_usage): New function.
	(md_operand): New function.
	(obtain_reloc_for_imm16): New function.
	(md_apply_fix3): New function.
	(tc_gen_reloc): New function.

include:
2000-08-08  Jason Eckhardt  <jle@cygnus.com>

	* opcode/i860.h: Small formatting adjustments.

opcode:
2000-08-08  Jason Eckhardt  <jle@cygnus.com>

	* i860-dis.c (print_br_address): Change third argument from int
	to long.

bfd:
2000-08-08  Jason Eckhardt  <jle@cygnus.com>
	* elf32-i860.c (elf32_i860_howto_table): Updated some fields.
This commit is contained in:
Jason Eckhardt 2000-08-09 03:33:42 +00:00
parent e374f1d977
commit 305d537e30
8 changed files with 913 additions and 697 deletions

View file

@ -1,3 +1,7 @@
2000-08-08 Jason Eckhardt <jle@cygnus.com>
* elf32-i860.c (elf32_i860_howto_table): Updated some fields.
2000-08-07 Kazu Hirata <kazu@hxi.com> 2000-08-07 Kazu Hirata <kazu@hxi.com>
* ieee.c (ieee_write_debug_part): Rewrite a comment. * ieee.c (ieee_write_debug_part): Rewrite a comment.

View file

@ -166,8 +166,8 @@ static reloc_howto_type elf32_i860_howto_table [] =
bfd_elf_generic_reloc, /* special_function */ bfd_elf_generic_reloc, /* special_function */
"R_860_PC16", /* name */ "R_860_PC16", /* name */
false, /* partial_inplace */ false, /* partial_inplace */
0xffff, /* src_mask */ 0x1f07ff, /* src_mask */
0xffff, /* dst_mask */ 0x1f07ff, /* dst_mask */
true), /* pcrel_offset */ true), /* pcrel_offset */
HOWTO (R_860_LOW0, /* type */ HOWTO (R_860_LOW0, /* type */
@ -222,8 +222,8 @@ static reloc_howto_type elf32_i860_howto_table [] =
bfd_elf_generic_reloc, /* special_function */ bfd_elf_generic_reloc, /* special_function */
"R_860_SPLIT1", /* name */ "R_860_SPLIT1", /* name */
false, /* partial_inplace */ false, /* partial_inplace */
0x1f07ff, /* src_mask */ 0x1f07fe, /* src_mask */
0x1f07ff, /* dst_mask */ 0x1f07fe, /* dst_mask */
false), /* pcrel_offset */ false), /* pcrel_offset */
HOWTO (R_860_LOW2, /* type */ HOWTO (R_860_LOW2, /* type */
@ -250,8 +250,8 @@ static reloc_howto_type elf32_i860_howto_table [] =
bfd_elf_generic_reloc, /* special_function */ bfd_elf_generic_reloc, /* special_function */
"R_860_SPLIT2", /* name */ "R_860_SPLIT2", /* name */
false, /* partial_inplace */ false, /* partial_inplace */
0x1f07ff, /* src_mask */ 0x1f07fc, /* src_mask */
0x1f07ff, /* dst_mask */ 0x1f07fc, /* dst_mask */
false), /* pcrel_offset */ false), /* pcrel_offset */
HOWTO (R_860_LOW3, /* type */ HOWTO (R_860_LOW3, /* type */

View file

@ -1,3 +1,29 @@
2000-08-08 Jason Eckhardt <jle@cygnus.com>
* config/tc-i860.h: Rework completely for BFD_ASSEMBLER.
(i860_fix_info): New enum.
(MD_APPLY_FIX3): Define.
(WORKING_DOT_WORD): Define.
(TC_HANDLES_FX_DONE): Define.
(DIFF_EXPR_OK): Define.
(LISTING_HEADER): Define.
(TARGET_FORMAT): Select target format based on endian flag.
(TARGET_BYTES_BIG_ENDIAN): Default to little endian.
(target_big_endian): Add external declaration.
* config/tc-i860.c: All existing code reworked completely. Other
new code shown below.
(SYNTAX_SVR4): Define.
(target_warn_expand): New variable.
(md_shortopts): Declare and define (-Qy, -Qn, and -V options).
(md_longopts): Declare and define with new options (-EL, -EB,
and -mwarn-expand).
(md_show_usage): New function.
(md_operand): New function.
(obtain_reloc_for_imm16): New function.
(md_apply_fix3): New function.
(tc_gen_reloc): New function.
2000-08-09 Kazu Hirata <kazu@hxi.com> 2000-08-09 Kazu Hirata <kazu@hxi.com>
* hash.c: Fix formatting. * hash.c: Fix formatting.

File diff suppressed because it is too large Load diff

View file

@ -1,5 +1,9 @@
/* tc-i860.h -- Header file for the I860 /* tc-i860.h -- Header file for the i860.
Copyright (C) 1991, 92, 95, 1998 Free Software Foundation, Inc. Copyright (C) 1991, 1992, 1995, 1998, 2000
Free Software Foundation, Inc.
Brought back from the dead and completely reworked
by Jason Eckhardt <jle@cygnus.com>.
This file is part of GAS, the GNU Assembler. This file is part of GAS, the GNU Assembler.
@ -17,23 +21,68 @@
with GAS; see the file COPYING. If not, write to the Free Software with GAS; see the file COPYING. If not, write to the Free Software
Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#ifndef TC_I860
#define TC_I860 1 #define TC_I860 1
#define TARGET_BYTES_BIG_ENDIAN 1
#ifndef BFD_ASSEMBLER
#error i860 support requires BFD_ASSEMBLER
#endif
enum i860_fix_info
{
OP_NONE = 0x00000,
OP_IMM_U5 = 0x00001,
OP_IMM_S16 = 0x00002,
OP_IMM_U16 = 0x00004,
OP_IMM_SPLIT16 = 0x00008,
OP_IMM_BR26 = 0x00010,
OP_IMM_BR16 = 0x00020,
OP_ENCODE1 = 0x00040,
OP_ENCODE2 = 0x00080,
OP_ENCODE3 = 0x00100,
OP_SEL_HA = 0x00200,
OP_SEL_H = 0x00400,
OP_SEL_L = 0x00800,
OP_SEL_GOT = 0x01000,
OP_SEL_GOTOFF = 0x02000,
OP_SEL_PLT = 0x04000,
OP_ALIGN2 = 0x08000,
OP_ALIGN4 = 0x10000,
OP_ALIGN8 = 0x20000,
OP_ALIGN16 = 0x40000
};
/* Set the endianness we are using. Default to little endian. */
#ifndef TARGET_BYTES_BIG_ENDIAN
#define TARGET_BYTES_BIG_ENDIAN 0
#endif
/* Whether or not the target is big endian. */
extern int target_big_endian;
/* BFD target architecture. */
#define TARGET_ARCH bfd_arch_i860
/* The target BFD format. */
#ifdef OBJ_ELF
#define TARGET_FORMAT (target_big_endian ? "elf32-i860" : "elf32-i860-little")
#else
#error i860 GAS currently supports only the ELF object format
#endif
#define WORKING_DOT_WORD #define WORKING_DOT_WORD
#define MD_APPLY_FIX3
#define TC_HANDLES_FX_DONE
#define DIFF_EXPR_OK
#define tc_headers_hook(a) {;} /* not used */ /* Permit temporary numeric labels. */
#define tc_crawl_symbol_chain(a) {;} /* not used */ #define LOCAL_LABELS_FB 1
#define tc_aout_pre_write_hook(x) {;} /* not used */ #define LISTING_HEADER "GAS for i860"
#define md_operand(x) #define md_convert_frag(b,s,f) as_fatal (_("i860_convert_frag\n"));
/* #endif /* TC_I860 */
* Local Variables:
* comment-column: 0
* fill-column: 131
* End:
*/
/* end of tc-i860.h */

View file

@ -1,3 +1,7 @@
2000-08-08 Jason Eckhardt <jle@cygnus.com>
* opcode/i860.h: Small formatting adjustments.
2000-07-29 Nick Clifton <nickc@cygnus.com> 2000-07-29 Nick Clifton <nickc@cygnus.com>
* os9k.h: Add copyright notice. * os9k.h: Add copyright notice.

View file

@ -15,32 +15,36 @@ GNU General Public License for more details.
You should have received a copy of the GNU General Public License You should have received a copy of the GNU General Public License
along with GAS or GDB; see the file COPYING. If not, write to along with GAS or GDB; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
#if !defined(__STDC__) && !defined(const)
#define const
#endif
/* /* Structure of an opcode table entry. */
* Structure of an opcode table entry.
*/
struct i860_opcode struct i860_opcode
{ {
/* The opcode name. */
const char *name; const char *name;
unsigned long match; /* Bits that must be set. */
unsigned long lose; /* Bits that must not be set. */ /* Bits that must be set. */
unsigned long match;
/* Bits that must not be set. */
unsigned long lose;
const char *args; const char *args;
/* Nonzero if this is a possible expand-instruction. */ /* Nonzero if this is a possible expand-instruction. */
char expand; char expand;
}; };
enum expand_type enum expand_type
{ {
E_MOV = 1, E_ADDR, E_U32, E_AND, E_S32, E_DELAY E_MOV = 1, E_ADDR, E_U32, E_AND, E_S32, E_DELAY
}; };
/*
All i860 opcodes are 32 bits, except for the pseudoinstructions /* All i860 opcodes are 32 bits, except for the pseudo-instructions
and the operations utilizing a 32-bit address expression, an and the operations utilizing a 32-bit address expression, an
unsigned 32-bit constant, or a signed 32-bit constant. unsigned 32-bit constant, or a signed 32-bit constant.
These opcodes are expanded into a two-instruction sequence for These opcodes are expanded into a two-instruction sequence for
@ -83,21 +87,18 @@ Kinds of operands:
U split 16 bit immediate, aligned 2^2. (st.l) U split 16 bit immediate, aligned 2^2. (st.l)
e src1 floating point register. e src1 floating point register.
f src2 floating point register. f src2 floating point register.
g dest floating point register. g dest floating point register. */
*/
/* The order of the opcodes in this table is significant: /* The order of the opcodes in this table is significant. The assembler
requires that all instances of the same mnemonic must be consecutive.
If they aren't, the assembler will not function properly.
* The assembler requires that all instances of the same mnemonic must be The order of opcodes does not affect the disassembler. */
consecutive. If they aren't, the assembler will bomb at runtime.
* The disassembler should not care about the order of the opcodes. */
static struct i860_opcode i860_opcodes[] = static struct i860_opcode i860_opcodes[] =
{ {
/* REG-Format Instructions. */
/* REG-Format Instructions */
{ "ld.c", 0x30000000, 0xcc000000, "c,d", 0 }, /* ld.c csrc2,idest */ { "ld.c", 0x30000000, 0xcc000000, "c,d", 0 }, /* ld.c csrc2,idest */
{ "ld.b", 0x00000000, 0xfc000000, "1(2),d", 0 }, /* ld.b isrc1(isrc2),idest */ { "ld.b", 0x00000000, 0xfc000000, "1(2),d", 0 }, /* ld.b isrc1(isrc2),idest */
{ "ld.b", 0x04000000, 0xf8000000, "I(2),d", E_ADDR }, /* ld.b #const(isrc2),idest */ { "ld.b", 0x04000000, 0xf8000000, "I(2),d", E_ADDR }, /* ld.b #const(isrc2),idest */
@ -212,7 +213,7 @@ static struct i860_opcode i860_opcodes[] =
{ "bnc", 0x78000000, 0x84000000, "l", 0 }, /* bnc lbroff */ { "bnc", 0x78000000, 0x84000000, "l", 0 }, /* bnc lbroff */
{ "bnc.t", 0x7c000000, 0x80000000, "l", E_DELAY }, /* bnc.t lbroff */ { "bnc.t", 0x7c000000, 0x80000000, "l", E_DELAY }, /* bnc.t lbroff */
/* Floating Point Escape Instruction Format - pfam.p fsrc1,fsrc2,fdest */ /* Floating Point Escape Instruction Format - pfam.p fsrc1,fsrc2,fdest. */
{ "r2p1.ss", 0x48000400, 0xb40001ff, "e,f,g", 0 }, { "r2p1.ss", 0x48000400, 0xb40001ff, "e,f,g", 0 },
{ "r2p1.sd", 0x48000480, 0xb400017f, "e,f,g", 0 }, { "r2p1.sd", 0x48000480, 0xb400017f, "e,f,g", 0 },
{ "r2p1.dd", 0x48000580, 0xb400007f, "e,f,g", 0 }, { "r2p1.dd", 0x48000580, 0xb400007f, "e,f,g", 0 },
@ -262,7 +263,7 @@ static struct i860_opcode i860_opcodes[] =
{ "m12tpa.sd", 0x4800048f, 0xb4000170, "e,f,g", 0 }, { "m12tpa.sd", 0x4800048f, 0xb4000170, "e,f,g", 0 },
{ "m12tpa.dd", 0x4800058f, 0xb4000070, "e,f,g", 0 }, { "m12tpa.dd", 0x4800058f, 0xb4000070, "e,f,g", 0 },
/* Floating Point Escape Instruction Format - pfsm.p fsrc1,fsrc2,fdest */ /* Floating Point Escape Instruction Format - pfsm.p fsrc1,fsrc2,fdest. */
{ "r2s1.ss", 0x48000410, 0xb40001ef, "e,f,g", 0 }, { "r2s1.ss", 0x48000410, 0xb40001ef, "e,f,g", 0 },
{ "r2s1.sd", 0x48000490, 0xb400016f, "e,f,g", 0 }, { "r2s1.sd", 0x48000490, 0xb400016f, "e,f,g", 0 },
{ "r2s1.dd", 0x48000590, 0xb400006f, "e,f,g", 0 }, { "r2s1.dd", 0x48000590, 0xb400006f, "e,f,g", 0 },
@ -312,7 +313,7 @@ static struct i860_opcode i860_opcodes[] =
{ "m12tsa.sd", 0x4800049f, 0xb4000160, "e,f,g", 0 }, { "m12tsa.sd", 0x4800049f, 0xb4000160, "e,f,g", 0 },
{ "m12tsa.dd", 0x4800059f, 0xb4000060, "e,f,g", 0 }, { "m12tsa.dd", 0x4800059f, 0xb4000060, "e,f,g", 0 },
/* Floating Point Escape Instruction Format - pfmam.p fsrc1,fsrc2,fdest */ /* Floating Point Escape Instruction Format - pfmam.p fsrc1,fsrc2,fdest. */
{ "mr2p1.ss", 0x48000000, 0xb40005ff, "e,f,g", 0 }, { "mr2p1.ss", 0x48000000, 0xb40005ff, "e,f,g", 0 },
{ "mr2p1.sd", 0x48000080, 0xb400057f, "e,f,g", 0 }, { "mr2p1.sd", 0x48000080, 0xb400057f, "e,f,g", 0 },
{ "mr2p1.dd", 0x48000180, 0xb400047f, "e,f,g", 0 }, { "mr2p1.dd", 0x48000180, 0xb400047f, "e,f,g", 0 },
@ -359,7 +360,7 @@ static struct i860_opcode i860_opcodes[] =
{ "mim1p2.sd", 0x4800008e, 0xb4000571, "e,f,g", 0 }, { "mim1p2.sd", 0x4800008e, 0xb4000571, "e,f,g", 0 },
{ "mim1p2.dd", 0x4800018e, 0xb4000471, "e,f,g", 0 }, { "mim1p2.dd", 0x4800018e, 0xb4000471, "e,f,g", 0 },
/* Floating Point Escape Instruction Format - pfmsm.p fsrc1,fsrc2,fdest */ /* Floating Point Escape Instruction Format - pfmsm.p fsrc1,fsrc2,fdest. */
{ "mr2s1.ss", 0x48000010, 0xb40005ef, "e,f,g", 0 }, { "mr2s1.ss", 0x48000010, 0xb40005ef, "e,f,g", 0 },
{ "mr2s1.sd", 0x48000090, 0xb400056f, "e,f,g", 0 }, { "mr2s1.sd", 0x48000090, 0xb400056f, "e,f,g", 0 },
{ "mr2s1.dd", 0x48000190, 0xb400046f, "e,f,g", 0 }, { "mr2s1.dd", 0x48000190, 0xb400046f, "e,f,g", 0 },
@ -406,7 +407,6 @@ static struct i860_opcode i860_opcodes[] =
{ "mim1s2.sd", 0x4800009e, 0xb4000561, "e,f,g", 0 }, { "mim1s2.sd", 0x4800009e, 0xb4000561, "e,f,g", 0 },
{ "mim1s2.dd", 0x4800019e, 0xb4000461, "e,f,g", 0 }, { "mim1s2.dd", 0x4800019e, 0xb4000461, "e,f,g", 0 },
{ "fmul.ss", 0x48000020, 0xb40005df, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */ { "fmul.ss", 0x48000020, 0xb40005df, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */
{ "fmul.sd", 0x480000a0, 0xb400055f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */ { "fmul.sd", 0x480000a0, 0xb400055f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */
{ "fmul.dd", 0x480001a0, 0xb400045f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */ { "fmul.dd", 0x480001a0, 0xb400045f, "e,f,g", 0 }, /* fmul.p fsrc1,fsrc2,fdest */
@ -447,10 +447,10 @@ static struct i860_opcode i860_opcodes[] =
{ "pfamov.ds", 0x48000533, 0xb40000cc, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ { "pfamov.ds", 0x48000533, 0xb40000cc, "e,g", 0 }, /* pfamov.p fsrc1,fdest */
{ "pfamov.sd", 0x480004b3, 0xb400014c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ { "pfamov.sd", 0x480004b3, 0xb400014c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */
{ "pfamov.dd", 0x480005b3, 0xb400004c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */ { "pfamov.dd", 0x480005b3, 0xb400004c, "e,g", 0 }, /* pfamov.p fsrc1,fdest */
/* pfgt has R bit cleared; pfle has R bit set */ /* Opcode pfgt has R bit cleared; pfle has R bit set. */
{ "pfgt.ss", 0x48000434, 0xb40001cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */ { "pfgt.ss", 0x48000434, 0xb40001cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */
{ "pfgt.dd", 0x48000534, 0xb40000cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */ { "pfgt.dd", 0x48000534, 0xb40000cb, "e,f,g", 0 }, /* pfgt.p fsrc1,fsrc2,fdest */
/* pfgt has R bit cleared; pfle has R bit set */ /* Opcode pfgt has R bit cleared; pfle has R bit set. */
{ "pfle.ss", 0x480004b4, 0xb400014b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */ { "pfle.ss", 0x480004b4, 0xb400014b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */
{ "pfle.dd", 0x480005b4, 0xb400004b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */ { "pfle.dd", 0x480005b4, 0xb400004b, "e,f,g", 0 }, /* pfle.p fsrc1,fsrc2,fdest */
{ "pfeq.ss", 0x48000435, 0xb40001ca, "e,f,g", 0 }, /* pfeq.p fsrc1,fsrc2,fdest */ { "pfeq.ss", 0x48000435, 0xb40001ca, "e,f,g", 0 }, /* pfeq.p fsrc1,fsrc2,fdest */
@ -481,7 +481,7 @@ static struct i860_opcode i860_opcodes[] =
{ "form", 0x480001da, 0xb4000425, "e,g", 0 }, /* form fsrc1,fdest */ { "form", 0x480001da, 0xb4000425, "e,g", 0 }, /* form fsrc1,fdest */
{ "pform", 0x480005da, 0xb4000025, "e,g", 0 }, /* pform fsrc1,fdest */ { "pform", 0x480005da, 0xb4000025, "e,g", 0 }, /* pform fsrc1,fdest */
/* Floating point pseudo-instructions */ /* Floating point pseudo-instructions. */
{ "fmov.ss", 0x48000049, 0xb7e005b6, "e,g", 0 }, /* fiadd.ss fsrc1,f0,fdest */ { "fmov.ss", 0x48000049, 0xb7e005b6, "e,g", 0 }, /* fiadd.ss fsrc1,f0,fdest */
{ "fmov.dd", 0x480001c9, 0xb7e00436, "e,g", 0 }, /* fiadd.dd fsrc1,f0,fdest */ { "fmov.dd", 0x480001c9, 0xb7e00436, "e,g", 0 }, /* fiadd.dd fsrc1,f0,fdest */
{ "fmov.sd", 0x480000b0, 0xb7e0054f, "e,g", 0 }, /* fadd.sd fsrc1,f0,fdest */ { "fmov.sd", 0x480000b0, 0xb7e0054f, "e,g", 0 }, /* fadd.sd fsrc1,f0,fdest */

View file

@ -44,7 +44,7 @@ static const char *const crnames[] =
/* Prototypes. */ /* Prototypes. */
static int sign_ext PARAMS((unsigned int, int)); static int sign_ext PARAMS((unsigned int, int));
static void print_br_address PARAMS((disassemble_info *, bfd_vma, int)); static void print_br_address PARAMS((disassemble_info *, bfd_vma, long));
/* True if opcode is xor, xorh, and, andh, or, orh, andnot, andnoth. */ /* True if opcode is xor, xorh, and, andh, or, orh, andnot, andnoth. */
@ -75,10 +75,10 @@ static void
print_br_address (info, memaddr, val) print_br_address (info, memaddr, val)
disassemble_info *info; disassemble_info *info;
bfd_vma memaddr; bfd_vma memaddr;
int val; long val;
{ {
int adj = memaddr + 4 + (val << 2); long adj = (long)memaddr + 4 + (val << 2);
(*info->fprintf_func) (info->stream, "0x%08x", adj); (*info->fprintf_func) (info->stream, "0x%08x", adj);