Add support for TBM instructions.
gas/ 2011-01-17 Quentin Neill <quentin.neill@amd.com> * config/tc-i386.c (cpu_arch): Add CPU_TBM_FLAGS. * doc/c-i386.texi (i386-TBM): New section. opcodes/ 2011-01-17 Quentin Neill <quentin.neill@amd.com> * i386-dis.c (REG_XOP_TBM_01): New. (REG_XOP_TBM_02): New. (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables. (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02 entries, and add bextr instruction. * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM. (cpu_flags): Add CpuTBM. * i386-opc.h (CpuTBM) New. (i386_cpu_flags): Add bit cputbm. * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk, blcs, blsfill, blsic, t1mskc, and tzmsk. * i386-init.h: Regenerated. * i386-tbl.h: Regenerated gas/testsuite 2011-01-17 Quentin Neill <quentin.neill@amd.com> * gas/i386/tbm.s: New. * gas/i386/tbm.d: New. * gas/i386/tbm-intel.d: New. * gas/i386/x86-64-tbm.s: New. * gas/i386/x86-64-tbm.d: New. * gas/i386/x86-64-tbm-intel.d: New. * gas/i386/arch-10.d: Add tbm flag and TBM instruction pattern. * gas/i386/arch-10.s: Add a TBM instruction. * gas/i386/arch-10-1.l: Add TBM instruction pattern. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/x86-64-arch-2.d: Likewise.
This commit is contained in:
Quentin Neill
parent
dc92e16124
commit
2a2a0f38e7
18 changed files with 131 additions and 7 deletions
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@ -1,3 +1,9 @@
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2011-01-17 Quentin Neill <quentin.neill@amd.com>
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* config/tc-i386.c (cpu_arch): Add CPU_TBM_FLAGS.
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* doc/c-i386.texi (i386-TBM): New section.
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2011-01-16 H.J. Lu <hongjiu.lu@intel.com>
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2011-01-16 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (disallow_64bit_disp): Renamed to ...
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* config/tc-i386.c (disallow_64bit_disp): Renamed to ...
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@ -733,6 +733,8 @@ static const arch_entry cpu_arch[] =
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CPU_ABM_FLAGS, 0, 0 },
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CPU_ABM_FLAGS, 0, 0 },
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{ STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
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{ STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
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CPU_BMI_FLAGS, 0, 0 },
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CPU_BMI_FLAGS, 0, 0 },
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{ STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
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CPU_TBM_FLAGS, 0, 0 },
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};
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};
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#ifdef I386COFF
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#ifdef I386COFF
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@ -36,6 +36,7 @@ extending the Intel architecture to 64-bits.
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* i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
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* i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
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* i386-LWP:: AMD's Lightweight Profiling Instructions
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* i386-LWP:: AMD's Lightweight Profiling Instructions
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* i386-BMI:: Bit Manipulation Instruction
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* i386-BMI:: Bit Manipulation Instruction
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* i386-TBM:: AMD's Trailing Bit Manipulation Instructions
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* i386-16bit:: Writing 16-bit Code
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* i386-16bit:: Writing 16-bit Code
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* i386-Arch:: Specifying an x86 CPU architecture
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* i386-Arch:: Specifying an x86 CPU architecture
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* i386-Bugs:: AT&T Syntax bugs
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* i386-Bugs:: AT&T Syntax bugs
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@ -860,6 +861,21 @@ resetting.
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@c Need to add a specification citation here when available.
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@c Need to add a specification citation here when available.
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@node i386-TBM
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@section AMD's Trailing Bit Manipulation Instructions
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@cindex TBM, i386
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@cindex TBM, x86-64
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@code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
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instruction set, available on AMD's BDVER2 processors (Trinity and
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Viperfish).
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TBM instructions provide instructions implementing individual bit
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manipulation operations such as isolating, masking, setting, resetting,
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complementing, and operations on trailing zeros and ones.
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@c Need to add a specification citation here when available.
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@node i386-16bit
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@node i386-16bit
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@section Writing 16-bit Code
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@section Writing 16-bit Code
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@ -1,3 +1,20 @@
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2011-01-17 Quentin Neill <quentin.neill@amd.com>
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* gas/i386/tbm.s: New.
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* gas/i386/tbm.d: New.
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* gas/i386/tbm-intel.d: New.
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* gas/i386/x86-64-tbm.s: New.
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* gas/i386/x86-64-tbm.d: New.
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* gas/i386/x86-64-tbm-intel.d: New.
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* gas/i386/arch-10.d: Add tbm flag and TBM instruction pattern.
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* gas/i386/arch-10.s: Add a TBM instruction.
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* gas/i386/arch-10-1.l: Add TBM instruction pattern.
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* gas/i386/arch-10-2.l: Likewise.
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* gas/i386/arch-10-3.l: Likewise.
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* gas/i386/arch-10-4.l: Likewise.
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* gas/i386/x86-64-arch-2.s: Likewise.
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* gas/i386/x86-64-arch-2.d: Likewise.
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2011-01-16 H.J. Lu <hongjiu.lu@intel.com>
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2011-01-16 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/ilp32/immed64.s: New.
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* gas/i386/ilp32/immed64.s: New.
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@ -30,6 +30,7 @@
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.*:60: Error: .*
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.*:60: Error: .*
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.*:62: Error: .*
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.*:62: Error: .*
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.*:64: Error: .*
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.*:64: Error: .*
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.*:66: Error: .*
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GAS LISTING .*
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GAS LISTING .*
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@ -101,3 +102,5 @@ GAS LISTING .*
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[ ]*62[ ]+nopl \(%eax\)
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[ ]*62[ ]+nopl \(%eax\)
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[ ]*63[ ]+\# BMI
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[ ]*63[ ]+\# BMI
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[ ]*64[ ]+blsr %ecx,%ebx
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[ ]*64[ ]+blsr %ecx,%ebx
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[ ]*65[ ]+\# TBM
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[ ]*66[ ]+blcfill %ecx,%ebx
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@ -29,6 +29,7 @@
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.*:60: Error: .*
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.*:60: Error: .*
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.*:62: Error: .*
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.*:62: Error: .*
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.*:64: Error: .*
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.*:64: Error: .*
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.*:66: Error: .*
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GAS LISTING .*
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GAS LISTING .*
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@ -100,3 +101,5 @@ GAS LISTING .*
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[ ]*62[ ]+nopl \(%eax\)
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[ ]*62[ ]+nopl \(%eax\)
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[ ]*63[ ]+\# BMI
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[ ]*63[ ]+\# BMI
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[ ]*64[ ]+blsr %ecx,%ebx
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[ ]*64[ ]+blsr %ecx,%ebx
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[ ]*65[ ]+\# TBM
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[ ]*66[ ]+blcfill %ecx,%ebx
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@ -22,6 +22,7 @@
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.*:60: Error: .*
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.*:60: Error: .*
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.*:62: Error: .*
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.*:62: Error: .*
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.*:64: Error: .*
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.*:64: Error: .*
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.*:66: Error: .*
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GAS LISTING .*
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GAS LISTING .*
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@ -96,3 +97,5 @@ GAS LISTING .*
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[ ]*62[ ]+nopl \(%eax\)
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[ ]*62[ ]+nopl \(%eax\)
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[ ]*63[ ]+\# BMI
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[ ]*63[ ]+\# BMI
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[ ]*64[ ]+blsr %ecx,%ebx
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[ ]*64[ ]+blsr %ecx,%ebx
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[ ]*65[ ]+\# TBM
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[ ]*66[ ]+blcfill %ecx,%ebx
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@ -20,6 +20,7 @@
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.*:60: Error: .*
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.*:60: Error: .*
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.*:62: Error: .*
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.*:62: Error: .*
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.*:64: Error: .*
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.*:64: Error: .*
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.*:66: Error: .*
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GAS LISTING .*
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GAS LISTING .*
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@ -94,3 +95,5 @@ GAS LISTING .*
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[ ]*62[ ]+nopl \(%eax\)
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[ ]*62[ ]+nopl \(%eax\)
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[ ]*63[ ]+\# BMI
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[ ]*63[ ]+\# BMI
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[ ]*64[ ]+blsr %ecx,%ebx
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[ ]*64[ ]+blsr %ecx,%ebx
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[ ]*65[ ]+\# TBM
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[ ]*66[ ]+blcfill %ecx,%ebx
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@ -1,4 +1,4 @@
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#as: -march=i686+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+nop+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi
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#as: -march=i686+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+nop+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi+tbm
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#objdump: -dw
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#objdump: -dw
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#name: i386 arch 10
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#name: i386 arch 10
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@ -38,4 +38,5 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 0f a7 c0 xstore-rng
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[ ]*[a-f0-9]+: 0f a7 c0 xstore-rng
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[ ]*[a-f0-9]+: 0f 1f 00 nopl \(%eax\)
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[ ]*[a-f0-9]+: 0f 1f 00 nopl \(%eax\)
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[ ]*[a-f0-9]+: c4 e2 60 f3 c9 blsr %ecx,%ebx
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[ ]*[a-f0-9]+: c4 e2 60 f3 c9 blsr %ecx,%ebx
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[ ]*[a-f0-9]+: 8f e9 60 01 c9 blcfill %ecx,%ebx
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#pass
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#pass
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@ -62,3 +62,5 @@ xstorerng
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nopl (%eax)
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nopl (%eax)
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# BMI
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# BMI
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blsr %ecx,%ebx
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blsr %ecx,%ebx
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# TBM
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blcfill %ecx,%ebx
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@ -175,6 +175,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "xop"
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run_dump_test "xop"
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run_dump_test "bmi"
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run_dump_test "bmi"
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run_dump_test "bmi-intel"
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run_dump_test "bmi-intel"
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run_dump_test "tbm"
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run_dump_test "tbm-intel"
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run_dump_test "f16c"
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run_dump_test "f16c"
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run_dump_test "f16c-intel"
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run_dump_test "f16c-intel"
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run_dump_test "fsgs"
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run_dump_test "fsgs"
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@ -376,6 +378,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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run_dump_test "x86-64-xop"
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run_dump_test "x86-64-xop"
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run_dump_test "x86-64-bmi"
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run_dump_test "x86-64-bmi"
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run_dump_test "x86-64-bmi-intel"
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run_dump_test "x86-64-bmi-intel"
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run_dump_test "x86-64-tbm"
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run_dump_test "x86-64-tbm-intel"
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run_dump_test "x86-64-f16c"
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run_dump_test "x86-64-f16c"
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run_dump_test "x86-64-f16c-intel"
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run_dump_test "x86-64-f16c-intel"
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run_dump_test "x86-64-fsgs"
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run_dump_test "x86-64-fsgs"
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@ -1,4 +1,4 @@
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#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi
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#as: -march=generic64+avx+vmx+smx+xsave+xsaveopt+aes+pclmul+fma+movbe+ept+clflush+syscall+rdtscp+3dnowa+sse4a+svme+abm+padlock+bmi+tbm
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#objdump: -dw
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#objdump: -dw
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#name: x86-64 arch 2
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#name: x86-64 arch 2
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@ -37,4 +37,5 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: f3 0f bd d9 lzcnt %ecx,%ebx
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[ ]*[a-f0-9]+: f3 0f bd d9 lzcnt %ecx,%ebx
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[ ]*[a-f0-9]+: 0f a7 c0 xstore-rng
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[ ]*[a-f0-9]+: 0f a7 c0 xstore-rng
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[ ]*[a-f0-9]+: c4 e2 60 f3 c9 blsr %ecx,%ebx
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[ ]*[a-f0-9]+: c4 e2 60 f3 c9 blsr %ecx,%ebx
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[ ]*[a-f0-9]+: 8f e9 60 01 c9 blcfill %ecx,%ebx
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#pass
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#pass
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@ -60,3 +60,5 @@ lzcnt %ecx,%ebx
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xstorerng
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xstorerng
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# BMI
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# BMI
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blsr %ecx,%ebx
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blsr %ecx,%ebx
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# TBM
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blcfill %ecx,%ebx
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@ -1,3 +1,23 @@
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2011-01-17 Quentin Neill <quentin.neill@amd.com>
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* i386-dis.c (REG_XOP_TBM_01): New.
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(REG_XOP_TBM_02): New.
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(reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
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(xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
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entries, and add bextr instruction.
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* i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
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(cpu_flags): Add CpuTBM.
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* i386-opc.h (CpuTBM) New.
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(i386_cpu_flags): Add bit cputbm.
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* i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
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blcs, blsfill, blsic, t1mskc, and tzmsk.
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* i386-init.h: Regenerated.
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* i386-tbl.h: Regenerated
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2011-01-12 DJ Delorie <dj@redhat.com>
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2011-01-12 DJ Delorie <dj@redhat.com>
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* rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
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* rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
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@ -601,7 +601,9 @@ enum
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REG_VEX_0FAE,
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REG_VEX_0FAE,
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REG_VEX_0F38F3,
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REG_VEX_0F38F3,
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REG_XOP_LWPCB,
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REG_XOP_LWPCB,
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REG_XOP_LWP
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REG_XOP_LWP,
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REG_XOP_TBM_01,
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REG_XOP_TBM_02
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};
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};
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enum
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enum
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@ -2779,6 +2781,27 @@ static const struct dis386 reg_table[][8] = {
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{ "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
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{ "lwpins", { { OP_LWP_E, 0 }, Ed, Iq } },
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{ "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
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{ "lwpval", { { OP_LWP_E, 0 }, Ed, Iq } },
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},
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},
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/* REG_XOP_TBM_01 */
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{
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{ Bad_Opcode },
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{ "blcfill", { { OP_LWP_E, 0 }, Ev } },
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{ "blsfill", { { OP_LWP_E, 0 }, Ev } },
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{ "blcs", { { OP_LWP_E, 0 }, Ev } },
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{ "tzmsk", { { OP_LWP_E, 0 }, Ev } },
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{ "blcic", { { OP_LWP_E, 0 }, Ev } },
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{ "blsic", { { OP_LWP_E, 0 }, Ev } },
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{ "t1mskc", { { OP_LWP_E, 0 }, Ev } },
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},
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/* REG_XOP_TBM_02 */
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{
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{ Bad_Opcode },
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{ "blcmsk", { { OP_LWP_E, 0 }, Ev } },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ "blci", { { OP_LWP_E, 0 }, Ev } },
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},
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};
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};
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static const struct dis386 prefix_table[][4] = {
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static const struct dis386 prefix_table[][4] = {
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@ -6459,7 +6482,7 @@ static const struct dis386 xop_table[][256] = {
|
||||||
{ Bad_Opcode },
|
{ Bad_Opcode },
|
||||||
{ Bad_Opcode },
|
{ Bad_Opcode },
|
||||||
/* 10 */
|
/* 10 */
|
||||||
{ Bad_Opcode },
|
{ "bextr", { Gv, Ev, Iq } },
|
||||||
{ Bad_Opcode },
|
{ Bad_Opcode },
|
||||||
{ Bad_Opcode },
|
{ Bad_Opcode },
|
||||||
{ Bad_Opcode },
|
{ Bad_Opcode },
|
||||||
|
|
@ -6733,8 +6756,8 @@ static const struct dis386 xop_table[][256] = {
|
||||||
{
|
{
|
||||||
/* 00 */
|
/* 00 */
|
||||||
{ Bad_Opcode },
|
{ Bad_Opcode },
|
||||||
{ Bad_Opcode },
|
{ REG_TABLE (REG_XOP_TBM_01) },
|
||||||
{ Bad_Opcode },
|
{ REG_TABLE (REG_XOP_TBM_02) },
|
||||||
{ Bad_Opcode },
|
{ Bad_Opcode },
|
||||||
{ Bad_Opcode },
|
{ Bad_Opcode },
|
||||||
{ Bad_Opcode },
|
{ Bad_Opcode },
|
||||||
|
|
@ -7041,7 +7064,7 @@ static const struct dis386 xop_table[][256] = {
|
||||||
{ Bad_Opcode },
|
{ Bad_Opcode },
|
||||||
{ Bad_Opcode },
|
{ Bad_Opcode },
|
||||||
/* 10 */
|
/* 10 */
|
||||||
{ Bad_Opcode },
|
{ "bextr", { Gv, Ev, Iq } },
|
||||||
{ Bad_Opcode },
|
{ Bad_Opcode },
|
||||||
{ REG_TABLE (REG_XOP_LWP) },
|
{ REG_TABLE (REG_XOP_LWP) },
|
||||||
{ Bad_Opcode },
|
{ Bad_Opcode },
|
||||||
|
|
|
||||||
|
|
@ -142,6 +142,8 @@ static initializer cpu_flag_init[] =
|
||||||
"CpuLWP" },
|
"CpuLWP" },
|
||||||
{ "CPU_BMI_FLAGS",
|
{ "CPU_BMI_FLAGS",
|
||||||
"CpuBMI" },
|
"CpuBMI" },
|
||||||
|
{ "CPU_TBM_FLAGS",
|
||||||
|
"CpuTBM" },
|
||||||
{ "CPU_MOVBE_FLAGS",
|
{ "CPU_MOVBE_FLAGS",
|
||||||
"CpuMovbe" },
|
"CpuMovbe" },
|
||||||
{ "CPU_RDTSCP_FLAGS",
|
{ "CPU_RDTSCP_FLAGS",
|
||||||
|
|
@ -323,6 +325,7 @@ static bitfield cpu_flags[] =
|
||||||
BITFIELD (CpuXOP),
|
BITFIELD (CpuXOP),
|
||||||
BITFIELD (CpuLWP),
|
BITFIELD (CpuLWP),
|
||||||
BITFIELD (CpuBMI),
|
BITFIELD (CpuBMI),
|
||||||
|
BITFIELD (CpuTBM),
|
||||||
BITFIELD (CpuLM),
|
BITFIELD (CpuLM),
|
||||||
BITFIELD (CpuMovbe),
|
BITFIELD (CpuMovbe),
|
||||||
BITFIELD (CpuEPT),
|
BITFIELD (CpuEPT),
|
||||||
|
|
|
||||||
|
|
@ -112,6 +112,8 @@ enum
|
||||||
CpuLWP,
|
CpuLWP,
|
||||||
/* BMI support required */
|
/* BMI support required */
|
||||||
CpuBMI,
|
CpuBMI,
|
||||||
|
/* TBM support required */
|
||||||
|
CpuTBM,
|
||||||
/* MOVBE Instruction support required */
|
/* MOVBE Instruction support required */
|
||||||
CpuMovbe,
|
CpuMovbe,
|
||||||
/* EPT Instructions required */
|
/* EPT Instructions required */
|
||||||
|
|
@ -189,6 +191,7 @@ typedef union i386_cpu_flags
|
||||||
unsigned int cpuxop:1;
|
unsigned int cpuxop:1;
|
||||||
unsigned int cpulwp:1;
|
unsigned int cpulwp:1;
|
||||||
unsigned int cpubmi:1;
|
unsigned int cpubmi:1;
|
||||||
|
unsigned int cputbm:1;
|
||||||
unsigned int cpumovbe:1;
|
unsigned int cpumovbe:1;
|
||||||
unsigned int cpuept:1;
|
unsigned int cpuept:1;
|
||||||
unsigned int cpurdtscp:1;
|
unsigned int cpurdtscp:1;
|
||||||
|
|
|
||||||
|
|
@ -2742,6 +2742,18 @@ blsmsk, 2, 0xf3, 0x2, 1, CpuBMI, Modrm|CheckRegSize|Vex=3|VexOpcode=1|VexVVVV=2|
|
||||||
blsr, 2, 0xf3, 0x1, 1, CpuBMI, Modrm|CheckRegSize|Vex=3|VexOpcode=1|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 }
|
blsr, 2, 0xf3, 0x1, 1, CpuBMI, Modrm|CheckRegSize|Vex=3|VexOpcode=1|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg32|Reg64 }
|
||||||
tzcnt, 2, 0xf30fbc, None, 2, CpuBMI, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
|
tzcnt, 2, 0xf30fbc, None, 2, CpuBMI, Modrm|CheckRegSize|No_bSuf|No_sSuf|No_ldSuf, { Reg16|Reg32|Reg64|Word|Dword|Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, Reg16|Reg32|Reg64 }
|
||||||
|
|
||||||
|
// TBM instructions
|
||||||
|
bextr, 3, 0x10, None, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=5|VexVVVV=0|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Imm32|Imm32S, Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||||
|
blcfill, 2, 0x01, 0x1, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||||
|
blci, 2, 0x02, 0x6, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||||
|
blcic, 2, 0x01, 0x5, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||||
|
blcmsk, 2, 0x02, 0x1, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||||
|
blcs, 2, 0x01, 0x3, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||||
|
blsfill, 2, 0x01, 0x2, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||||
|
blsic, 2, 0x01, 0x6, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||||
|
t1mskc, 2, 0x01, 0x7, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||||
|
tzmsk, 2, 0x01, 0x4, 1, CpuTBM, Modrm|CheckRegSize|Vex=3|VexOpcode=4|VexVVVV=2|No_bSuf|No_wSuf|No_sSuf|No_ldSuf, { Reg32|Reg64|Dword|Qword|Disp8|Disp16|Disp32|Disp32S|Unspecified|BaseIndex, Reg32|Reg64 }
|
||||||
|
|
||||||
// AMD 3DNow! instructions.
|
// AMD 3DNow! instructions.
|
||||||
|
|
||||||
prefetch, 1, 0xf0d, 0x0, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
prefetch, 1, 0xf0d, 0x0, 2, Cpu3dnow, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Byte|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue