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2012-10-31 David Holsgrove <david.holsgrove@xilinx.com>

Browse source 
* config/tc-microblaze.c: Check for weak symbols before
	emitting relocation.

2012-10-31  David Holsgrove  <david.holsgrove@xilinx.com>

	* gas/microblaze: New.
	* gas/microblaze/reloc_sym.exp: Add test case.
	* gas/microblaze/reloc_strongsym.s: Likewise.
	* gas/microblaze/reloc_weaksym.s: Likewise.
	* gas/microblaze/reloc_sym.d: Likewise.
This commit is contained in:
Michael Eager 2012-10-31 15:27:37 +00:00
parent c66fb220b1
commit 28ad2e2dc9
10 changed files with 181 additions and 1 deletions
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5
gas/ChangeLog
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@ -1,3 +1,8 @@
2012-10-31 David Holsgrove <david.holsgrove@xilinx.com>
* config/tc-microblaze.c: Check for weak symbols before
emitting relocation.
2012-10-29 Alan Modra <amodra@gmail.com>
* sb.c (sb_check): Use __builtin_clzll when size_t is not the

3
gas/config/tc-microblaze.c
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@ -2065,7 +2065,8 @@ md_estimate_size_before_relax (fragS * fragP,
as_bad (_("Absolute PC-relative value in relaxation code. Assembler error....."));
abort ();
}
else if ((S_GET_SEGMENT (fragP->fr_symbol) == segment_type))
else if (S_GET_SEGMENT (fragP->fr_symbol) == segment_type &&
!S_IS_WEAK (fragP->fr_symbol))
{
fragP->fr_subtype = DEFINED_PC_OFFSET;
/* Don't know now whether we need an imm instruction. */

8
gas/testsuite/ChangeLog
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@ -1,3 +1,11 @@
2012-10-31 David Holsgrove <david.holsgrove@xilinx.com>
* gas/microblaze: New.
* gas/microblaze/reloc_sym.exp: Add test case.
* gas/microblaze/reloc_strongsym.s: Likewise.
* gas/microblaze/reloc_weaksym.s: Likewise.
* gas/microblaze/reloc_sym.d: Likewise.
2012-10-29 Alan Modra <amodra@gmail.com>
* gas/cfi/cfi.exp: Remove redundant ppc test. Exclude

20
gas/testsuite/gas/microblaze/reloc_strongsym.s Normal file
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@ -0,0 +1,20 @@
.section ".testsection"
.align 2
.globl test_start
.ent test_start
.type test_start, @function
test_start:
.frame r19,8,r15 # vars= 0, regs= 1, args= 0
.mask 0x00080000
addik r1,r1,-8
swi r19,r1,4
addk r19,r1,r0
addk r1,r19,r0
lwi r19,r1,4
addik r1,r1,8
rtsd r15,8
nop # Unfilled delay slot
.end test_start
$Lfe1:
.size test_start,$Lfe1-test_start

45
gas/testsuite/gas/microblaze/reloc_sym.d Normal file
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@ -0,0 +1,45 @@
reloc_sym.x: file format elf32-microblaze
Disassembly of section .text:
10000054 <__def_start>:
10000054: 3021fff8 addik r1, r1, -8
10000058: fa610004 swi r19, r1, 4
1000005c: 12610000 addk r19, r1, r0
10000060: 10330000 addk r1, r19, r0
10000064: ea610004 lwi r19, r1, 4
10000068: 30210008 addik r1, r1, 8
1000006c: b60f0008 rtsd r15, 8
10000070: 80000000 or r0, r0, r0
10000074 <main>:
10000074: 3021ffe0 addik r1, r1, -32
10000078: f9e10000 swi r15, r1, 0
1000007c: fa61001c swi r19, r1, 28
10000080: 12610000 addk r19, r1, r0
10000084: b000efff imm -4097
10000088: b9f4ff7c brlid r15, -132 // 4 <test_start>
1000008c: 80000000 or r0, r0, r0
10000090: b9f4ffc4 brlid r15, -60 // 10000054 <__def_start>
10000094: 80000000 or r0, r0, r0
10000098: 10600000 addk r3, r0, r0
1000009c: e9e10000 lwi r15, r1, 0
100000a0: 10330000 addk r1, r19, r0
100000a4: ea61001c lwi r19, r1, 28
100000a8: 30210020 addik r1, r1, 32
100000ac: b60f0008 rtsd r15, 8
100000b0: 80000000 or r0, r0, r0
Disassembly of section .testsection:
00000004 <test_start>:
4: 3021fff8 addik r1, r1, -8
8: fa610004 swi r19, r1, 4
c: 12610000 addk r19, r1, r0
10: 10330000 addk r1, r19, r0
14: ea610004 lwi r19, r1, 4
18: 30210008 addik r1, r1, 8
1c: b60f0008 rtsd r15, 8
20: 80000000 or r0, r0, r0

27
gas/testsuite/gas/microblaze/reloc_sym.exp Normal file
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# Relocation test.
proc ld_test { objects ldflags dest test } {
set ld_output [target_link $objects $dest $ldflags]
if [string match "" $ld_output] then { pass $test } else { fail $test }
}
proc objdump_test { exec flags dest test } {
set objcopy [find_binutils_prog objdump]
verbose -log "$objcopy $flags $exec > $dest"
catch "exec $objcopy $flags $exec > $dest" objdump_output
if [string match "" $objdump_output] then { pass $test } else { fail $test }
}
proc regexp_test { file1 file2 test } {
if [regexp_diff $file1 $file2] then { fail $test } else { pass $test }
}
global srcdir subdir
if [istarget microblaze*-*-*] {
gas_test "reloc_strongsym.s" {-o reloc_strongsym.o} {} {assembling reloc_strongsym}
gas_test "reloc_weaksym.s" {-o reloc_weaksym.o} {} {assembling reloc_weaksym}
ld_test {reloc_strongsym.o reloc_weaksym.o} {-e 0 -section-start .text=0x10000054 -section-start .testsection=0x4} {reloc_sym.x} {linking reloc_sym.x}
objdump_test {reloc_sym.x} {-d --section=.text --section=.testsection} {reloc_sym.dump} {disassembling reloc_sym.x}
regexp_test {reloc_sym.dump} "$srcdir/$subdir/reloc_sym.d" {matching disassembly}
}

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gas/testsuite/gas/microblaze/reloc_weaksym.s Normal file
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@ -0,0 +1,52 @@
.text
.align 2
.globl __def_start
.ent __def_start
.type __def_start, @function
__def_start:
.frame r19,8,r15 # vars= 0, regs= 1, args= 0
.mask 0x00080000
addik r1,r1,-8
swi r19,r1,4
addk r19,r1,r0
addk r1,r19,r0
lwi r19,r1,4
addik r1,r1,8
rtsd r15,8
nop # Unfilled delay slot
.end __def_start
$Lfe1:
.size __def_start,$Lfe1-__def_start
.align 2
.globl main
.ent main
.type main, @function
main:
.frame r19,32,r15 # vars= 0, regs= 1, args= 24
.mask 0x00088000
addik r1,r1,-32
swi r15,r1,0
swi r19,r1,28
addk r19,r1,r0
brlid r15,test_start
nop # Unfilled delay slot
brlid r15,test_start_strong
nop # Unfilled delay slot
addk r3,r0,r0
lwi r15,r1,0
addk r1,r19,r0
lwi r19,r1,28
addik r1,r1,32
rtsd r15,8
nop # Unfilled delay slot
.end main
$Lfe2:
.size main,$Lfe2-main
.weakext test_start
test_start = __def_start
.globl test_start_strong
test_start_strong = __def_start

14
gas/testsuite/gas/microblaze/special_reg.d Normal file
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#as:
#objdump: -ds
.*: file format .*
Contents of section .text:
0000 9409d000 6c00d000 001ff800 ....l.......
Disassembly of section .text:
00000000 <.text>:
0: 9409d000 mts rpid, r9
4: 6c00d000 tnput rfsl0
8: 001ff800 add r0, r31, r31

5
gas/testsuite/gas/microblaze/special_reg.exp Normal file
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@ -0,0 +1,5 @@
# MicroBlaze test for special register.
if [istarget microblaze*-*-*] {
run_dump_test "special_reg"
}

3
gas/testsuite/gas/microblaze/special_reg.s Normal file
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@ -0,0 +1,3 @@
mts rpid, r9
tnput rfsl0
add r0, r31, r31