* mips-dis.c: Add missing prototypes.
* a29k-dis.c: Likewise. * arc-dis.c: Likewise. * ia64-opc.c: Likewise.
This commit is contained in:
Andreas Jaeger
parent
7fa108a4d5
commit
279a96ca39
2 changed files with 192 additions and 163 deletions
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@ -35,16 +35,16 @@
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#define dbg (0)
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#endif
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#define BIT(word,n) ((word) & (1 << n))
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#define BITS(word,s,e) (((word) << (31 - e)) >> (s + (31 - e)))
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#define OPCODE(word) (BITS ((word), 27, 31))
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#define FIELDA(word) (BITS ((word), 21, 26))
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#define FIELDB(word) (BITS ((word), 15, 20))
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#define FIELDC(word) (BITS ((word), 9, 14))
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#define BIT(word,n) ((word) & (1 << n))
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#define BITS(word,s,e) (((word) << (31 - e)) >> (s + (31 - e)))
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#define OPCODE(word) (BITS ((word), 27, 31))
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#define FIELDA(word) (BITS ((word), 21, 26))
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#define FIELDB(word) (BITS ((word), 15, 20))
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#define FIELDC(word) (BITS ((word), 9, 14))
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/* FIELD D is signed in all of its uses, so we make sure argument is
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treated as signed for bit shifting purposes: */
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#define FIELDD(word) (BITS (((signed int)word), 0, 8))
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#define FIELDD(word) (BITS (((signed int)word), 0, 8))
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#define PUT_NEXT_WORD_IN(a) \
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do \
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@ -136,20 +136,35 @@
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(IS_REG (x) ? cb1"%r"ca1 : \
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usesAuxReg ? cb"%a"ca : \
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IS_SMALL (x) ? cb"%d"ca : cb"%h"ca))
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#define WRITE_FORMAT_RB() strcat (formatString, "]")
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#define WRITE_FORMAT_RB() strcat (formatString, "]")
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#define WRITE_COMMENT(str) (state->comm[state->commNum++] = (str))
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#define WRITE_NOP_COMMENT() if (!fieldAisReg && !flag) WRITE_COMMENT ("nop");
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#define WRITE_NOP_COMMENT() if (!fieldAisReg && !flag) WRITE_COMMENT ("nop");
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#define NEXT_WORD(x) (offset += 4, state->words[x])
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#define NEXT_WORD(x) (offset += 4, state->words[x])
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#define add_target(x) (state->targets[state->tcnt++] = (x))
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#define add_target(x) (state->targets[state->tcnt++] = (x))
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static char comment_prefix[] = "\t; ";
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static const char *core_reg_name PARAMS ((struct arcDisState *, int));
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static const char *aux_reg_name PARAMS ((struct arcDisState *, int));
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static const char *cond_code_name PARAMS ((struct arcDisState *, int));
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static const char *instruction_name
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PARAMS ((struct arcDisState *, int, int, int *));
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static void mwerror PARAMS ((struct arcDisState *, const char *));
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static const char *post_address PARAMS ((struct arcDisState *, int));
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static void write_comments_
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PARAMS ((struct arcDisState *, int, int, long int));
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static void write_instr_name_
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PARAMS ((struct arcDisState *, const char *, int, int, int, int, int, int));
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static int dsmOneArcInst PARAMS ((bfd_vma, struct arcDisState *));
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static const char *_coreRegName PARAMS ((void *, int));
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static int decodeInstr PARAMS ((bfd_vma, disassemble_info *));
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static const char *
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core_reg_name (state, val)
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struct arcDisState * state;
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int val;
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int val;
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{
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if (state->coreRegName)
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return (*state->coreRegName)(state->_this, val);
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@ -159,7 +174,7 @@ core_reg_name (state, val)
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static const char *
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aux_reg_name (state, val)
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struct arcDisState * state;
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int val;
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int val;
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{
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if (state->auxRegName)
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return (*state->auxRegName)(state->_this, val);
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@ -169,7 +184,7 @@ aux_reg_name (state, val)
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static const char *
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cond_code_name (state, val)
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struct arcDisState * state;
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int val;
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int val;
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{
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if (state->condCodeName)
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return (*state->condCodeName)(state->_this, val);
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@ -181,7 +196,7 @@ instruction_name (state, op1, op2, flags)
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struct arcDisState * state;
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int op1;
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int op2;
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int * flags;
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int * flags;
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{
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if (state->instName)
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return (*state->instName)(state->_this, op1, op2, flags);
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@ -191,7 +206,7 @@ instruction_name (state, op1, op2, flags)
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static void
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mwerror (state, msg)
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struct arcDisState * state;
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const char * msg;
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const char * msg;
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{
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if (state->err != 0)
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(*state->err)(state->_this, (msg));
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@ -200,7 +215,7 @@ mwerror (state, msg)
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static const char *
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post_address (state, addr)
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struct arcDisState * state;
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int addr;
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int addr;
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{
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static char id[3 * ARRAY_SIZE (state->addresses)];
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int j, i = state->acnt;
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@ -213,47 +228,47 @@ post_address (state, addr)
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id[j+0] = '@';
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id[j+1] = '0'+i;
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id[j+2] = 0;
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return id + j;
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}
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return "";
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}
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static void
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static void
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my_sprintf (
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struct arcDisState * state,
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char * buf,
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const char * format,
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...)
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{
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char *bp;
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char *bp;
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const char *p;
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int size, leading_zero, regMap[2];
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long auxNum;
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va_list ap;
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va_start (ap, format);
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bp = buf;
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bp = buf;
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*bp = 0;
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p = format;
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auxNum = -1;
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regMap[0] = 0;
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regMap[1] = 0;
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while (1)
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while (1)
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switch (*p++)
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{
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case 0:
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goto DOCOMM; /* (return) */
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default:
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*bp++ = p[-1];
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default:
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*bp++ = p[-1];
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break;
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case '%':
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size = 0;
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leading_zero = 0;
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RETRY: ;
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switch (*p++)
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switch (*p++)
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{
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case '0':
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case '1':
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@ -279,25 +294,25 @@ my_sprintf (
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}
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#define inc_bp() bp = bp + strlen (bp)
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case 'h':
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case 'h':
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{
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unsigned u = va_arg (ap, int);
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/* Hex. We can change the format to 0x%08x in
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one place, here, if we wish.
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We add underscores for easy reading. */
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if (u > 65536)
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if (u > 65536)
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sprintf (bp, "0x%x_%04x", u >> 16, u & 0xffff);
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else
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else
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sprintf (bp, "0x%x", u);
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inc_bp ();
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}
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}
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break;
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case 'X': case 'x':
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case 'X': case 'x':
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{
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int val = va_arg (ap, int);
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if (size != 0)
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if (size != 0)
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if (leading_zero)
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sprintf (bp, "%0*x", size, val);
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else
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@ -307,10 +322,10 @@ my_sprintf (
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inc_bp ();
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}
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break;
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case 'd':
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case 'd':
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{
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int val = va_arg (ap, int);
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if (size != 0)
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sprintf (bp, "%*d", size, val);
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else
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@ -318,15 +333,15 @@ my_sprintf (
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inc_bp ();
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}
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break;
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case 'r':
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case 'r':
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{
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/* Register. */
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int val = va_arg (ap, int);
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#define REG2NAME(num, name) case num: sprintf (bp, ""name); \
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regMap[(num < 32) ? 0 : 1] |= 1 << (num - ((num < 32) ? 0 : 32)); break;
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switch (val)
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switch (val)
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{
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REG2NAME (26, "gp");
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REG2NAME (27, "fp");
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@ -349,15 +364,15 @@ my_sprintf (
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}
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inc_bp ();
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} break;
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case 'a':
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case 'a':
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{
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/* Aux Register. */
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int val = va_arg (ap, int);
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#define AUXREG2NAME(num, name) case num: sprintf (bp,name); break;
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switch (val)
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switch (val)
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{
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AUXREG2NAME (0x0, "status");
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AUXREG2NAME (0x1, "semaphore");
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@ -380,14 +395,14 @@ my_sprintf (
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inc_bp ();
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}
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break;
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case 's':
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case 's':
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{
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sprintf (bp, "%s", va_arg (ap, char *));
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inc_bp ();
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}
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break;
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default:
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fprintf (stderr, "?? format %c\n", p[-1]);
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break;
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@ -397,30 +412,30 @@ my_sprintf (
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DOCOMM: *bp = 0;
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}
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static void
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static void
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write_comments_(state, shimm, is_limm, limm_value)
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struct arcDisState * state;
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int shimm;
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int is_limm;
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long limm_value;
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{
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if (state->commentBuffer != 0)
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if (state->commentBuffer != 0)
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{
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int i;
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if (is_limm)
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if (is_limm)
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{
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const char *name = post_address (state, limm_value + shimm);
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if (*name != 0)
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WRITE_COMMENT (name);
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}
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for (i = 0; i < state->commNum; i++)
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for (i = 0; i < state->commNum; i++)
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{
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if (i == 0)
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strcpy (state->commentBuffer, comment_prefix);
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else
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strcat (state->commentBuffer, ", ");
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strcat (state->commentBuffer, ", ");
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strncat (state->commentBuffer, state->comm[i], sizeof (state->commentBuffer));
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}
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}
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@ -431,11 +446,11 @@ write_comments_(state, shimm, is_limm, limm_value)
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static const char *condName[] = {
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/* 0..15. */
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"" , "z" , "nz" , "p" , "n" , "c" , "nc" , "v" ,
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"" , "z" , "nz" , "p" , "n" , "c" , "nc" , "v" ,
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"nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz"
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};
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static void
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static void
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write_instr_name_(state, instrName, cond, condCodeIsPartOfName, flag, signExtend, addrWriteBack, directMem)
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struct arcDisState * state;
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const char * instrName;
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@ -448,7 +463,7 @@ write_instr_name_(state, instrName, cond, condCodeIsPartOfName, flag, signExtend
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{
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strcpy (state->instrBuffer, instrName);
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if (cond > 0)
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if (cond > 0)
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{
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const char *cc = 0;
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@ -469,7 +484,7 @@ write_instr_name_(state, instrName, cond, condCodeIsPartOfName, flag, signExtend
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if (flag)
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strcat (state->instrBuffer, ".f");
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switch (state->nullifyMode)
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switch (state->nullifyMode)
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{
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case BR_exec_always:
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strcat (state->instrBuffer, ".d");
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@ -498,16 +513,16 @@ write_instr_name_(state, instrName, cond, condCodeIsPartOfName, flag, signExtend
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} \
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while (0)
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enum {
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op_LD0 = 0, op_LD1 = 1, op_ST = 2, op_3 = 3,
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enum {
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op_LD0 = 0, op_LD1 = 1, op_ST = 2, op_3 = 3,
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op_BC = 4, op_BLC = 5, op_LPC = 6, op_JC = 7,
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op_ADD = 8, op_ADC = 9, op_SUB = 10, op_SBC = 11,
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op_ADD = 8, op_ADC = 9, op_SUB = 10, op_SBC = 11,
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op_AND = 12, op_OR = 13, op_BIC = 14, op_XOR = 15
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};
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extern disassemble_info tm_print_insn_info;
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static int
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static int
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dsmOneArcInst (addr, state)
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bfd_vma addr;
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struct arcDisState * state;
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@ -536,22 +551,22 @@ dsmOneArcInst (addr, state)
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int flags;
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int ignoreFirstOpd;
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char formatString[60];
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state->instructionLen = 4;
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state->nullifyMode = BR_exec_when_no_jump;
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state->opWidth = 12;
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state->isBranch = 0;
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state->_mem_load = 0;
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state->_ea_present = 0;
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state->_load_len = 0;
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state->ea_reg1 = no_reg;
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state->ea_reg2 = no_reg;
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state->_offset = 0;
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if (! NEXT_WORD (0))
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return 0;
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state->_opcode = OPCODE (state->words[0]);
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instrName = 0;
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decodingClass = 0; /* default! */
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@ -566,10 +581,10 @@ dsmOneArcInst (addr, state)
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if (state->commentBuffer)
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state->commentBuffer[0] = '\0';
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switch (state->_opcode)
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switch (state->_opcode)
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{
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case op_LD0:
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switch (BITS (state->words[0],1,2))
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case op_LD0:
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switch (BITS (state->words[0],1,2))
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{
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case 0:
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instrName = "ld";
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@ -584,22 +599,22 @@ dsmOneArcInst (addr, state)
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state->_load_len = 2;
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break;
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default:
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instrName = "??? (0[3])";
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instrName = "??? (0[3])";
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state->flow = invalid_instr;
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break;
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}
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decodingClass = 5;
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decodingClass = 5;
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break;
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case op_LD1:
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if (BIT (state->words[0],13))
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case op_LD1:
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if (BIT (state->words[0],13))
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{
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instrName = "lr";
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instrName = "lr";
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decodingClass = 10;
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}
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else
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else
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{
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switch (BITS (state->words[0],10,11))
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switch (BITS (state->words[0],10,11))
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{
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case 0:
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instrName = "ld";
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@ -614,23 +629,23 @@ dsmOneArcInst (addr, state)
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state->_load_len = 2;
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break;
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default:
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instrName = "??? (1[3])";
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instrName = "??? (1[3])";
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state->flow = invalid_instr;
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break;
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}
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decodingClass = 6;
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}
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break;
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case op_ST:
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if (BIT (state->words[0],25))
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if (BIT (state->words[0],25))
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{
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instrName = "sr";
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decodingClass = 8;
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}
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else
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else
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{
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switch (BITS (state->words[0],22,23))
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switch (BITS (state->words[0],22,23))
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{
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case 0:
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instrName = "st";
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@ -642,20 +657,20 @@ dsmOneArcInst (addr, state)
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instrName = "stw";
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break;
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default:
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instrName = "??? (2[3])";
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instrName = "??? (2[3])";
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state->flow = invalid_instr;
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break;
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}
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decodingClass = 7;
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}
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break;
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case op_3:
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decodingClass = 1; /* default for opcode 3... */
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switch (FIELDC (state->words[0]))
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switch (FIELDC (state->words[0]))
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{
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case 0:
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instrName = "flag";
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instrName = "flag";
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decodingClass = 2;
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break;
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case 1:
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@ -682,10 +697,10 @@ dsmOneArcInst (addr, state)
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case 8:
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instrName = "extw";
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break;
|
||||
case 0x3f:
|
||||
case 0x3f:
|
||||
{
|
||||
decodingClass = 9;
|
||||
switch( FIELDD (state->words[0]) )
|
||||
switch( FIELDD (state->words[0]) )
|
||||
{
|
||||
case 0:
|
||||
instrName = "brk";
|
||||
|
|
@ -703,7 +718,7 @@ dsmOneArcInst (addr, state)
|
|||
}
|
||||
}
|
||||
break;
|
||||
|
||||
|
||||
/* ARC Extension Library Instructions
|
||||
NOTE: We assume that extension codes are these instrs. */
|
||||
default:
|
||||
|
|
@ -723,24 +738,24 @@ dsmOneArcInst (addr, state)
|
|||
break;
|
||||
|
||||
case op_BC:
|
||||
instrName = "b";
|
||||
instrName = "b";
|
||||
case op_BLC:
|
||||
if (!instrName)
|
||||
instrName = "bl";
|
||||
instrName = "bl";
|
||||
case op_LPC:
|
||||
if (!instrName)
|
||||
instrName = "lp";
|
||||
instrName = "lp";
|
||||
case op_JC:
|
||||
if (!instrName)
|
||||
{
|
||||
if (BITS (state->words[0],9,9))
|
||||
if (BITS (state->words[0],9,9))
|
||||
{
|
||||
instrName = "jl";
|
||||
instrName = "jl";
|
||||
is_linked = 1;
|
||||
}
|
||||
else
|
||||
else
|
||||
{
|
||||
instrName = "j";
|
||||
instrName = "j";
|
||||
is_linked = 0;
|
||||
}
|
||||
}
|
||||
|
|
@ -748,14 +763,14 @@ dsmOneArcInst (addr, state)
|
|||
decodingClass = ((state->_opcode == op_JC) ? 4 : 3);
|
||||
state->isBranch = 1;
|
||||
break;
|
||||
|
||||
|
||||
case op_ADD:
|
||||
case op_ADC:
|
||||
case op_AND:
|
||||
repeatsOp = (FIELDC (state->words[0]) == FIELDB (state->words[0]));
|
||||
decodingClass = 0;
|
||||
|
||||
switch (state->_opcode)
|
||||
switch (state->_opcode)
|
||||
{
|
||||
case op_ADD:
|
||||
instrName = (repeatsOp ? "asl" : "add");
|
||||
|
|
@ -768,7 +783,7 @@ dsmOneArcInst (addr, state)
|
|||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
|
||||
case op_SUB: instrName = "sub";
|
||||
break;
|
||||
case op_SBC: instrName = "sbc";
|
||||
|
|
@ -785,10 +800,10 @@ dsmOneArcInst (addr, state)
|
|||
instrName = "nop";
|
||||
decodingClass = 9;
|
||||
}
|
||||
else
|
||||
else
|
||||
instrName = "xor";
|
||||
break;
|
||||
|
||||
|
||||
default:
|
||||
instrName = instruction_name (state,state->_opcode,0,&flags);
|
||||
/* if (instrName) printf("FLAGS=0x%x\n", flags); */
|
||||
|
|
@ -801,14 +816,14 @@ dsmOneArcInst (addr, state)
|
|||
ignoreFirstOpd = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
fieldAisReg = fieldBisReg = fieldCisReg = 1; /* Assume regs for now. */
|
||||
flag = cond = is_shimm = is_limm = 0;
|
||||
state->nullifyMode = BR_exec_when_no_jump; /* 0 */
|
||||
signExtend = addrWriteBack = directMem = 0;
|
||||
usesAuxReg = 0;
|
||||
|
||||
switch (decodingClass)
|
||||
|
||||
switch (decodingClass)
|
||||
{
|
||||
case 0:
|
||||
CHECK_FIELD_A ();
|
||||
|
|
@ -816,9 +831,9 @@ dsmOneArcInst (addr, state)
|
|||
if (!repeatsOp)
|
||||
CHECK_FIELD_C ();
|
||||
CHECK_FLAG_COND_NULLIFY ();
|
||||
|
||||
|
||||
write_instr_name ();
|
||||
if (!ignoreFirstOpd)
|
||||
if (!ignoreFirstOpd)
|
||||
{
|
||||
WRITE_FORMAT_x (A);
|
||||
WRITE_FORMAT_COMMA_x (B);
|
||||
|
|
@ -827,7 +842,7 @@ dsmOneArcInst (addr, state)
|
|||
WRITE_NOP_COMMENT ();
|
||||
my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
|
||||
}
|
||||
else
|
||||
else
|
||||
{
|
||||
WRITE_FORMAT_x (B);
|
||||
if (!repeatsOp)
|
||||
|
|
@ -836,49 +851,49 @@ dsmOneArcInst (addr, state)
|
|||
}
|
||||
write_comments ();
|
||||
break;
|
||||
|
||||
|
||||
case 1:
|
||||
CHECK_FIELD_A ();
|
||||
CHECK_FIELD_B ();
|
||||
CHECK_FLAG_COND_NULLIFY ();
|
||||
|
||||
|
||||
write_instr_name ();
|
||||
if (!ignoreFirstOpd)
|
||||
if (!ignoreFirstOpd)
|
||||
{
|
||||
WRITE_FORMAT_x (A);
|
||||
WRITE_FORMAT_COMMA_x (B);
|
||||
WRITE_NOP_COMMENT ();
|
||||
my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB);
|
||||
my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB);
|
||||
}
|
||||
else
|
||||
else
|
||||
{
|
||||
WRITE_FORMAT_x (B);
|
||||
my_sprintf (state, state->operandBuffer, formatString, fieldB);
|
||||
my_sprintf (state, state->operandBuffer, formatString, fieldB);
|
||||
}
|
||||
write_comments ();
|
||||
break;
|
||||
|
||||
|
||||
case 2:
|
||||
CHECK_FIELD_B ();
|
||||
CHECK_FLAG_COND_NULLIFY ();
|
||||
flag = 0; /* this is the FLAG instruction -- it's redundant */
|
||||
|
||||
|
||||
write_instr_name ();
|
||||
WRITE_FORMAT_x (B);
|
||||
my_sprintf (state, state->operandBuffer, formatString, fieldB);
|
||||
write_comments ();
|
||||
break;
|
||||
|
||||
|
||||
case 3:
|
||||
fieldA = BITS (state->words[0],7,26) << 2;
|
||||
fieldA = (fieldA << 10) >> 10; /* make it signed */
|
||||
fieldA += addr + 4;
|
||||
CHECK_FLAG_COND_NULLIFY ();
|
||||
flag = 0;
|
||||
|
||||
|
||||
write_instr_name ();
|
||||
/* This address could be a label we know. Convert it. */
|
||||
if (state->_opcode != op_LPC /* LP */)
|
||||
if (state->_opcode != op_LPC /* LP */)
|
||||
{
|
||||
add_target (fieldA); /* For debugger. */
|
||||
state->flow = state->_opcode == op_BLC /* BL */
|
||||
|
|
@ -886,13 +901,13 @@ dsmOneArcInst (addr, state)
|
|||
: direct_jump;
|
||||
/* indirect calls are achieved by "lr blink,[status];
|
||||
lr dest<- func addr; j [dest]" */
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
strcat (formatString, "%s"); /* address/label name */
|
||||
my_sprintf (state, state->operandBuffer, formatString, post_address (state, fieldA));
|
||||
write_comments ();
|
||||
break;
|
||||
|
||||
|
||||
case 4:
|
||||
/* For op_JC -- jump to address specified.
|
||||
Also covers jump and link--bit 9 of the instr. word
|
||||
|
|
@ -900,8 +915,8 @@ dsmOneArcInst (addr, state)
|
|||
fieldA = 0;
|
||||
CHECK_FIELD_B ();
|
||||
CHECK_FLAG_COND_NULLIFY ();
|
||||
|
||||
if (!fieldBisReg)
|
||||
|
||||
if (!fieldBisReg)
|
||||
{
|
||||
fieldAisReg = 0;
|
||||
fieldA = (fieldB >> 25) & 0x7F; /* flags */
|
||||
|
|
@ -913,7 +928,7 @@ dsmOneArcInst (addr, state)
|
|||
if (is_linked && state->nullifyMode == BR_exec_when_jump)
|
||||
state->nullifyMode = BR_exec_when_no_jump;
|
||||
}
|
||||
else
|
||||
else
|
||||
{
|
||||
state->flow = is_linked ? indirect_call : indirect_jump;
|
||||
/* We should also treat this as indirect call if NOT linked
|
||||
|
|
@ -922,11 +937,11 @@ dsmOneArcInst (addr, state)
|
|||
* For now we can't detect such. */
|
||||
state->register_for_indirect_jump = fieldB;
|
||||
}
|
||||
|
||||
|
||||
write_instr_name ();
|
||||
strcat (formatString,
|
||||
strcat (formatString,
|
||||
IS_REG (B) ? "[%r]" : "%s"); /* address/label name */
|
||||
if (fieldA != 0)
|
||||
if (fieldA != 0)
|
||||
{
|
||||
fieldAisReg = 0;
|
||||
WRITE_FORMAT_COMMA_x (A);
|
||||
|
|
@ -934,11 +949,11 @@ dsmOneArcInst (addr, state)
|
|||
if (IS_REG (B))
|
||||
my_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA);
|
||||
else
|
||||
my_sprintf (state, state->operandBuffer, formatString,
|
||||
my_sprintf (state, state->operandBuffer, formatString,
|
||||
post_address (state, fieldB), fieldA);
|
||||
write_comments ();
|
||||
break;
|
||||
|
||||
|
||||
case 5:
|
||||
/* LD instruction.
|
||||
B and C can be regs, or one (both?) can be limm. */
|
||||
|
|
@ -959,29 +974,29 @@ dsmOneArcInst (addr, state)
|
|||
else
|
||||
state->_offset += fieldC;
|
||||
state->_mem_load = 1;
|
||||
|
||||
|
||||
directMem = BIT (state->words[0],5);
|
||||
addrWriteBack = BIT (state->words[0],3);
|
||||
signExtend = BIT (state->words[0],0);
|
||||
|
||||
|
||||
write_instr_name ();
|
||||
WRITE_FORMAT_x_COMMA_LB(A);
|
||||
if (fieldBisReg || fieldB != 0)
|
||||
WRITE_FORMAT_x_COMMA (B);
|
||||
else
|
||||
fieldB = fieldC;
|
||||
|
||||
|
||||
WRITE_FORMAT_x_RB (C);
|
||||
my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
|
||||
write_comments ();
|
||||
break;
|
||||
|
||||
|
||||
case 6:
|
||||
/* LD instruction. */
|
||||
CHECK_FIELD_B ();
|
||||
CHECK_FIELD_A ();
|
||||
fieldC = FIELDD (state->words[0]);
|
||||
|
||||
|
||||
if (dbg)
|
||||
printf ("6:b reg %d %d c 0x%x \n",
|
||||
fieldBisReg, fieldB, fieldC);
|
||||
|
|
@ -994,22 +1009,22 @@ dsmOneArcInst (addr, state)
|
|||
Say ea is not present, so only one of us will do the name lookup. */
|
||||
else
|
||||
state->_offset += fieldB, state->_ea_present = 0;
|
||||
|
||||
|
||||
directMem = BIT (state->words[0],14);
|
||||
addrWriteBack = BIT (state->words[0],12);
|
||||
signExtend = BIT (state->words[0],9);
|
||||
|
||||
|
||||
write_instr_name ();
|
||||
WRITE_FORMAT_x_COMMA_LB (A);
|
||||
if (!fieldBisReg)
|
||||
if (!fieldBisReg)
|
||||
{
|
||||
fieldB = state->_offset;
|
||||
WRITE_FORMAT_x_RB (B);
|
||||
}
|
||||
else
|
||||
else
|
||||
{
|
||||
WRITE_FORMAT_x (B);
|
||||
if (fieldC != 0 && !BIT (state->words[0],13))
|
||||
if (fieldC != 0 && !BIT (state->words[0],13))
|
||||
{
|
||||
fieldCisReg = 0;
|
||||
WRITE_FORMAT_COMMA_x_RB (C);
|
||||
|
|
@ -1020,13 +1035,13 @@ dsmOneArcInst (addr, state)
|
|||
my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC);
|
||||
write_comments ();
|
||||
break;
|
||||
|
||||
|
||||
case 7:
|
||||
/* ST instruction. */
|
||||
CHECK_FIELD_B();
|
||||
CHECK_FIELD_C();
|
||||
fieldA = FIELDD(state->words[0]); /* shimm */
|
||||
|
||||
|
||||
/* [B,A offset] */
|
||||
if (dbg) printf("7:b reg %d %x off %x\n",
|
||||
fieldBisReg,fieldB,fieldA);
|
||||
|
|
@ -1034,27 +1049,27 @@ dsmOneArcInst (addr, state)
|
|||
state->_offset = fieldA;
|
||||
if (fieldBisReg)
|
||||
state->ea_reg1 = fieldB;
|
||||
/* field B is either a shimm (same as fieldA) or limm (different!)
|
||||
/* field B is either a shimm (same as fieldA) or limm (different!)
|
||||
Say ea is not present, so only one of us will do the name lookup.
|
||||
(for is_limm we do the name translation here). */
|
||||
else
|
||||
else
|
||||
state->_offset += fieldB, state->_ea_present = 0;
|
||||
|
||||
|
||||
directMem = BIT(state->words[0],26);
|
||||
addrWriteBack = BIT(state->words[0],24);
|
||||
|
||||
|
||||
write_instr_name();
|
||||
WRITE_FORMAT_x_COMMA_LB(C);
|
||||
|
||||
if (!fieldBisReg)
|
||||
|
||||
if (!fieldBisReg)
|
||||
{
|
||||
fieldB = state->_offset;
|
||||
WRITE_FORMAT_x_RB(B);
|
||||
}
|
||||
else
|
||||
else
|
||||
{
|
||||
WRITE_FORMAT_x(B);
|
||||
if (fieldBisReg && fieldA != 0)
|
||||
if (fieldBisReg && fieldA != 0)
|
||||
{
|
||||
fieldAisReg = 0;
|
||||
WRITE_FORMAT_COMMA_x_RB(A);
|
||||
|
|
@ -1069,7 +1084,7 @@ dsmOneArcInst (addr, state)
|
|||
/* SR instruction */
|
||||
CHECK_FIELD_B();
|
||||
CHECK_FIELD_C();
|
||||
|
||||
|
||||
write_instr_name();
|
||||
WRITE_FORMAT_x_COMMA_LB(C);
|
||||
/* Try to print B as an aux reg if it is not a core reg. */
|
||||
|
|
@ -1079,17 +1094,17 @@ dsmOneArcInst (addr, state)
|
|||
my_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB);
|
||||
write_comments();
|
||||
break;
|
||||
|
||||
|
||||
case 9:
|
||||
write_instr_name();
|
||||
state->operandBuffer[0] = '\0';
|
||||
break;
|
||||
|
||||
|
||||
case 10:
|
||||
/* LR instruction */
|
||||
CHECK_FIELD_A();
|
||||
CHECK_FIELD_B();
|
||||
|
||||
|
||||
write_instr_name();
|
||||
WRITE_FORMAT_x_COMMA_LB(A);
|
||||
/* Try to print B as an aux reg if it is not a core reg. */
|
||||
|
|
@ -1099,18 +1114,18 @@ dsmOneArcInst (addr, state)
|
|||
my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB);
|
||||
write_comments();
|
||||
break;
|
||||
|
||||
|
||||
case 11:
|
||||
CHECK_COND();
|
||||
write_instr_name();
|
||||
state->operandBuffer[0] = '\0';
|
||||
break;
|
||||
|
||||
|
||||
default:
|
||||
mwerror (state, "Bad decoding class in ARC disassembler");
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
state->_cond = cond;
|
||||
return state->instructionLen = offset;
|
||||
}
|
||||
|
|
@ -1158,11 +1173,11 @@ decodeInstr (address, info)
|
|||
bfd_byte buffer[4];
|
||||
struct arcDisState s; /* ARC Disassembler state */
|
||||
void *stream = info->stream; /* output stream */
|
||||
fprintf_ftype func = info->fprintf_func;
|
||||
fprintf_ftype func = info->fprintf_func;
|
||||
int bytes;
|
||||
|
||||
|
||||
memset (&s, 0, sizeof(struct arcDisState));
|
||||
|
||||
|
||||
/* read first instruction */
|
||||
status = (*info->read_memory_func) (address, buffer, 4, info);
|
||||
if (status != 0)
|
||||
|
|
@ -1195,9 +1210,9 @@ decodeInstr (address, info)
|
|||
/* display the disassembly instruction */
|
||||
(*func) (stream, "%08x ", s.words[0]);
|
||||
(*func) (stream, " ");
|
||||
|
||||
|
||||
(*func) (stream, "%-10s ", s.instrBuffer);
|
||||
|
||||
|
||||
if (__TRANSLATION_REQUIRED(s))
|
||||
{
|
||||
bfd_vma addr = s.addresses[s.operandBuffer[1] - '0'];
|
||||
|
|
|
|||
|
|
@ -25,6 +25,20 @@
|
|||
#include "ia64-asmtab.h"
|
||||
#include "ia64-asmtab.c"
|
||||
|
||||
static void get_opc_prefix PARAMS ((const char **, char *));
|
||||
static short int find_string_ent PARAMS ((const char *));
|
||||
static short int find_main_ent PARAMS ((short int));
|
||||
static short int find_completer PARAMS ((short int, short int, const char *));
|
||||
static ia64_insn apply_completer PARAMS ((ia64_insn, int));
|
||||
static int extract_op_bits PARAMS ((int, int, int));
|
||||
static int extract_op PARAMS ((int, int *, unsigned int *));
|
||||
static int opcode_verify PARAMS ((ia64_insn, int, enum ia64_insn_type));
|
||||
static int locate_opcode_ent PARAMS ((ia64_insn, enum ia64_insn_type));
|
||||
static struct ia64_opcode *make_ia64_opcode
|
||||
PARAMS ((ia64_insn, const char *, int, int));
|
||||
static struct ia64_opcode *ia64_find_matching_opcode
|
||||
PARAMS ((const char *, short int));
|
||||
|
||||
const struct ia64_templ_desc ia64_templ_desc[16] =
|
||||
{
|
||||
{ 0, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_I }, "MII" }, /* 0 */
|
||||
|
|
@ -149,7 +163,7 @@ find_main_ent (nameindex)
|
|||
MAIN_ENT (starting from PREV_COMPLETER) that matches NAME, or
|
||||
return -1 if one does not exist. */
|
||||
|
||||
static short
|
||||
static short
|
||||
find_completer (main_ent, prev_completer, name)
|
||||
short main_ent;
|
||||
short prev_completer;
|
||||
|
|
@ -312,7 +326,7 @@ opcode_verify (opcode, place, type)
|
|||
{
|
||||
return 0;
|
||||
}
|
||||
if (main_table[place].flags
|
||||
if (main_table[place].flags
|
||||
& (IA64_OPCODE_F2_EQ_F3 | IA64_OPCODE_LEN_EQ_64MCNT))
|
||||
{
|
||||
const struct ia64_operand *o1, *o2;
|
||||
|
|
@ -481,7 +495,7 @@ locate_opcode_ent (opcode, type)
|
|||
|
||||
priority = ia64_dis_names[disent].priority;
|
||||
|
||||
if (opcode_verify (opcode, place, type)
|
||||
if (opcode_verify (opcode, place, type)
|
||||
&& priority > found_priority)
|
||||
{
|
||||
break;
|
||||
|
|
@ -610,7 +624,7 @@ ia64_dis_opcode (insn, type)
|
|||
{
|
||||
abort ();
|
||||
}
|
||||
return make_ia64_opcode (insn, name, place,
|
||||
return make_ia64_opcode (insn, name, place,
|
||||
completer_table[ci].dependencies);
|
||||
}
|
||||
}
|
||||
|
|
@ -646,7 +660,7 @@ ia64_find_matching_opcode (name, place)
|
|||
short completer = -1;
|
||||
|
||||
do {
|
||||
if (suffix[0] == '\0')
|
||||
if (suffix[0] == '\0')
|
||||
{
|
||||
completer = find_completer (place, completer, suffix);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue