Thu Mar 26 23:07:18 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
* config/tc-i386.c (md_assemble): Swap template arguments to CONSISTENT_REGISTER_MATCH macro in reverse direction test. This macro is currently symmetric, so passing them the wrong way didn't cause any problem, but may if the macro is changed in the future. After copying template to i.tm, use i.tm. rather than t-> to access fields, and make t a const* Move i.tm.operand_types[] swap to immediately after the copy.
This commit is contained in:
Ian Lance Taylor
parent
411589588a
commit
227b6b55fa
2 changed files with 84 additions and 76 deletions
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@ -1,3 +1,14 @@
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Thu Mar 26 23:07:18 1998 Alan Modra <alan@spri.levels.unisa.edu.au>
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* config/tc-i386.c (md_assemble): Swap template arguments to
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CONSISTENT_REGISTER_MATCH macro in reverse direction test.
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This macro is currently symmetric, so passing them the wrong
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way didn't cause any problem, but may if the macro is changed
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in the future.
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After copying template to i.tm, use i.tm. rather than t-> to
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access fields, and make t a const*
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Move i.tm.operand_types[] swap to immediately after the copy.
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start-sanitize-sky
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Thu Mar 26 13:29:59 1998 Doug Evans <devans@canuck.cygnus.com>
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@ -834,8 +834,8 @@ void
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md_assemble (line)
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char *line;
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{
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/* Holds template once we've found it. */
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template *t;
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/* Points to template once we've found it. */
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const template *t;
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/* Count the size of the instruction generated. */
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int insn_size = 0;
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@ -853,7 +853,7 @@ md_assemble (line)
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memset (im_expressions, '\0', sizeof (im_expressions));
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save_stack_p = save_stack; /* reset stack pointer */
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/* Fist parse an opcode & call i386_operand for the operands.
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/* First parse an opcode & call i386_operand for the operands.
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We assume that the scrubber has arranged it so that line[0] is the valid
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start of a (possibly prefixed) opcode. */
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{
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@ -1132,8 +1132,8 @@ md_assemble (line)
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if (!MATCH (overlap0, i.types[0]) ||
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!MATCH (overlap1, i.types[1]) ||
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!CONSISTENT_REGISTER_MATCH (overlap0, overlap1,
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t->operand_types[0],
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t->operand_types[1]))
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t->operand_types[1],
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t->operand_types[0]))
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{
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/* does not match either direction */
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continue;
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@ -1168,18 +1168,23 @@ md_assemble (line)
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/* Copy the template we found (we may change it!). */
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i.tm = *t;
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t = &i.tm; /* alter new copy of template */
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if (found_reverse_match)
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{
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i.tm.operand_types[0] = t->operand_types[1];
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i.tm.operand_types[1] = t->operand_types[0];
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}
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/* If the matched instruction specifies an explicit opcode suffix,
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use it - and make sure none has already been specified. */
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if (t->opcode_modifier & (Data16|Data32))
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if (i.tm.opcode_modifier & (Data16|Data32))
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{
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if (i.suffix)
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{
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as_bad ("extraneous opcode suffix given");
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return;
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}
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if (t->opcode_modifier & Data16)
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if (i.tm.opcode_modifier & Data16)
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i.suffix = WORD_OPCODE_SUFFIX;
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else
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i.suffix = DWORD_OPCODE_SUFFIX;
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@ -1276,19 +1281,11 @@ md_assemble (line)
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if (overlap0 & Imm1)
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i.imm_operands = 0; /* kludge for shift insns */
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if (found_reverse_match)
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{
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unsigned int save;
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save = t->operand_types[0];
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t->operand_types[0] = t->operand_types[1];
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t->operand_types[1] = save;
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}
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/* Finalize opcode. First, we change the opcode based on the operand
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size given by i.suffix: we never have to change things for byte insns,
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or when no opcode suffix is need to size the operands. */
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if (!i.suffix && (t->opcode_modifier & W))
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if (!i.suffix && (i.tm.opcode_modifier & W))
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{
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as_bad ("no opcode suffix given and no register operands; can't size instruction");
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return;
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@ -1297,15 +1294,15 @@ md_assemble (line)
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if (i.suffix && i.suffix != BYTE_OPCODE_SUFFIX)
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{
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/* Select between byte and word/dword operations. */
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if (t->opcode_modifier & W)
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t->base_opcode |= W;
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if (i.tm.opcode_modifier & W)
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i.tm.base_opcode |= W;
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/* Now select between word & dword operations via the
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operand size prefix. */
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if ((i.suffix == WORD_OPCODE_SUFFIX) ^ flag_16bit_code)
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{
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if (i.prefixes == MAX_PREFIXES)
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{
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as_bad ("%d prefixes given and 'w' opcode suffix gives too many prefixes",
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as_bad ("%d prefixes given and data size prefix gives too many prefixes",
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MAX_PREFIXES);
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return;
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}
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@ -1332,12 +1329,12 @@ md_assemble (line)
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if (found_reverse_match)
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{
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t->base_opcode |= found_reverse_match;
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i.tm.base_opcode |= found_reverse_match;
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}
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/* The imul $imm, %reg instruction is converted into
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imul $imm, %reg, %reg. */
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if (t->opcode_modifier & imulKludge)
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if (i.tm.opcode_modifier & imulKludge)
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{
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/* Pretend we saw the 3 operand case. */
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i.regs[2] = i.regs[1];
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@ -1345,7 +1342,7 @@ md_assemble (line)
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}
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/* The clr %reg instruction is converted into xor %reg, %reg. */
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if (t->opcode_modifier & iclrKludge)
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if (i.tm.opcode_modifier & iclrKludge)
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{
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i.regs[1] = i.regs[0];
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i.reg_operands = 2;
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@ -1356,7 +1353,7 @@ md_assemble (line)
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instructions, if the source operand is a register, we must reverse
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the i.rm.reg and i.rm.regmem fields. We accomplish this by faking
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that the two register operands were given in the reverse order. */
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if ((t->opcode_modifier & ReverseRegRegmem) && i.reg_operands == 2)
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if ((i.tm.opcode_modifier & ReverseRegRegmem) && i.reg_operands == 2)
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{
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unsigned int first_reg_operand = (i.types[0] & Reg) ? 0 : 1;
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unsigned int second_reg_operand = first_reg_operand + 1;
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@ -1365,40 +1362,40 @@ md_assemble (line)
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i.regs[second_reg_operand] = tmp;
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}
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if (t->opcode_modifier & ShortForm)
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if (i.tm.opcode_modifier & ShortForm)
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{
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/* The register or float register operand is in operand 0 or 1. */
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unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
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/* Register goes in low 3 bits of opcode. */
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t->base_opcode |= i.regs[op]->reg_num;
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i.tm.base_opcode |= i.regs[op]->reg_num;
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}
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else if (t->opcode_modifier & ShortFormW)
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else if (i.tm.opcode_modifier & ShortFormW)
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{
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/* Short form with 0x8 width bit. Register is always dest. operand */
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t->base_opcode |= i.regs[1]->reg_num;
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i.tm.base_opcode |= i.regs[1]->reg_num;
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if (i.suffix == WORD_OPCODE_SUFFIX ||
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i.suffix == DWORD_OPCODE_SUFFIX)
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t->base_opcode |= 0x8;
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i.tm.base_opcode |= 0x8;
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}
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else if (t->opcode_modifier & Seg2ShortForm)
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else if (i.tm.opcode_modifier & Seg2ShortForm)
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{
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if (t->base_opcode == POP_SEG_SHORT && i.regs[0]->reg_num == 1)
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if (i.tm.base_opcode == POP_SEG_SHORT && i.regs[0]->reg_num == 1)
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{
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as_bad ("you can't 'pop cs' on the 386.");
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return;
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}
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t->base_opcode |= (i.regs[0]->reg_num << 3);
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i.tm.base_opcode |= (i.regs[0]->reg_num << 3);
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}
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else if (t->opcode_modifier & Seg3ShortForm)
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else if (i.tm.opcode_modifier & Seg3ShortForm)
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{
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/* 'push %fs' is 0x0fa0; 'pop %fs' is 0x0fa1.
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'push %gs' is 0x0fa8; 'pop %fs' is 0x0fa9.
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So, only if i.regs[0]->reg_num == 5 (%gs) do we need
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to change the opcode. */
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if (i.regs[0]->reg_num == 5)
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t->base_opcode |= 0x08;
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i.tm.base_opcode |= 0x08;
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}
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else if ((t->base_opcode & ~DW) == MOV_AX_DISP32)
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else if ((i.tm.base_opcode & ~DW) == MOV_AX_DISP32)
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{
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/* This is a special non-modrm instruction
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that addresses memory with a 32-bit displacement mode anyway,
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@ -1406,12 +1403,12 @@ md_assemble (line)
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uses_mem_addrmode = 1;
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default_seg = &ds;
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}
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else if (t->opcode_modifier & Modrm)
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else if (i.tm.opcode_modifier & Modrm)
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{
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/* The opcode is completed (modulo t->extension_opcode which must
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be put into the modrm byte.
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Now, we make the modrm & index base bytes based on all the info
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we've collected. */
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/* The opcode is completed (modulo i.tm.extension_opcode which
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must be put into the modrm byte).
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Now, we make the modrm & index base bytes based on all the
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info we've collected. */
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/* i.reg_operands MUST be the number of real register operands;
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implicit registers do not count. */
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@ -1564,10 +1561,10 @@ md_assemble (line)
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}
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/* Fill in i.rm.reg or i.rm.regmem field with register
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operand (if any) based on
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t->extension_opcode. Again, we must be careful to
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make sure that segment/control/debug/test/MMX
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registers are coded into the i.rm.reg field. */
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operand (if any) based on i.tm.extension_opcode.
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Again, we must be careful to make sure that
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segment/control/debug/test/MMX registers are coded
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into the i.rm.reg field. */
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if (i.reg_operands)
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{
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unsigned int op =
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@ -1582,7 +1579,7 @@ md_assemble (line)
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: 2));
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/* If there is an extension opcode to put here, the
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register number must be put into the regmem field. */
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if (t->extension_opcode != None)
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if (i.tm.extension_opcode != None)
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i.rm.regmem = i.regs[op]->reg_num;
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else
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i.rm.reg = i.regs[op]->reg_num;
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@ -1595,8 +1592,8 @@ md_assemble (line)
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}
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/* Fill in i.rm.reg field with extension opcode (if any). */
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if (t->extension_opcode != None)
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i.rm.reg = t->extension_opcode;
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if (i.tm.extension_opcode != None)
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i.rm.reg = i.tm.extension_opcode;
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}
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if (i.rm.mode != 3)
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@ -1637,9 +1634,9 @@ md_assemble (line)
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}
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/* Handle conversion of 'int $3' --> special int3 insn. */
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if (t->base_opcode == INT_OPCODE && i.imms[0]->X_add_number == 3)
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if (i.tm.base_opcode == INT_OPCODE && i.imms[0]->X_add_number == 3)
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{
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t->base_opcode = INT3_OPCODE;
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i.tm.base_opcode = INT3_OPCODE;
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i.imm_operands = 0;
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}
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@ -1648,7 +1645,7 @@ md_assemble (line)
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register char *p;
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/* Output jumps. */
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if (t->opcode_modifier & Jump)
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if (i.tm.opcode_modifier & Jump)
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{
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unsigned long n = i.disps[0]->X_add_number;
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@ -1658,7 +1655,7 @@ md_assemble (line)
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{
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p = frag_more (2);
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insn_size += 2;
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p[0] = t->base_opcode;
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p[0] = i.tm.base_opcode;
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p[1] = n;
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}
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else
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@ -1675,7 +1672,7 @@ md_assemble (line)
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return;
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}
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if (t->base_opcode == JUMP_PC_RELATIVE)
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if (i.tm.base_opcode == JUMP_PC_RELATIVE)
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{ /* pace */
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/* unconditional jump */
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p = frag_more (1 + jmp_size);
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@ -1689,7 +1686,7 @@ md_assemble (line)
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p = frag_more (2 + jmp_size);
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insn_size += 2 + jmp_size;
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p[0] = TWO_BYTE_OPCODE_ESCAPE;
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p[1] = t->base_opcode + 0x10;
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p[1] = i.tm.base_opcode + 0x10;
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md_number_to_chars (&p[2], (valueT) n, jmp_size);
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}
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}
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@ -1708,7 +1705,7 @@ md_assemble (line)
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frag_grow (7);
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p = frag_more (1);
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insn_size += 1;
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p[0] = t->base_opcode;
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p[0] = i.tm.base_opcode;
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frag_var (rs_machine_dependent,
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6, /* 2 opcode/prefix + 4 displacement */
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1,
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@ -1719,9 +1716,9 @@ md_assemble (line)
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(offsetT) n, p);
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}
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}
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else if (t->opcode_modifier & (JumpByte | JumpDword))
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else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
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{
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int size = (t->opcode_modifier & JumpByte) ? 1 : 4;
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int size = (i.tm.opcode_modifier & JumpByte) ? 1 : 4;
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unsigned long n = i.disps[0]->X_add_number;
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unsigned char *q;
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@ -1748,8 +1745,8 @@ md_assemble (line)
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want to emit WORD_PREFIX_OPCODE, but I am keeping
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the old behaviour for safety. */
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if (IS_JUMP_ON_CX_ZERO (t->base_opcode)
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|| IS_LOOP_ECX_TIMES (t->base_opcode))
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if (IS_JUMP_ON_CX_ZERO (i.tm.base_opcode)
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|| IS_LOOP_ECX_TIMES (i.tm.base_opcode))
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FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
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else
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FRAG_APPEND_1_CHAR (WORD_PREFIX_OPCODE);
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@ -1764,9 +1761,9 @@ md_assemble (line)
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insn_size += 1;
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}
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if (fits_in_unsigned_byte (t->base_opcode))
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if (fits_in_unsigned_byte (i.tm.base_opcode))
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{
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FRAG_APPEND_1_CHAR (t->base_opcode);
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FRAG_APPEND_1_CHAR (i.tm.base_opcode);
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insn_size += 1;
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}
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else
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@ -1774,8 +1771,8 @@ md_assemble (line)
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p = frag_more (2); /* opcode can be at most two bytes */
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insn_size += 2;
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/* put out high byte first: can't use md_number_to_chars! */
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*p++ = (t->base_opcode >> 8) & 0xff;
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*p = t->base_opcode & 0xff;
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*p++ = (i.tm.base_opcode >> 8) & 0xff;
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*p = i.tm.base_opcode & 0xff;
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}
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p = frag_more (size);
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@ -1796,7 +1793,7 @@ md_assemble (line)
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}
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}
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else if (t->opcode_modifier & JumpInterSegment)
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else if (i.tm.opcode_modifier & JumpInterSegment)
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{
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if (flag_16bit_code)
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{
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@ -1806,7 +1803,7 @@ md_assemble (line)
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p = frag_more (1 + 2 + 4); /* 1 opcode; 2 segment; 4 offset */
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insn_size += 1 + 2 + 4;
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p[0] = t->base_opcode;
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p[0] = i.tm.base_opcode;
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if (i.imms[1]->X_op == O_constant)
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md_number_to_chars (p + 1, (valueT) i.imms[1]->X_add_number, 4);
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else
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@ -1830,39 +1827,39 @@ md_assemble (line)
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}
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/* Now the opcode; be careful about word order here! */
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if (fits_in_unsigned_byte (t->base_opcode))
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if (fits_in_unsigned_byte (i.tm.base_opcode))
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{
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FRAG_APPEND_1_CHAR (t->base_opcode);
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FRAG_APPEND_1_CHAR (i.tm.base_opcode);
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insn_size += 1;
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}
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else if (fits_in_unsigned_word (t->base_opcode))
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else if (fits_in_unsigned_word (i.tm.base_opcode))
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{
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p = frag_more (2);
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insn_size += 2;
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/* put out high byte first: can't use md_number_to_chars! */
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*p++ = (t->base_opcode >> 8) & 0xff;
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*p = t->base_opcode & 0xff;
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*p++ = (i.tm.base_opcode >> 8) & 0xff;
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*p = i.tm.base_opcode & 0xff;
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}
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else
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{ /* opcode is either 3 or 4 bytes */
|
||||
if (t->base_opcode & 0xff000000)
|
||||
if (i.tm.base_opcode & 0xff000000)
|
||||
{
|
||||
p = frag_more (4);
|
||||
insn_size += 4;
|
||||
*p++ = (t->base_opcode >> 24) & 0xff;
|
||||
*p++ = (i.tm.base_opcode >> 24) & 0xff;
|
||||
}
|
||||
else
|
||||
{
|
||||
p = frag_more (3);
|
||||
insn_size += 3;
|
||||
}
|
||||
*p++ = (t->base_opcode >> 16) & 0xff;
|
||||
*p++ = (t->base_opcode >> 8) & 0xff;
|
||||
*p = (t->base_opcode) & 0xff;
|
||||
*p++ = (i.tm.base_opcode >> 16) & 0xff;
|
||||
*p++ = (i.tm.base_opcode >> 8) & 0xff;
|
||||
*p = (i.tm.base_opcode) & 0xff;
|
||||
}
|
||||
|
||||
/* Now the modrm byte and base index byte (if present). */
|
||||
if (t->opcode_modifier & Modrm)
|
||||
if (i.tm.opcode_modifier & Modrm)
|
||||
{
|
||||
p = frag_more (1);
|
||||
insn_size += 1;
|
||||
|
|
@ -2193,7 +2190,7 @@ i386_operand (operand_string)
|
|||
i.mem_operands++;
|
||||
|
||||
/* Determine type of memory operand from opcode_suffix;
|
||||
no opcode suffix implies general memory references. */
|
||||
no opcode suffix implies general memory references. */
|
||||
switch (i.suffix)
|
||||
{
|
||||
case BYTE_OPCODE_SUFFIX:
|
||||
|
|
|
|||
Loading…
Reference in a new issue