* ppc-dis.c (powerpc_dialect): Handle "-Mpower5".
(print_ppc_disassembler_options): Document it. * ppc-opc.c (SCV_LEV): Define. (LEV): Allow optional operand. (POWER5): Define. (powerpc_opcodes): Extend "sc". Adjust "svc" and "svcl". Add "hrfid", "popcntb", "fsqrtes", "fsqrtes.", "fre" and "fre.".
This commit is contained in:
Alan Modra
parent
f4411256d5
commit
1ed8e1e4fb
3 changed files with 35 additions and 5 deletions
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@ -1,3 +1,13 @@
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2005-05-19 Anton Blanchard <anton@samba.org>
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* ppc-dis.c (powerpc_dialect): Handle "-Mpower5".
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(print_ppc_disassembler_options): Document it.
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* ppc-opc.c (SVC_LEV): Define.
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(LEV): Allow optional operand.
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(POWER5): Define.
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(powerpc_opcodes): Extend "sc". Adjust "svc" and "svcl". Add
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"hrfid", "popcntb", "fsqrtes", "fsqrtes.", "fre" and "fre.".
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2005-05-19 Kelley Cook <kcook@gcc.gnu.org>
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* Makefile.in: Regenerate.
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@ -71,6 +71,10 @@ powerpc_dialect (struct disassemble_info *info)
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&& strstr (info->disassembler_options, "power4") != NULL)
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dialect |= PPC_OPCODE_POWER4;
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if (info->disassembler_options
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&& strstr (info->disassembler_options, "power5") != NULL)
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dialect |= PPC_OPCODE_POWER4 | PPC_OPCODE_POWER5;
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if (info->disassembler_options
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&& strstr (info->disassembler_options, "any") != NULL)
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dialect |= PPC_OPCODE_ANY;
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@ -302,6 +306,7 @@ the -M switch:\n");
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fprintf (stream, " e500|e500x2 Disassemble the e500 instructions\n");
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fprintf (stream, " efs Disassemble the EFS instructions\n");
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fprintf (stream, " power4 Disassemble the Power4 instructions\n");
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fprintf (stream, " power5 Disassemble the Power5 instructions\n");
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fprintf (stream, " 32 Do not disassemble 64-bit instructions\n");
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fprintf (stream, " 64 Allow disassembly of 64-bit instructions\n");
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}
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@ -304,10 +304,14 @@ const struct powerpc_operand powerpc_operands[] =
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#define L FXM4 + 1
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{ 1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
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/* The LEV field in a POWER SC form instruction. */
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#define LEV L + 1
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/* The LEV field in a POWER SVC form instruction. */
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#define SVC_LEV L + 1
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{ 7, 5, NULL, NULL, 0 },
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/* The LEV field in an SC form instruction. */
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#define LEV SVC_LEV + 1
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{ 7, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },
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/* The LI field in an I form instruction. The lower two bits are
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forced to zero. */
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#define LI LEV + 1
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@ -1818,6 +1822,7 @@ extract_tbr (unsigned long insn,
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#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON
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#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
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#define POWER4 PPC_OPCODE_POWER4
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#define POWER5 PPC_OPCODE_POWER5
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#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC
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#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC
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#define PPC403 PPC_OPCODE_403
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@ -2749,9 +2754,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "bcla+", B(16,1,1), B_MASK, PPCCOM, { BOE, BI, BDPA } },
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{ "bcla", B(16,1,1), B_MASK, COM, { BO, BI, BDA } },
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{ "sc", SC(17,1,0), 0xffffffff, PPC, { 0 } },
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{ "svc", SC(17,0,0), SC_MASK, POWER, { LEV, FL1, FL2 } },
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{ "svcl", SC(17,0,1), SC_MASK, POWER, { LEV, FL1, FL2 } },
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{ "sc", SC(17,1,0), SC_MASK, PPC, { LEV } },
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{ "svc", SC(17,0,0), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
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{ "svcl", SC(17,0,1), SC_MASK, POWER, { SVC_LEV, FL1, FL2 } },
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{ "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } },
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{ "svcla", SC(17,1,1), SC_MASK, POWER, { SV } },
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@ -3008,6 +3013,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "crand", XL(19,257), XL_MASK, COM, { BT, BA, BB } },
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{ "hrfid", XL(19,274), 0xffffffff, POWER5, { 0 } },
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{ "crset", XL(19,289), XL_MASK, PPCCOM, { BT, BAT, BBA } },
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{ "creqv", XL(19,289), XL_MASK, COM, { BT, BA, BB } },
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@ -3435,6 +3442,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "lbzux", X(31,119), X_MASK, COM, { RT, RAL, RB } },
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{ "popcntb", X(31,122), XRB_MASK, POWER5, { RA, RS } },
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{ "not", XRC(31,124,0), X_MASK, COM, { RA, RS, RBS } },
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{ "nor", XRC(31,124,0), X_MASK, COM, { RA, RS, RB } },
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{ "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } },
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@ -4512,6 +4521,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "fmuls", A(59,25,0), AFRB_MASK, PPC, { FRT, FRA, FRC } },
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{ "fmuls.", A(59,25,1), AFRB_MASK, PPC, { FRT, FRA, FRC } },
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{ "fsqrtes", A(59,26,0), AFRAFRC_MASK, POWER5, { FRT, FRB } },
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{ "fsqrtes.", A(59,26,1), AFRAFRC_MASK, POWER5, { FRT, FRB } },
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{ "fmsubs", A(59,28,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
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{ "fmsubs.", A(59,28,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
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@ -4583,6 +4595,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "fsel", A(63,23,0), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
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{ "fsel.", A(63,23,1), A_MASK, PPC, { FRT,FRA,FRC,FRB } },
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{ "fre", A(63,24,0), AFRAFRC_MASK, POWER5, { FRT, FRB } },
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{ "fre.", A(63,24,1), AFRAFRC_MASK, POWER5, { FRT, FRB } },
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{ "fmul", A(63,25,0), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
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{ "fm", A(63,25,0), AFRB_MASK, PWRCOM, { FRT, FRA, FRC } },
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{ "fmul.", A(63,25,1), AFRB_MASK, PPCCOM, { FRT, FRA, FRC } },
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