* config/tc-mips.c (dummy_opcode): Delete.
(nop_insn, mips16_nop_insn): New variables. (NOP_INSN): New macro. (insn_length, create_insn, install_insn, move_insn, add_fixed_insn) (add_relaxed_insn, insert_into_history, emit_nop): New functions. (md_begin): Initialize nop_insn and mips16_nop_insn. (append_insn): Use the new emit_nop function to add nops, recording them in the history buffer. Use add_fixed_insn or add_relaxed_insn to reserve room for the instruction and install_insn to install the final form. Use insert_into_history to record the instruction in the history buffer. Use move_insn to do delay slot filling. (mips_emit_delays): Use add_fixed_insn instead of the emit_nop macro. (macro_build, mips16_macro_build, macro_build_lui, mips_ip) (mips16_ip): Use create_insn to initialize mips_cl_insns.
This commit is contained in:
Richard Sandiford
parent
bf12938eac
commit
1e91584932
2 changed files with 268 additions and 311 deletions
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@ -1,3 +1,20 @@
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2005-03-09 Richard Sandiford <rsandifo@redhat.com>
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* config/tc-mips.c (dummy_opcode): Delete.
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(nop_insn, mips16_nop_insn): New variables.
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(NOP_INSN): New macro.
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(insn_length, create_insn, install_insn, move_insn, add_fixed_insn)
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(add_relaxed_insn, insert_into_history, emit_nop): New functions.
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(md_begin): Initialize nop_insn and mips16_nop_insn.
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(append_insn): Use the new emit_nop function to add nops, recording
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them in the history buffer. Use add_fixed_insn or add_relaxed_insn
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to reserve room for the instruction and install_insn to install the
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final form. Use insert_into_history to record the instruction in
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the history buffer. Use move_insn to do delay slot filling.
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(mips_emit_delays): Use add_fixed_insn instead of the emit_nop macro.
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(macro_build, mips16_macro_build, macro_build_lui, mips_ip)
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(mips16_ip): Use create_insn to initialize mips_cl_insns.
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2005-03-09 Richard Sandiford <rsandifo@redhat.com>
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* config/tc-mips.c (INSERT_BITS, EXTRACT_BITS, INSERT_OPERAND)
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@ -560,9 +560,11 @@ static int mips_debug = 0;
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/* A list of previous instructions, with index 0 being the most recent. */
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static struct mips_cl_insn history[2];
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/* If we don't want information for a history[] entry, we
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point the insn_mo field at this dummy integer. */
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static const struct mips_opcode dummy_opcode = { NULL, NULL, 0, 0, 0, 0, 0 };
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/* Nop instructions used by emit_nop. */
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static struct mips_cl_insn nop_insn, mips16_nop_insn;
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/* The appropriate nop for the current mode. */
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#define NOP_INSN (mips_opts.mips16 ? &mips16_nop_insn : &nop_insn)
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/* If this is set, it points to a frag holding nop instructions which
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were inserted before the start of a noreorder section. If those
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@ -1159,6 +1161,130 @@ mips_target_format (void)
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}
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}
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/* Return the length of instruction INSN. */
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static inline unsigned int
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insn_length (const struct mips_cl_insn *insn)
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{
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if (!mips_opts.mips16)
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return 4;
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return insn->mips16_absolute_jump_p || insn->use_extend ? 4 : 2;
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}
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/* Initialise INSN from opcode entry MO. Leave its position unspecified. */
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static void
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create_insn (struct mips_cl_insn *insn, const struct mips_opcode *mo)
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{
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size_t i;
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insn->insn_mo = mo;
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insn->use_extend = FALSE;
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insn->extend = 0;
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insn->insn_opcode = mo->match;
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insn->frag = NULL;
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insn->where = 0;
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for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
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insn->fixp[i] = NULL;
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insn->fixed_p = (mips_opts.noreorder > 0);
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insn->noreorder_p = (mips_opts.noreorder > 0);
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insn->mips16_absolute_jump_p = 0;
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}
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/* Install INSN at the location specified by its "frag" and "where" fields. */
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static void
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install_insn (const struct mips_cl_insn *insn)
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{
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char *f = insn->frag->fr_literal + insn->where;
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if (!mips_opts.mips16)
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md_number_to_chars (f, insn->insn_opcode, 4);
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else if (insn->mips16_absolute_jump_p)
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{
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md_number_to_chars (f, insn->insn_opcode >> 16, 2);
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md_number_to_chars (f + 2, insn->insn_opcode & 0xffff, 2);
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}
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else
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{
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if (insn->use_extend)
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{
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md_number_to_chars (f, 0xf000 | insn->extend, 2);
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f += 2;
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}
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md_number_to_chars (f, insn->insn_opcode, 2);
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}
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}
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/* Move INSN to offset WHERE in FRAG. Adjust the fixups accordingly
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and install the opcode in the new location. */
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static void
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move_insn (struct mips_cl_insn *insn, fragS *frag, long where)
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{
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size_t i;
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insn->frag = frag;
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insn->where = where;
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for (i = 0; i < ARRAY_SIZE (insn->fixp); i++)
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if (insn->fixp[i] != NULL)
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{
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insn->fixp[i]->fx_frag = frag;
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insn->fixp[i]->fx_where = where;
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}
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install_insn (insn);
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}
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/* Add INSN to the end of the output. */
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static void
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add_fixed_insn (struct mips_cl_insn *insn)
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{
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char *f = frag_more (insn_length (insn));
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move_insn (insn, frag_now, f - frag_now->fr_literal);
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}
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/* Start a variant frag and move INSN to the start of the variant part,
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marking it as fixed. The other arguments are as for frag_var. */
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static void
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add_relaxed_insn (struct mips_cl_insn *insn, int max_chars, int var,
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relax_substateT subtype, symbolS *symbol, offsetT offset)
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{
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frag_grow (max_chars);
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move_insn (insn, frag_now, frag_more (0) - frag_now->fr_literal);
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insn->fixed_p = 1;
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frag_var (rs_machine_dependent, max_chars, var,
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subtype, symbol, offset, NULL);
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}
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/* Insert N copies of INSN into the history buffer, starting at
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position FIRST. Neither FIRST nor N need to be clipped. */
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static void
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insert_into_history (unsigned int first, unsigned int n,
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const struct mips_cl_insn *insn)
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{
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if (mips_relax.sequence != 2)
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{
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unsigned int i;
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for (i = ARRAY_SIZE (history); i-- > first;)
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if (i >= first + n)
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history[i] = history[i - n];
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else
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history[i] = *insn;
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}
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}
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/* Emit a nop instruction, recording it in the history buffer. */
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static void
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emit_nop (void)
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{
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add_fixed_insn (NOP_INSN);
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insert_into_history (0, 1, NOP_INSN);
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}
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/* This function is called once, at assembler startup time. It should
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set up all the tables, etc. that the MD part of the assembler will need. */
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@ -1192,6 +1318,11 @@ md_begin (void)
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{
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if (!validate_mips_insn (&mips_opcodes[i]))
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broken = 1;
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if (nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
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{
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create_insn (&nop_insn, mips_opcodes + i);
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nop_insn.fixed_p = 1;
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}
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}
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++i;
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}
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@ -1219,6 +1350,11 @@ md_begin (void)
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mips16_opcodes[i].name, mips16_opcodes[i].args);
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broken = 1;
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}
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if (mips16_nop_insn.insn_mo == NULL && strcmp (name, "nop") == 0)
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{
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create_insn (&mips16_nop_insn, mips16_opcodes + i);
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mips16_nop_insn.fixed_p = 1;
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}
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++i;
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}
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while (i < bfd_mips16_num_opcodes
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@ -1646,12 +1782,9 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
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bfd_reloc_code_real_type *reloc_type)
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{
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register unsigned long prev_pinfo, pinfo;
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char *f;
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fixS *fixp[3];
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int nops = 0;
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relax_stateT prev_insn_frag_type = 0;
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bfd_boolean relaxed_branch = FALSE;
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bfd_boolean force_new_frag = FALSE;
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/* Mark instruction labels in mips16 mode. */
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mips16_mark_labels ();
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@ -1684,12 +1817,6 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
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benefit hand written assembly code, and does not seem worth
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it. */
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/* This is how a NOP is emitted. */
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#define emit_nop() \
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(mips_opts.mips16 \
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? md_number_to_chars (frag_more (2), 0x6500, 2) \
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: md_number_to_chars (frag_more (4), 0, 4))
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/* The previous insn might require a delay slot, depending upon
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the contents of the current insn. */
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if (! mips_opts.mips16
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@ -2061,32 +2188,31 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
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&& !mips_opts.mips16)
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{
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relaxed_branch = TRUE;
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f = frag_var (rs_machine_dependent,
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relaxed_branch_length
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(NULL, NULL,
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(pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
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: (pinfo & INSN_COND_BRANCH_LIKELY) ? 1 : 0), 4,
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RELAX_BRANCH_ENCODE
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(pinfo & INSN_UNCOND_BRANCH_DELAY,
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pinfo & INSN_COND_BRANCH_LIKELY,
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pinfo & INSN_WRITE_GPR_31,
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0),
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address_expr->X_add_symbol,
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address_expr->X_add_number,
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0);
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add_relaxed_insn (ip, (relaxed_branch_length
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(NULL, NULL,
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(pinfo & INSN_UNCOND_BRANCH_DELAY) ? -1
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: (pinfo & INSN_COND_BRANCH_LIKELY) ? 1
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: 0)), 4,
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RELAX_BRANCH_ENCODE
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(pinfo & INSN_UNCOND_BRANCH_DELAY,
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pinfo & INSN_COND_BRANCH_LIKELY,
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pinfo & INSN_WRITE_GPR_31,
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0),
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address_expr->X_add_symbol,
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address_expr->X_add_number);
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*reloc_type = BFD_RELOC_UNUSED;
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}
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else if (*reloc_type > BFD_RELOC_UNUSED)
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{
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/* We need to set up a variant frag. */
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assert (mips_opts.mips16 && address_expr != NULL);
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f = frag_var (rs_machine_dependent, 4, 0,
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RELAX_MIPS16_ENCODE (*reloc_type - BFD_RELOC_UNUSED,
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mips16_small, mips16_ext,
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(prev_pinfo
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& INSN_UNCOND_BRANCH_DELAY),
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history[0].mips16_absolute_jump_p),
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make_expr_symbol (address_expr), 0, NULL);
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add_relaxed_insn (ip, 4, 0,
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RELAX_MIPS16_ENCODE
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(*reloc_type - BFD_RELOC_UNUSED,
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mips16_small, mips16_ext,
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prev_pinfo & INSN_UNCOND_BRANCH_DELAY,
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history[0].mips16_absolute_jump_p),
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make_expr_symbol (address_expr), 0);
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}
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else if (mips_opts.mips16
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&& ! ip->use_extend
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@ -2095,7 +2221,7 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
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/* Make sure there is enough room to swap this instruction with
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a following jump instruction. */
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frag_grow (6);
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f = frag_more (2);
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add_fixed_insn (ip);
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}
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else
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{
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@ -2119,10 +2245,14 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
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if (mips_relax.sequence != 1)
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mips_macro_warning.sizes[1] += 4;
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f = frag_more (4);
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if (mips_opts.mips16)
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{
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ip->fixed_p = 1;
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ip->mips16_absolute_jump_p = (*reloc_type == BFD_RELOC_MIPS16_JMP);
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}
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add_fixed_insn (ip);
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}
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fixp[0] = fixp[1] = fixp[2] = NULL;
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if (address_expr != NULL && *reloc_type <= BFD_RELOC_UNUSED)
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{
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if (address_expr->X_op == O_constant)
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@ -2203,11 +2333,11 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
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break;
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howto = bfd_reloc_type_lookup (stdoutput, reloc_type[i - 1]);
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fixp[0] = fix_new_exp (frag_now, f - frag_now->fr_literal,
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bfd_get_reloc_size(howto),
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address_expr,
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reloc_type[0] == BFD_RELOC_16_PCREL_S2,
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reloc_type[0]);
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ip->fixp[0] = fix_new_exp (ip->frag, ip->where,
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bfd_get_reloc_size (howto),
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address_expr,
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reloc_type[0] == BFD_RELOC_16_PCREL_S2,
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reloc_type[0]);
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/* These relocations can have an addend that won't fit in
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4 octets for 64bit assembly. */
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@ -2232,12 +2362,12 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
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|| reloc_type[0] == BFD_RELOC_MIPS16_GPREL
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|| reloc_type[0] == BFD_RELOC_MIPS16_HI16_S
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|| reloc_type[0] == BFD_RELOC_MIPS16_LO16))
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fixp[0]->fx_no_overflow = 1;
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ip->fixp[0]->fx_no_overflow = 1;
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if (mips_relax.sequence)
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{
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if (mips_relax.first_fixup == 0)
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mips_relax.first_fixup = fixp[0];
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mips_relax.first_fixup = ip->fixp[0];
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}
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else if (reloc_needs_lo_p (*reloc_type))
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{
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@ -2253,7 +2383,7 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
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hi_fixup->next = mips_hi_fixup_list;
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mips_hi_fixup_list = hi_fixup;
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}
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hi_fixup->fixp = fixp[0];
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hi_fixup->fixp = ip->fixp[0];
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hi_fixup->seg = now_seg;
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}
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@ -2265,33 +2395,17 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
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for (i = 1; i < 3; i++)
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if (reloc_type[i] != BFD_RELOC_UNUSED)
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{
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fixp[i] = fix_new (frag_now, fixp[0]->fx_where,
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fixp[0]->fx_size, NULL, 0,
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FALSE, reloc_type[i]);
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ip->fixp[i] = fix_new (ip->frag, ip->where,
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ip->fixp[0]->fx_size, NULL, 0,
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FALSE, reloc_type[i]);
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/* Use fx_tcbit to mark compound relocs. */
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fixp[0]->fx_tcbit = 1;
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fixp[i]->fx_tcbit = 1;
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ip->fixp[0]->fx_tcbit = 1;
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ip->fixp[i]->fx_tcbit = 1;
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}
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}
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}
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if (! mips_opts.mips16)
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md_number_to_chars (f, ip->insn_opcode, 4);
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else if (*reloc_type == BFD_RELOC_MIPS16_JMP)
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{
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md_number_to_chars (f, ip->insn_opcode >> 16, 2);
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md_number_to_chars (f + 2, ip->insn_opcode & 0xffff, 2);
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}
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else
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{
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if (ip->use_extend)
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{
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md_number_to_chars (f, 0xf000 | ip->extend, 2);
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f += 2;
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}
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md_number_to_chars (f, ip->insn_opcode, 2);
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}
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install_insn (ip);
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/* Update the register mask information. */
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if (! mips_opts.mips16)
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|
|
@ -2534,163 +2648,46 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
|
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portions of this object file; we could pick up the
|
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instruction at the destination, put it in the delay
|
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slot, and bump the destination address. */
|
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insert_into_history (0, 1, ip);
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emit_nop ();
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if (mips_relax.sequence)
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mips_relax.sizes[mips_relax.sequence - 1] += 4;
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/* Update the previous insn information. */
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history[1].insn_mo = ip->insn_mo;
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history[1].use_extend = ip->use_extend;
|
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history[1].extend = ip->extend;
|
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history[1].insn_opcode = ip->insn_opcode;
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history[0].insn_mo = &dummy_opcode;
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}
|
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else
|
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{
|
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/* It looks like we can actually do the swap. */
|
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if (! mips_opts.mips16)
|
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struct mips_cl_insn delay = history[0];
|
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if (mips_opts.mips16)
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{
|
||||
char *prev_f;
|
||||
char temp[4];
|
||||
|
||||
prev_f = history[0].frag->fr_literal + history[0].where;
|
||||
if (!relaxed_branch)
|
||||
{
|
||||
/* If this is not a relaxed branch, then just
|
||||
swap the instructions. */
|
||||
memcpy (temp, prev_f, 4);
|
||||
memcpy (prev_f, f, 4);
|
||||
memcpy (f, temp, 4);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* If this is a relaxed branch, then we move the
|
||||
instruction to be placed in the delay slot to
|
||||
the current frag, shrinking the fixed part of
|
||||
the originating frag. If the branch occupies
|
||||
the tail of the latter, we move it backwards,
|
||||
into the space freed by the moved instruction. */
|
||||
f = frag_more (4);
|
||||
memcpy (f, prev_f, 4);
|
||||
history[0].frag->fr_fix -= 4;
|
||||
if (history[0].frag->fr_type == rs_machine_dependent)
|
||||
memmove (prev_f, prev_f + 4, history[0].frag->fr_var);
|
||||
}
|
||||
|
||||
if (history[0].fixp[0])
|
||||
{
|
||||
history[0].fixp[0]->fx_frag = frag_now;
|
||||
history[0].fixp[0]->fx_where = f - frag_now->fr_literal;
|
||||
}
|
||||
if (history[0].fixp[1])
|
||||
{
|
||||
history[0].fixp[1]->fx_frag = frag_now;
|
||||
history[0].fixp[1]->fx_where = f - frag_now->fr_literal;
|
||||
}
|
||||
if (history[0].fixp[2])
|
||||
{
|
||||
history[0].fixp[2]->fx_frag = frag_now;
|
||||
history[0].fixp[2]->fx_where = f - frag_now->fr_literal;
|
||||
}
|
||||
if (history[0].fixp[0] && HAVE_NEWABI
|
||||
&& history[0].frag != frag_now
|
||||
&& (history[0].fixp[0]->fx_r_type
|
||||
== BFD_RELOC_MIPS_GOT_DISP
|
||||
|| (history[0].fixp[0]->fx_r_type
|
||||
== BFD_RELOC_MIPS_CALL16)))
|
||||
{
|
||||
/* To avoid confusion in tc_gen_reloc, we must
|
||||
ensure that this does not become a variant
|
||||
frag. */
|
||||
force_new_frag = TRUE;
|
||||
}
|
||||
|
||||
if (!relaxed_branch)
|
||||
{
|
||||
if (fixp[0])
|
||||
{
|
||||
fixp[0]->fx_frag = history[0].frag;
|
||||
fixp[0]->fx_where = history[0].where;
|
||||
}
|
||||
if (fixp[1])
|
||||
{
|
||||
fixp[1]->fx_frag = history[0].frag;
|
||||
fixp[1]->fx_where = history[0].where;
|
||||
}
|
||||
if (fixp[2])
|
||||
{
|
||||
fixp[2]->fx_frag = history[0].frag;
|
||||
fixp[2]->fx_where = history[0].where;
|
||||
}
|
||||
}
|
||||
else if (history[0].frag->fr_type == rs_machine_dependent)
|
||||
{
|
||||
if (fixp[0])
|
||||
fixp[0]->fx_where -= 4;
|
||||
if (fixp[1])
|
||||
fixp[1]->fx_where -= 4;
|
||||
if (fixp[2])
|
||||
fixp[2]->fx_where -= 4;
|
||||
}
|
||||
know (delay.frag == ip->frag);
|
||||
move_insn (ip, delay.frag, delay.where);
|
||||
move_insn (&delay, ip->frag, ip->where + insn_length (ip));
|
||||
}
|
||||
else if (relaxed_branch)
|
||||
{
|
||||
/* Add the delay slot instruction to the end of the
|
||||
current frag and shrink the fixed part of the
|
||||
original frag. If the branch occupies the tail of
|
||||
the latter, move it backwards to cover the gap. */
|
||||
delay.frag->fr_fix -= 4;
|
||||
if (delay.frag == ip->frag)
|
||||
move_insn (ip, ip->frag, ip->where - 4);
|
||||
add_fixed_insn (&delay);
|
||||
}
|
||||
else
|
||||
{
|
||||
char *prev_f;
|
||||
char temp[2];
|
||||
|
||||
assert (history[0].fixp[0] == NULL);
|
||||
assert (history[0].fixp[1] == NULL);
|
||||
assert (history[0].fixp[2] == NULL);
|
||||
prev_f = history[0].frag->fr_literal + history[0].where;
|
||||
memcpy (temp, prev_f, 2);
|
||||
memcpy (prev_f, f, 2);
|
||||
if (*reloc_type != BFD_RELOC_MIPS16_JMP)
|
||||
{
|
||||
assert (*reloc_type == BFD_RELOC_UNUSED);
|
||||
memcpy (f, temp, 2);
|
||||
}
|
||||
else
|
||||
{
|
||||
memcpy (f, f + 2, 2);
|
||||
memcpy (f + 2, temp, 2);
|
||||
}
|
||||
if (fixp[0])
|
||||
{
|
||||
fixp[0]->fx_frag = history[0].frag;
|
||||
fixp[0]->fx_where = history[0].where;
|
||||
}
|
||||
if (fixp[1])
|
||||
{
|
||||
fixp[1]->fx_frag = history[0].frag;
|
||||
fixp[1]->fx_where = history[0].where;
|
||||
}
|
||||
if (fixp[2])
|
||||
{
|
||||
fixp[2]->fx_frag = history[0].frag;
|
||||
fixp[2]->fx_where = history[0].where;
|
||||
}
|
||||
move_insn (&delay, ip->frag, ip->where);
|
||||
move_insn (ip, history[0].frag, history[0].where);
|
||||
}
|
||||
|
||||
/* Update the previous insn information; leave history[0]
|
||||
unchanged. */
|
||||
history[1].insn_mo = ip->insn_mo;
|
||||
history[1].use_extend = ip->use_extend;
|
||||
history[1].extend = ip->extend;
|
||||
history[1].insn_opcode = ip->insn_opcode;
|
||||
history[0] = *ip;
|
||||
delay.fixed_p = 1;
|
||||
insert_into_history (0, 1, &delay);
|
||||
}
|
||||
history[0].fixed_p = 1;
|
||||
|
||||
/* If that was an unconditional branch, forget the previous
|
||||
insn information. */
|
||||
if (pinfo & INSN_UNCOND_BRANCH_DELAY)
|
||||
{
|
||||
history[1].insn_mo = &dummy_opcode;
|
||||
history[0].insn_mo = &dummy_opcode;
|
||||
}
|
||||
|
||||
history[0].fixp[0] = NULL;
|
||||
history[0].fixp[1] = NULL;
|
||||
history[0].fixp[2] = NULL;
|
||||
history[0].mips16_absolute_jump_p = 0;
|
||||
mips_no_prev_insn (FALSE);
|
||||
}
|
||||
else if (pinfo & INSN_COND_BRANCH_LIKELY)
|
||||
{
|
||||
|
|
@ -2698,69 +2695,14 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
|
|||
is look at the target, copy the instruction found there
|
||||
into the delay slot, and increment the branch to jump to
|
||||
the next instruction. */
|
||||
insert_into_history (0, 1, ip);
|
||||
emit_nop ();
|
||||
/* Update the previous insn information. */
|
||||
history[1].insn_mo = ip->insn_mo;
|
||||
history[1].use_extend = ip->use_extend;
|
||||
history[1].extend = ip->extend;
|
||||
history[1].insn_opcode = ip->insn_opcode;
|
||||
history[0].insn_mo = &dummy_opcode;
|
||||
history[0].fixp[0] = NULL;
|
||||
history[0].fixp[1] = NULL;
|
||||
history[0].fixp[2] = NULL;
|
||||
history[0].mips16_absolute_jump_p = 0;
|
||||
history[0].fixed_p = 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Update the previous insn information. */
|
||||
if (nops > 0)
|
||||
history[1].insn_mo = &dummy_opcode;
|
||||
else
|
||||
{
|
||||
history[1].insn_mo = history[0].insn_mo;
|
||||
history[1].use_extend = history[0].use_extend;
|
||||
history[1].extend = history[0].extend;
|
||||
history[1].insn_opcode = history[0].insn_opcode;
|
||||
}
|
||||
history[0].insn_mo = ip->insn_mo;
|
||||
history[0].use_extend = ip->use_extend;
|
||||
history[0].extend = ip->extend;
|
||||
history[0].insn_opcode = ip->insn_opcode;
|
||||
history[0].fixed_p = (mips_opts.mips16
|
||||
&& (ip->use_extend
|
||||
|| *reloc_type > BFD_RELOC_UNUSED));
|
||||
history[0].fixp[0] = fixp[0];
|
||||
history[0].fixp[1] = fixp[1];
|
||||
history[0].fixp[2] = fixp[2];
|
||||
history[0].mips16_absolute_jump_p = (reloc_type[0]
|
||||
== BFD_RELOC_MIPS16_JMP);
|
||||
}
|
||||
|
||||
history[1].noreorder_p = history[0].noreorder_p;
|
||||
history[0].noreorder_p = 0;
|
||||
history[0].frag = frag_now;
|
||||
history[0].where = f - frag_now->fr_literal;
|
||||
}
|
||||
else if (mips_relax.sequence != 2)
|
||||
{
|
||||
/* We need to record a bit of information even when we are not
|
||||
reordering, in order to determine the base address for mips16
|
||||
PC relative relocs. */
|
||||
history[1].insn_mo = history[0].insn_mo;
|
||||
history[1].use_extend = history[0].use_extend;
|
||||
history[1].extend = history[0].extend;
|
||||
history[1].insn_opcode = history[0].insn_opcode;
|
||||
history[0].insn_mo = ip->insn_mo;
|
||||
history[0].use_extend = ip->use_extend;
|
||||
history[0].extend = ip->extend;
|
||||
history[0].insn_opcode = ip->insn_opcode;
|
||||
history[0].mips16_absolute_jump_p = (reloc_type[0]
|
||||
== BFD_RELOC_MIPS16_JMP);
|
||||
history[1].noreorder_p = history[0].noreorder_p;
|
||||
history[0].noreorder_p = 1;
|
||||
history[0].fixed_p = 1;
|
||||
insert_into_history (0, 1, ip);
|
||||
}
|
||||
else
|
||||
insert_into_history (0, 1, ip);
|
||||
|
||||
/* We just output an insn, so the next one doesn't have a label. */
|
||||
mips_clear_insn_labels ();
|
||||
|
|
@ -2773,19 +2715,24 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
|
|||
static void
|
||||
mips_no_prev_insn (int preserve)
|
||||
{
|
||||
size_t i;
|
||||
|
||||
if (! preserve)
|
||||
{
|
||||
history[0].insn_mo = &dummy_opcode;
|
||||
history[1].insn_mo = &dummy_opcode;
|
||||
prev_nop_frag = NULL;
|
||||
prev_nop_frag_holds = 0;
|
||||
prev_nop_frag_required = 0;
|
||||
prev_nop_frag_since = 0;
|
||||
for (i = 0; i < ARRAY_SIZE (history); i++)
|
||||
history[i] = (mips_opts.mips16 ? mips16_nop_insn : nop_insn);
|
||||
}
|
||||
history[0].fixed_p = 1;
|
||||
history[0].noreorder_p = 0;
|
||||
history[0].mips16_absolute_jump_p = 0;
|
||||
history[1].noreorder_p = 0;
|
||||
else
|
||||
for (i = 0; i < ARRAY_SIZE (history); i++)
|
||||
{
|
||||
history[i].fixed_p = 1;
|
||||
history[i].noreorder_p = 0;
|
||||
history[i].mips16_absolute_jump_p = 0;
|
||||
}
|
||||
mips_clear_insn_labels ();
|
||||
}
|
||||
|
||||
|
|
@ -2874,7 +2821,7 @@ mips_emit_delays (bfd_boolean insns)
|
|||
}
|
||||
|
||||
for (; nops > 0; --nops)
|
||||
emit_nop ();
|
||||
add_fixed_insn (NOP_INSN);
|
||||
|
||||
if (insns)
|
||||
{
|
||||
|
|
@ -2997,6 +2944,7 @@ macro_read_relocs (va_list *args, bfd_reloc_code_real_type *r)
|
|||
static void
|
||||
macro_build (expressionS *ep, const char *name, const char *fmt, ...)
|
||||
{
|
||||
const struct mips_opcode *mo;
|
||||
struct mips_cl_insn insn;
|
||||
bfd_reloc_code_real_type r[3];
|
||||
va_list args;
|
||||
|
|
@ -3013,30 +2961,26 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
|
|||
r[0] = BFD_RELOC_UNUSED;
|
||||
r[1] = BFD_RELOC_UNUSED;
|
||||
r[2] = BFD_RELOC_UNUSED;
|
||||
insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
|
||||
assert (insn.insn_mo);
|
||||
assert (strcmp (name, insn.insn_mo->name) == 0);
|
||||
mo = (struct mips_opcode *) hash_find (op_hash, name);
|
||||
assert (mo);
|
||||
assert (strcmp (name, mo->name) == 0);
|
||||
|
||||
/* Search until we get a match for NAME. */
|
||||
while (1)
|
||||
{
|
||||
/* It is assumed here that macros will never generate
|
||||
MDMX or MIPS-3D instructions. */
|
||||
if (strcmp (fmt, insn.insn_mo->args) == 0
|
||||
&& insn.insn_mo->pinfo != INSN_MACRO
|
||||
&& OPCODE_IS_MEMBER (insn.insn_mo,
|
||||
(mips_opts.isa
|
||||
| (file_ase_mips16 ? INSN_MIPS16 : 0)),
|
||||
/* Search until we get a match for NAME. It is assumed here that
|
||||
macros will never generate MDMX or MIPS-3D instructions. */
|
||||
while (strcmp (fmt, mo->args) != 0
|
||||
|| mo->pinfo == INSN_MACRO
|
||||
|| !OPCODE_IS_MEMBER (mo,
|
||||
(mips_opts.isa
|
||||
| (file_ase_mips16 ? INSN_MIPS16 : 0)),
|
||||
mips_opts.arch)
|
||||
&& (mips_opts.arch != CPU_R4650 || (insn.insn_mo->pinfo & FP_D) == 0))
|
||||
break;
|
||||
|
||||
++insn.insn_mo;
|
||||
assert (insn.insn_mo->name);
|
||||
assert (strcmp (name, insn.insn_mo->name) == 0);
|
||||
|| (mips_opts.arch == CPU_R4650 && (mo->pinfo & FP_D) != 0))
|
||||
{
|
||||
++mo;
|
||||
assert (mo->name);
|
||||
assert (strcmp (name, mo->name) == 0);
|
||||
}
|
||||
|
||||
insn.insn_opcode = insn.insn_mo->match;
|
||||
create_insn (&insn, mo);
|
||||
for (;;)
|
||||
{
|
||||
switch (*fmt++)
|
||||
|
|
@ -3219,25 +3163,23 @@ static void
|
|||
mips16_macro_build (expressionS *ep, const char *name, const char *fmt,
|
||||
va_list args)
|
||||
{
|
||||
struct mips_opcode *mo;
|
||||
struct mips_cl_insn insn;
|
||||
bfd_reloc_code_real_type r[3]
|
||||
= {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
|
||||
|
||||
insn.insn_mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
|
||||
assert (insn.insn_mo);
|
||||
assert (strcmp (name, insn.insn_mo->name) == 0);
|
||||
mo = (struct mips_opcode *) hash_find (mips16_op_hash, name);
|
||||
assert (mo);
|
||||
assert (strcmp (name, mo->name) == 0);
|
||||
|
||||
while (strcmp (fmt, insn.insn_mo->args) != 0
|
||||
|| insn.insn_mo->pinfo == INSN_MACRO)
|
||||
while (strcmp (fmt, mo->args) != 0 || mo->pinfo == INSN_MACRO)
|
||||
{
|
||||
++insn.insn_mo;
|
||||
assert (insn.insn_mo->name);
|
||||
assert (strcmp (name, insn.insn_mo->name) == 0);
|
||||
++mo;
|
||||
assert (mo->name);
|
||||
assert (strcmp (name, mo->name) == 0);
|
||||
}
|
||||
|
||||
insn.insn_opcode = insn.insn_mo->match;
|
||||
insn.use_extend = FALSE;
|
||||
|
||||
create_insn (&insn, mo);
|
||||
for (;;)
|
||||
{
|
||||
int c;
|
||||
|
|
@ -3363,6 +3305,7 @@ static void
|
|||
macro_build_lui (expressionS *ep, int regnum)
|
||||
{
|
||||
expressionS high_expr;
|
||||
const struct mips_opcode *mo;
|
||||
struct mips_cl_insn insn;
|
||||
bfd_reloc_code_real_type r[3]
|
||||
= {BFD_RELOC_UNUSED, BFD_RELOC_UNUSED, BFD_RELOC_UNUSED};
|
||||
|
|
@ -3394,10 +3337,10 @@ macro_build_lui (expressionS *ep, int regnum)
|
|||
*r = BFD_RELOC_HI16_S;
|
||||
}
|
||||
|
||||
insn.insn_mo = (struct mips_opcode *) hash_find (op_hash, name);
|
||||
assert (insn.insn_mo);
|
||||
assert (strcmp (name, insn.insn_mo->name) == 0);
|
||||
assert (strcmp (fmt, insn.insn_mo->args) == 0);
|
||||
mo = hash_find (op_hash, name);
|
||||
assert (strcmp (name, mo->name) == 0);
|
||||
assert (strcmp (fmt, mo->args) == 0);
|
||||
create_insn (&insn, mo);
|
||||
|
||||
insn.insn_opcode = insn.insn_mo->match;
|
||||
INSERT_OPERAND (RT, insn, regnum);
|
||||
|
|
@ -8018,8 +7961,7 @@ mips_ip (char *str, struct mips_cl_insn *ip)
|
|||
}
|
||||
}
|
||||
|
||||
ip->insn_mo = insn;
|
||||
ip->insn_opcode = insn->match;
|
||||
create_insn (ip, insn);
|
||||
insn_error = NULL;
|
||||
for (args = insn->args;; ++args)
|
||||
{
|
||||
|
|
@ -9123,9 +9065,7 @@ mips16_ip (char *str, struct mips_cl_insn *ip)
|
|||
{
|
||||
assert (strcmp (insn->name, str) == 0);
|
||||
|
||||
ip->insn_mo = insn;
|
||||
ip->insn_opcode = insn->match;
|
||||
ip->use_extend = FALSE;
|
||||
create_insn (ip, insn);
|
||||
imm_expr.X_op = O_absent;
|
||||
imm_reloc[0] = BFD_RELOC_UNUSED;
|
||||
imm_reloc[1] = BFD_RELOC_UNUSED;
|
||||
|
|
|
|||
Loading…
Reference in a new issue