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Add missing ARMv8-M special registers

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2016-08-26  Thomas Preud'homme  <thomas.preudhomme@arm.com>

gas/
	* config/tc-arm.c (v7m_psrs): Add MSPLIM, PSPLIM, MSPLIM_NS,
	PSPLIM_NS, PRIMASK_NS, BASEPRI_NS, FAULTMASK_NS, CONTROL_NS, SP_NS and
	their lowecase counterpart special registers.  Write register
	identifier in hex.
	* testsuite/gas/arm/archv8m-cmse-msr.s: Reorganize tests per
	operation, special register and then case.  Use different register for
	each operation.  Add tests for new special registers.
	* testsuite/gas/arm/archv8m-cmse-msr-base.d: Adapt expected result
	accordingly.
	* testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.
	* testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.

opcodes/
	* arm-dis.c (psr_name): Use hex as case labels.  Add detection for
	MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
	FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
This commit is contained in:
Thomas Preud'homme 2016-08-26 11:53:30 +01:00
parent 980aa3e6df
commit 1a336194b7
8 changed files with 366 additions and 80 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

14
gas/ChangeLog
View file

@ -1,3 +1,17 @@
2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (v7m_psrs): Add MSPLIM, PSPLIM, MSPLIM_NS,
PSPLIM_NS, PRIMASK_NS, BASEPRI_NS, FAULTMASK_NS, CONTROL_NS, SP_NS and
their lowecase counterpart special registers. Write register
identifier in hex.
* testsuite/gas/arm/archv8m-cmse-msr.s: Reorganize tests per
operation, special register and then case. Use different register for
each operation. Add tests for new special registers.
* testsuite/gas/arm/archv8m-cmse-msr-base.d: Adapt expected result
accordingly.
* testsuite/gas/arm/archv8m-cmse-msr-main.d: Likewise.
* testsuite/gas/arm/archv8m-main-dsp-4.d: Likewise.
2016-08-25 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.c (v7m_psrs): Remove msp_s, MSP_S, psp_s and PSP_S

45
gas/config/tc-arm.c
View file

@ -18798,24 +18798,33 @@ static const struct asm_psr psrs[] =
/* Table of V7M psr names. */
static const struct asm_psr v7m_psrs[] =
{
{"apsr", 0 }, {"APSR", 0 },
{"iapsr", 1 }, {"IAPSR", 1 },
{"eapsr", 2 }, {"EAPSR", 2 },
{"psr", 3 }, {"PSR", 3 },
{"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
{"ipsr", 5 }, {"IPSR", 5 },
{"epsr", 6 }, {"EPSR", 6 },
{"iepsr", 7 }, {"IEPSR", 7 },
{"msp", 8 }, {"MSP", 8 },
{"psp", 9 }, {"PSP", 9 },
{"primask", 16}, {"PRIMASK", 16},
{"basepri", 17}, {"BASEPRI", 17},
{"basepri_max", 18}, {"BASEPRI_MAX", 18},
{"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
{"faultmask", 19}, {"FAULTMASK", 19},
{"control", 20}, {"CONTROL", 20},
{"msp_ns", 0x88}, {"MSP_NS", 0x88},
{"psp_ns", 0x89}, {"PSP_NS", 0x89}
{"apsr", 0x0 }, {"APSR", 0x0 },
{"iapsr", 0x1 }, {"IAPSR", 0x1 },
{"eapsr", 0x2 }, {"EAPSR", 0x2 },
{"psr", 0x3 }, {"PSR", 0x3 },
{"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
{"ipsr", 0x5 }, {"IPSR", 0x5 },
{"epsr", 0x6 }, {"EPSR", 0x6 },
{"iepsr", 0x7 }, {"IEPSR", 0x7 },
{"msp", 0x8 }, {"MSP", 0x8 },
{"psp", 0x9 }, {"PSP", 0x9 },
{"msplim", 0xa }, {"MSPLIM", 0xa },
{"psplim", 0xb }, {"PSPLIM", 0xb },
{"primask", 0x10}, {"PRIMASK", 0x10},
{"basepri", 0x11}, {"BASEPRI", 0x11},
{"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
{"basepri_max", 0x12}, {"BASEPRI_MASK", 0x12}, /* Typo, preserved for backwards compatibility. */
{"faultmask", 0x13}, {"FAULTMASK", 0x13},
{"control", 0x14}, {"CONTROL", 0x14},
{"msp_ns", 0x88}, {"MSP_NS", 0x88},
{"psp_ns", 0x89}, {"PSP_NS", 0x89},
{"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
{"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
{"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
{"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
{"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
{"control_ns", 0x94}, {"CONTROL_NS", 0x94},
{"sp_ns", 0x98}, {"SP_NS", 0x98 }
};
/* Table of all shift-in-operand names. */

76
gas/testsuite/gas/arm/archv8m-cmse-msr-base.d
View file

@ -6,19 +6,71 @@
.*: +file format .*arm.*
Disassembly of section .text:
0+.* <[^>]*> f380 8808 msr MSP, r0
0+.* <[^>]*> f380 8888 msr MSP_NS, r0
0+.* <[^>]*> f380 8809 msr PSP, r0
0+.* <[^>]*> f380 8889 msr PSP_NS, r0
0+.* <[^>]*> f380 8808 msr MSP, r0
0+.* <[^>]*> f380 8888 msr MSP_NS, r0
0+.* <[^>]*> f380 8809 msr PSP, r0
0+.* <[^>]*> f380 8889 msr PSP_NS, r0
0+.* <[^>]*> f3ef 8008 mrs r0, MSP
0+.* <[^>]*> f3ef 8088 mrs r0, MSP_NS
0+.* <[^>]*> f3ef 8009 mrs r0, PSP
0+.* <[^>]*> f3ef 8089 mrs r0, PSP_NS
0+.* <[^>]*> f3ef 8008 mrs r0, MSP
0+.* <[^>]*> f3ef 8088 mrs r0, MSP_NS
0+.* <[^>]*> f3ef 8009 mrs r0, PSP
0+.* <[^>]*> f3ef 8089 mrs r0, PSP_NS
0+.* <[^>]*> f3ef 8109 mrs r1, PSP
0+.* <[^>]*> f3ef 8189 mrs r1, PSP_NS
0+.* <[^>]*> f3ef 8109 mrs r1, PSP
0+.* <[^>]*> f3ef 8189 mrs r1, PSP_NS
0+.* <[^>]*> f3ef 820a mrs r2, MSPLIM
0+.* <[^>]*> f3ef 828a mrs r2, MSPLIM_NS
0+.* <[^>]*> f3ef 820a mrs r2, MSPLIM
0+.* <[^>]*> f3ef 828a mrs r2, MSPLIM_NS
0+.* <[^>]*> f3ef 830b mrs r3, PSPLIM
0+.* <[^>]*> f3ef 838b mrs r3, PSPLIM_NS
0+.* <[^>]*> f3ef 830b mrs r3, PSPLIM
0+.* <[^>]*> f3ef 838b mrs r3, PSPLIM_NS
0+.* <[^>]*> f3ef 8410 mrs r4, PRIMASK
0+.* <[^>]*> f3ef 8490 mrs r4, PRIMASK_NS
0+.* <[^>]*> f3ef 8410 mrs r4, PRIMASK
0+.* <[^>]*> f3ef 8490 mrs r4, PRIMASK_NS
0+.* <[^>]*> f3ef 8511 mrs r5, BASEPRI
0+.* <[^>]*> f3ef 8591 mrs r5, BASEPRI_NS
0+.* <[^>]*> f3ef 8511 mrs r5, BASEPRI
0+.* <[^>]*> f3ef 8591 mrs r5, BASEPRI_NS
0+.* <[^>]*> f3ef 8613 mrs r6, FAULTMASK
0+.* <[^>]*> f3ef 8693 mrs r6, FAULTMASK_NS
0+.* <[^>]*> f3ef 8613 mrs r6, FAULTMASK
0+.* <[^>]*> f3ef 8693 mrs r6, FAULTMASK_NS
0+.* <[^>]*> f3ef 8714 mrs r7, CONTROL
0+.* <[^>]*> f3ef 8794 mrs r7, CONTROL_NS
0+.* <[^>]*> f3ef 8714 mrs r7, CONTROL
0+.* <[^>]*> f3ef 8794 mrs r7, CONTROL_NS
0+.* <[^>]*> f3ef 8898 mrs r8, SP_NS
0+.* <[^>]*> f3ef 8898 mrs r8, SP_NS
0+.* <[^>]*> f380 8808 msr MSP, r0
0+.* <[^>]*> f380 8888 msr MSP_NS, r0
0+.* <[^>]*> f380 8808 msr MSP, r0
0+.* <[^>]*> f380 8888 msr MSP_NS, r0
0+.* <[^>]*> f381 8809 msr PSP, r1
0+.* <[^>]*> f381 8889 msr PSP_NS, r1
0+.* <[^>]*> f381 8809 msr PSP, r1
0+.* <[^>]*> f381 8889 msr PSP_NS, r1
0+.* <[^>]*> f382 880a msr MSPLIM, r2
0+.* <[^>]*> f382 888a msr MSPLIM_NS, r2
0+.* <[^>]*> f382 880a msr MSPLIM, r2
0+.* <[^>]*> f382 888a msr MSPLIM_NS, r2
0+.* <[^>]*> f383 880b msr PSPLIM, r3
0+.* <[^>]*> f383 888b msr PSPLIM_NS, r3
0+.* <[^>]*> f383 880b msr PSPLIM, r3
0+.* <[^>]*> f383 888b msr PSPLIM_NS, r3
0+.* <[^>]*> f384 8810 msr PRIMASK, r4
0+.* <[^>]*> f384 8890 msr PRIMASK_NS, r4
0+.* <[^>]*> f384 8810 msr PRIMASK, r4
0+.* <[^>]*> f384 8890 msr PRIMASK_NS, r4
0+.* <[^>]*> f385 8811 msr BASEPRI, r5
0+.* <[^>]*> f385 8891 msr BASEPRI_NS, r5
0+.* <[^>]*> f385 8811 msr BASEPRI, r5
0+.* <[^>]*> f385 8891 msr BASEPRI_NS, r5
0+.* <[^>]*> f386 8813 msr FAULTMASK, r6
0+.* <[^>]*> f386 8893 msr FAULTMASK_NS, r6
0+.* <[^>]*> f386 8813 msr FAULTMASK, r6
0+.* <[^>]*> f386 8893 msr FAULTMASK_NS, r6
0+.* <[^>]*> f387 8814 msr CONTROL, r7
0+.* <[^>]*> f387 8894 msr CONTROL_NS, r7
0+.* <[^>]*> f387 8814 msr CONTROL, r7
0+.* <[^>]*> f387 8894 msr CONTROL_NS, r7
0+.* <[^>]*> f388 8898 msr SP_NS, r8
0+.* <[^>]*> f388 8898 msr SP_NS, r8

76
gas/testsuite/gas/arm/archv8m-cmse-msr-main.d
View file

@ -6,19 +6,71 @@
.*: +file format .*arm.*
Disassembly of section .text:
0+.* <[^>]*> f380 8808 msr MSP, r0
0+.* <[^>]*> f380 8888 msr MSP_NS, r0
0+.* <[^>]*> f380 8809 msr PSP, r0
0+.* <[^>]*> f380 8889 msr PSP_NS, r0
0+.* <[^>]*> f380 8808 msr MSP, r0
0+.* <[^>]*> f380 8888 msr MSP_NS, r0
0+.* <[^>]*> f380 8809 msr PSP, r0
0+.* <[^>]*> f380 8889 msr PSP_NS, r0
0+.* <[^>]*> f3ef 8008 mrs r0, MSP
0+.* <[^>]*> f3ef 8088 mrs r0, MSP_NS
0+.* <[^>]*> f3ef 8009 mrs r0, PSP
0+.* <[^>]*> f3ef 8089 mrs r0, PSP_NS
0+.* <[^>]*> f3ef 8008 mrs r0, MSP
0+.* <[^>]*> f3ef 8088 mrs r0, MSP_NS
0+.* <[^>]*> f3ef 8009 mrs r0, PSP
0+.* <[^>]*> f3ef 8089 mrs r0, PSP_NS
0+.* <[^>]*> f3ef 8109 mrs r1, PSP
0+.* <[^>]*> f3ef 8189 mrs r1, PSP_NS
0+.* <[^>]*> f3ef 8109 mrs r1, PSP
0+.* <[^>]*> f3ef 8189 mrs r1, PSP_NS
0+.* <[^>]*> f3ef 820a mrs r2, MSPLIM
0+.* <[^>]*> f3ef 828a mrs r2, MSPLIM_NS
0+.* <[^>]*> f3ef 820a mrs r2, MSPLIM
0+.* <[^>]*> f3ef 828a mrs r2, MSPLIM_NS
0+.* <[^>]*> f3ef 830b mrs r3, PSPLIM
0+.* <[^>]*> f3ef 838b mrs r3, PSPLIM_NS
0+.* <[^>]*> f3ef 830b mrs r3, PSPLIM
0+.* <[^>]*> f3ef 838b mrs r3, PSPLIM_NS
0+.* <[^>]*> f3ef 8410 mrs r4, PRIMASK
0+.* <[^>]*> f3ef 8490 mrs r4, PRIMASK_NS
0+.* <[^>]*> f3ef 8410 mrs r4, PRIMASK
0+.* <[^>]*> f3ef 8490 mrs r4, PRIMASK_NS
0+.* <[^>]*> f3ef 8511 mrs r5, BASEPRI
0+.* <[^>]*> f3ef 8591 mrs r5, BASEPRI_NS
0+.* <[^>]*> f3ef 8511 mrs r5, BASEPRI
0+.* <[^>]*> f3ef 8591 mrs r5, BASEPRI_NS
0+.* <[^>]*> f3ef 8613 mrs r6, FAULTMASK
0+.* <[^>]*> f3ef 8693 mrs r6, FAULTMASK_NS
0+.* <[^>]*> f3ef 8613 mrs r6, FAULTMASK
0+.* <[^>]*> f3ef 8693 mrs r6, FAULTMASK_NS
0+.* <[^>]*> f3ef 8714 mrs r7, CONTROL
0+.* <[^>]*> f3ef 8794 mrs r7, CONTROL_NS
0+.* <[^>]*> f3ef 8714 mrs r7, CONTROL
0+.* <[^>]*> f3ef 8794 mrs r7, CONTROL_NS
0+.* <[^>]*> f3ef 8898 mrs r8, SP_NS
0+.* <[^>]*> f3ef 8898 mrs r8, SP_NS
0+.* <[^>]*> f380 8808 msr MSP, r0
0+.* <[^>]*> f380 8888 msr MSP_NS, r0
0+.* <[^>]*> f380 8808 msr MSP, r0
0+.* <[^>]*> f380 8888 msr MSP_NS, r0
0+.* <[^>]*> f381 8809 msr PSP, r1
0+.* <[^>]*> f381 8889 msr PSP_NS, r1
0+.* <[^>]*> f381 8809 msr PSP, r1
0+.* <[^>]*> f381 8889 msr PSP_NS, r1
0+.* <[^>]*> f382 880a msr MSPLIM, r2
0+.* <[^>]*> f382 888a msr MSPLIM_NS, r2
0+.* <[^>]*> f382 880a msr MSPLIM, r2
0+.* <[^>]*> f382 888a msr MSPLIM_NS, r2
0+.* <[^>]*> f383 880b msr PSPLIM, r3
0+.* <[^>]*> f383 888b msr PSPLIM_NS, r3
0+.* <[^>]*> f383 880b msr PSPLIM, r3
0+.* <[^>]*> f383 888b msr PSPLIM_NS, r3
0+.* <[^>]*> f384 8810 msr PRIMASK, r4
0+.* <[^>]*> f384 8890 msr PRIMASK_NS, r4
0+.* <[^>]*> f384 8810 msr PRIMASK, r4
0+.* <[^>]*> f384 8890 msr PRIMASK_NS, r4
0+.* <[^>]*> f385 8811 msr BASEPRI, r5
0+.* <[^>]*> f385 8891 msr BASEPRI_NS, r5
0+.* <[^>]*> f385 8811 msr BASEPRI, r5
0+.* <[^>]*> f385 8891 msr BASEPRI_NS, r5
0+.* <[^>]*> f386 8813 msr FAULTMASK, r6
0+.* <[^>]*> f386 8893 msr FAULTMASK_NS, r6
0+.* <[^>]*> f386 8813 msr FAULTMASK, r6
0+.* <[^>]*> f386 8893 msr FAULTMASK_NS, r6
0+.* <[^>]*> f387 8814 msr CONTROL, r7
0+.* <[^>]*> f387 8894 msr CONTROL_NS, r7
0+.* <[^>]*> f387 8814 msr CONTROL, r7
0+.* <[^>]*> f387 8894 msr CONTROL_NS, r7
0+.* <[^>]*> f388 8898 msr SP_NS, r8
0+.* <[^>]*> f388 8898 msr SP_NS, r8

116
gas/testsuite/gas/arm/archv8m-cmse-msr.s
View file

@ -1,17 +1,109 @@
T:
msr MSP, r0
msr MSP_NS, r0
msr PSP, r0
msr PSP_NS, r0
msr msp, r0
msr msp_ns, r0
msr psp, r0
msr psp_ns, r0
## MRS ##
# MSP
mrs r0, MSP
mrs r0, MSP_NS
mrs r0, PSP
mrs r0, PSP_NS
mrs r0, msp
mrs r0, msp_ns
mrs r0, psp
mrs r0, psp_ns
# PSP
mrs r1, PSP
mrs r1, PSP_NS
mrs r1, psp
mrs r1, psp_ns
# MSPLIM
mrs r2, MSPLIM
mrs r2, MSPLIM_NS
mrs r2, msplim
mrs r2, msplim_ns
# PSPLIM
mrs r3, PSPLIM
mrs r3, PSPLIM_NS
mrs r3, psplim
mrs r3, psplim_ns
# PRIMASK
mrs r4, PRIMASK
mrs r4, PRIMASK_NS
mrs r4, primask
mrs r4, primask_ns
# BASEPRI
mrs r5, BASEPRI
mrs r5, BASEPRI_NS
mrs r5, basepri
mrs r5, basepri_ns
# FAULTMASK
mrs r6, FAULTMASK
mrs r6, FAULTMASK_NS
mrs r6, faultmask
mrs r6, faultmask_ns
# CONTROL
mrs r7, CONTROL
mrs r7, CONTROL_NS
mrs r7, control
mrs r7, control_ns
# SP_NS
mrs r8, SP_NS
mrs r8, sp_ns
## MSR ##
# MSP
msr MSP, r0
msr MSP_NS, r0
msr msp, r0
msr msp_ns, r0
# PSP
msr PSP, r1
msr PSP_NS, r1
msr psp, r1
msr psp_ns, r1
# MSPLIM
msr MSPLIM, r2
msr MSPLIM_NS, r2
msr msplim, r2
msr msplim_ns, r2
# PSPLIM
msr PSPLIM, r3
msr PSPLIM_NS, r3
msr psplim, r3
msr psplim_ns, r3
# PRIMASK
msr PRIMASK, r4
msr PRIMASK_NS, r4
msr primask, r4
msr primask_ns, r4
# BASEPRI
msr BASEPRI, r5
msr BASEPRI_NS, r5
msr basepri, r5
msr basepri_ns, r5
# FAULTMASK
msr FAULTMASK, r6
msr FAULTMASK_NS, r6
msr faultmask, r6
msr faultmask_ns, r6
# CONTROL
msr CONTROL, r7
msr CONTROL_NS, r7
msr control, r7
msr control_ns, r7
# SP_NS
msr SP_NS, r8
msr sp_ns, r8

76
gas/testsuite/gas/arm/archv8m-main-dsp-4.d
View file

@ -6,19 +6,71 @@
.*: +file format .*arm.*
Disassembly of section .text:
0+.* <[^>]*> f380 8808 msr MSP, r0
0+.* <[^>]*> f380 8888 msr MSP_NS, r0
0+.* <[^>]*> f380 8809 msr PSP, r0
0+.* <[^>]*> f380 8889 msr PSP_NS, r0
0+.* <[^>]*> f380 8808 msr MSP, r0
0+.* <[^>]*> f380 8888 msr MSP_NS, r0
0+.* <[^>]*> f380 8809 msr PSP, r0
0+.* <[^>]*> f380 8889 msr PSP_NS, r0
0+.* <[^>]*> f3ef 8008 mrs r0, MSP
0+.* <[^>]*> f3ef 8088 mrs r0, MSP_NS
0+.* <[^>]*> f3ef 8009 mrs r0, PSP
0+.* <[^>]*> f3ef 8089 mrs r0, PSP_NS
0+.* <[^>]*> f3ef 8008 mrs r0, MSP
0+.* <[^>]*> f3ef 8088 mrs r0, MSP_NS
0+.* <[^>]*> f3ef 8009 mrs r0, PSP
0+.* <[^>]*> f3ef 8089 mrs r0, PSP_NS
0+.* <[^>]*> f3ef 8109 mrs r1, PSP
0+.* <[^>]*> f3ef 8189 mrs r1, PSP_NS
0+.* <[^>]*> f3ef 8109 mrs r1, PSP
0+.* <[^>]*> f3ef 8189 mrs r1, PSP_NS
0+.* <[^>]*> f3ef 820a mrs r2, MSPLIM
0+.* <[^>]*> f3ef 828a mrs r2, MSPLIM_NS
0+.* <[^>]*> f3ef 820a mrs r2, MSPLIM
0+.* <[^>]*> f3ef 828a mrs r2, MSPLIM_NS
0+.* <[^>]*> f3ef 830b mrs r3, PSPLIM
0+.* <[^>]*> f3ef 838b mrs r3, PSPLIM_NS
0+.* <[^>]*> f3ef 830b mrs r3, PSPLIM
0+.* <[^>]*> f3ef 838b mrs r3, PSPLIM_NS
0+.* <[^>]*> f3ef 8410 mrs r4, PRIMASK
0+.* <[^>]*> f3ef 8490 mrs r4, PRIMASK_NS
0+.* <[^>]*> f3ef 8410 mrs r4, PRIMASK
0+.* <[^>]*> f3ef 8490 mrs r4, PRIMASK_NS
0+.* <[^>]*> f3ef 8511 mrs r5, BASEPRI
0+.* <[^>]*> f3ef 8591 mrs r5, BASEPRI_NS
0+.* <[^>]*> f3ef 8511 mrs r5, BASEPRI
0+.* <[^>]*> f3ef 8591 mrs r5, BASEPRI_NS
0+.* <[^>]*> f3ef 8613 mrs r6, FAULTMASK
0+.* <[^>]*> f3ef 8693 mrs r6, FAULTMASK_NS
0+.* <[^>]*> f3ef 8613 mrs r6, FAULTMASK
0+.* <[^>]*> f3ef 8693 mrs r6, FAULTMASK_NS
0+.* <[^>]*> f3ef 8714 mrs r7, CONTROL
0+.* <[^>]*> f3ef 8794 mrs r7, CONTROL_NS
0+.* <[^>]*> f3ef 8714 mrs r7, CONTROL
0+.* <[^>]*> f3ef 8794 mrs r7, CONTROL_NS
0+.* <[^>]*> f3ef 8898 mrs r8, SP_NS
0+.* <[^>]*> f3ef 8898 mrs r8, SP_NS
0+.* <[^>]*> f380 8808 msr MSP, r0
0+.* <[^>]*> f380 8888 msr MSP_NS, r0
0+.* <[^>]*> f380 8808 msr MSP, r0
0+.* <[^>]*> f380 8888 msr MSP_NS, r0
0+.* <[^>]*> f381 8809 msr PSP, r1
0+.* <[^>]*> f381 8889 msr PSP_NS, r1
0+.* <[^>]*> f381 8809 msr PSP, r1
0+.* <[^>]*> f381 8889 msr PSP_NS, r1
0+.* <[^>]*> f382 880a msr MSPLIM, r2
0+.* <[^>]*> f382 888a msr MSPLIM_NS, r2
0+.* <[^>]*> f382 880a msr MSPLIM, r2
0+.* <[^>]*> f382 888a msr MSPLIM_NS, r2
0+.* <[^>]*> f383 880b msr PSPLIM, r3
0+.* <[^>]*> f383 888b msr PSPLIM_NS, r3
0+.* <[^>]*> f383 880b msr PSPLIM, r3
0+.* <[^>]*> f383 888b msr PSPLIM_NS, r3
0+.* <[^>]*> f384 8810 msr PRIMASK, r4
0+.* <[^>]*> f384 8890 msr PRIMASK_NS, r4
0+.* <[^>]*> f384 8810 msr PRIMASK, r4
0+.* <[^>]*> f384 8890 msr PRIMASK_NS, r4
0+.* <[^>]*> f385 8811 msr BASEPRI, r5
0+.* <[^>]*> f385 8891 msr BASEPRI_NS, r5
0+.* <[^>]*> f385 8811 msr BASEPRI, r5
0+.* <[^>]*> f385 8891 msr BASEPRI_NS, r5
0+.* <[^>]*> f386 8813 msr FAULTMASK, r6
0+.* <[^>]*> f386 8893 msr FAULTMASK_NS, r6
0+.* <[^>]*> f386 8813 msr FAULTMASK, r6
0+.* <[^>]*> f386 8893 msr FAULTMASK_NS, r6
0+.* <[^>]*> f387 8814 msr CONTROL, r7
0+.* <[^>]*> f387 8894 msr CONTROL_NS, r7
0+.* <[^>]*> f387 8814 msr CONTROL, r7
0+.* <[^>]*> f387 8894 msr CONTROL_NS, r7
0+.* <[^>]*> f388 8898 msr SP_NS, r8
0+.* <[^>]*> f388 8898 msr SP_NS, r8

6
opcodes/ChangeLog
View file

@ -1,3 +1,9 @@
2016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
* arm-dis.c (psr_name): Use hex as case labels. Add detection for
MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
2016-08-24 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.

37
opcodes/arm-dis.c
View file

@ -5427,22 +5427,31 @@ psr_name (int regno)
{
switch (regno)
{
case 0: return "APSR";
case 1: return "IAPSR";
case 2: return "EAPSR";
case 3: return "PSR";
case 5: return "IPSR";
case 6: return "EPSR";
case 7: return "IEPSR";
case 8: return "MSP";
case 9: return "PSP";
case 16: return "PRIMASK";
case 17: return "BASEPRI";
case 18: return "BASEPRI_MAX";
case 19: return "FAULTMASK";
case 20: return "CONTROL";
case 0x0: return "APSR";
case 0x1: return "IAPSR";
case 0x2: return "EAPSR";
case 0x3: return "PSR";
case 0x5: return "IPSR";
case 0x6: return "EPSR";
case 0x7: return "IEPSR";
case 0x8: return "MSP";
case 0x9: return "PSP";
case 0xa: return "MSPLIM";
case 0xb: return "PSPLIM";
case 0x10: return "PRIMASK";
case 0x11: return "BASEPRI";
case 0x12: return "BASEPRI_MAX";
case 0x13: return "FAULTMASK";
case 0x14: return "CONTROL";
case 0x88: return "MSP_NS";
case 0x89: return "PSP_NS";
case 0x8a: return "MSPLIM_NS";
case 0x8b: return "PSPLIM_NS";
case 0x90: return "PRIMASK_NS";
case 0x91: return "BASEPRI_NS";
case 0x93: return "FAULTMASK_NS";
case 0x94: return "CONTROL_NS";
case 0x98: return "SP_NS";
default: return "<unknown>";
}
}