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Add support for new POWER ISA 3.0 instructions.

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opcodes/

	* ppc-opc.c (CY): New define.  Document it.
	(powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.

gas/
	* testsuite/gas/ppc/altivec3.d <vmsumudm>: Add test.
	* testsuite/gas/ppc/altivec3.s: Likewise.
	* testsuite/gas/ppc/power9.d <addex[.], lwzmx, vmsumudm>: Add tests.
	* testsuite/gas/ppc/power9.s: Likewise.
This commit is contained in:
Peter Bergner 2016-05-26 19:06:51 -05:00
parent 5e0bc41893
commit 19dfcc89e8
7 changed files with 40 additions and 0 deletions
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7
gas/ChangeLog
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@ -1,3 +1,10 @@
2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
* testsuite/gas/ppc/altivec3.d <vmsumudm>: Add test.
* testsuite/gas/ppc/altivec3.s: Likewise.
* testsuite/gas/ppc/power9.d <addex[.], lwzmx, vmsumudm>: Add tests.
* testsuite/gas/ppc/power9.s: Likewise.
2016-05-26 H.J. Lu <hongjiu.lu@intel.com>
* testsuite/gas/i386/avx512vl-2.l: Append "#pass".

1
gas/testsuite/gas/ppc/altivec3.d
View file

@ -76,4 +76,5 @@ Disassembly of section \.text:
.*: (12 b5 17 44|44 17 b5 12) vslv v21,v21,v2
.*: (11 e9 0f 4d|4d 0f e9 11) vextuhrx r15,r9,v1
.*: (12 b1 87 8d|8d 87 b1 12) vextuwrx r21,r17,v16
.*: (12 95 b5 e3|e3 b5 95 12) vmsumudm v20,v21,v22,v23
#pass

1
gas/testsuite/gas/ppc/altivec3.s
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@ -67,3 +67,4 @@ start:
vslv 21,21,2
vextuhrx 15,9,1
vextuwrx 21,17,16
vmsumudm 20,21,22,23

9
gas/testsuite/gas/ppc/power9.d
View file

@ -365,6 +365,8 @@ Disassembly of section \.text:
.*: (7c 00 f6 e4|e4 f6 00 7c) rmieg r30
.*: (7d 40 7a 6a|6a 7a 40 7d) ldmx r10,0,r15
.*: (7d 43 7a 6a|6a 7a 43 7d) ldmx r10,r3,r15
.*: (7d 60 83 6a|6a 83 60 7d) lwzmx r11,0,r16
.*: (7d 63 83 6a|6a 83 63 7d) lwzmx r11,r3,r16
.*: (4c 00 02 e4|e4 02 00 4c) stop
.*: (7c 00 00 3c|3c 00 00 7c) wait
.*: (7c 00 00 3c|3c 00 00 7c) wait
@ -383,4 +385,11 @@ Disassembly of section \.text:
.*: (f0 6d bc 07|07 bc 6d f0) xsmaxcdp vs35,vs45,vs55
.*: (f0 8e c4 c7|c7 c4 8e f0) xsminjdp vs36,vs46,vs56
.*: (f0 af cc 87|87 cc af f0) xsmaxjdp vs37,vs47,vs57
.*: (12 95 b5 e3|e3 b5 95 12) vmsumudm v20,v21,v22,v23
.*: (7d 6c 69 54|54 69 6c 7d) addex r11,r12,r13,0
.*: (7d 6c 6b 54|54 6b 6c 7d) addex r11,r12,r13,1
.*: (7d 6c 6d 54|54 6d 6c 7d) addex r11,r12,r13,2
.*: (7e b6 b9 55|55 b9 b6 7e) addex\. r21,r22,r23,0
.*: (7e b6 bb 55|55 bb b6 7e) addex\. r21,r22,r23,1
.*: (7e b6 bd 55|55 bd b6 7e) addex\. r21,r22,r23,2
#pass

9
gas/testsuite/gas/ppc/power9.s
View file

@ -356,6 +356,8 @@ power9:
rmieg 30
ldmx 10,0,15
ldmx 10,3,15
lwzmx 11,0,16
lwzmx 11,3,16
stop
wait
wait 0
@ -374,3 +376,10 @@ power9:
xsmaxcdp 35,45,55
xsminjdp 36,46,56
xsmaxjdp 37,47,57
vmsumudm 20,21,22,23
addex 11,12,13,0
addex 11,12,13,1
addex 11,12,13,2
addex. 21,22,23,0
addex. 21,22,23,1
addex. 21,22,23,2

5
opcodes/ChangeLog
View file

@ -1,3 +1,8 @@
2016-05-26 Peter Bergner <bergner@vnet.ibm.com>
* ppc-opc.c (CY): New define. Document it.
(powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
2016-05-25 H.J. Lu <hongjiu.lu@intel.com>
* i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,

8
opcodes/ppc-opc.c
View file

@ -815,7 +815,9 @@ const struct powerpc_operand powerpc_operands[] =
#define X_R A_L
{ 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
/* The RMC or CY field in a Z23 form instruction. */
#define RMC A_L + 1
#define CY RMC
{ 0x3, 9, NULL, NULL, 0 },
#define R RMC + 1
@ -3145,6 +3147,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"vmhaddshs", VXA(4, 32), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
{"vmhraddshs", VXA(4, 33), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
{"vmladduhm", VXA(4, 34), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
{"vmsumudm", VXA(4, 35), VXA_MASK, PPCVEC3, PPCNONE, {VD, VA, VB, VC}},
{"ps_div", A (4, 18,0), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
{"vmsumubm", VXA(4, 36), VXA_MASK, PPCVEC|PPCVLE, PPCNONE, {VD, VA, VB, VC}},
{"ps_div.", A (4, 18,1), AFRC_MASK, PPCPS, PPCNONE, {FRT, FRA, FRB}},
@ -4977,6 +4980,9 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"stvehx", X(31,167), X_MASK, PPCVEC, PPCNONE, {VS, RA0, RB}},
{"sthfcmx", APU(31,167,0), APU_MASK, PPC405, PPCNONE, {FCRT, RA, RB}},
{"addex", ZRC(31,170,0), Z2_MASK, POWER9, PPCNONE, {RT, RA, RB, CY}},
{"addex.", ZRC(31,170,1), Z2_MASK, POWER9, PPCNONE, {RT, RA, RB, CY}},
{"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, PPCNONE, {RB}},
{"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
@ -5504,6 +5510,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, PPCNONE, {XT6, RA0, RB}},
{"lwzmx", X(31,437), X_MASK, POWER9, PPCNONE, {RT, RA0, RB}},
{"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
{"sthux", X(31,439), X_MASK, COM|PPCVLE, PPCNONE, {RS, RAS, RB}},