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Ensure zero-hardwired bits in DPSW remain zero.

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This commit is contained in:
Andrew Cagney 1998-02-11 06:34:30 +00:00
parent 14926763d6
commit 19431a0280
3 changed files with 77 additions and 4 deletions
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38
sim/d10v/ChangeLog
View file

@ -1,3 +1,41 @@
Wed Feb 11 16:53:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
* d10v_sim.h (enum): Define DPSW_CR.
* simops.c (move_to_cr): Mask out hardwired zero bits in DPSW.
Tue Feb 10 18:28:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
* interp.c (sim_write_phys): Delete.
(sim_load): Call sim_load_file with sim_write and LMA.
Mon Feb 9 12:05:01 1998 Andrew Cagney <cagney@b1.cygnus.com>
* interp.c: Rewrite xfer_mem so that it translates addresses as -
0x00... - DMAP translated memory, 0x01... IMAP translated memory,
0x10... - on-chip data, 0x11... - on-chip insn, 0x12... - unified
memory.
(pc_addr): Delete.
(imem_addr): New function - translate IMEM address.
(sim_resume): Use imem_addr to translate insn address, abort if
translation failed.
(sim_create_inferior): Write ARGV to memory using sim_write. Pass
argc/argv using r0/r1 not r2/r3.
(sim_size): Do not initialize IMAP/DMAP here.
(sim_open): Call sim_create_inferior and sim_size to initialize
the system.
(sim_create_inferior): Initialize IMAP/DMAP to hardware reset
defaults.
(init_system): Delete.
(xfer_mem, sim_fetch_register, sim_store_register): Do not call
init_system.
(decode_pc): Check prog_bfd is defined before looking up .text
section.
Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.
Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
* configure: Regenerated to track ../common/aclocal.m4 changes.

5
sim/d10v/d10v_sim.h
View file

@ -12,6 +12,7 @@
#define DEBUG_LINE_NUMBER 0x00000004
#define DEBUG_MEMSIZE 0x00000008
#define DEBUG_INSTRUCTION 0x00000010
#define DEBUG_TRAP 0x00000020
#ifndef DEBUG
#define DEBUG (DEBUG_TRACE | DEBUG_VALUES | DEBUG_LINE_NUMBER)
@ -115,6 +116,7 @@ enum
BPSW_CR = 1,
PC_CR = 2,
BPC_CR = 3,
DPSW_CR = 4,
RPT_C_CR = 7,
RPT_S_CR = 8,
RPT_E_CR = 9,
@ -143,7 +145,7 @@ enum
or assigned-to directly */
#define PC (State.cregs[PC_CR])
#define PSW (move_from_cr (PSW_CR))
#define BPSW (0 + State.cregs[PSW_CR])
#define BPSW (0 + State.cregs[BPSW_CR])
#define BPC (State.cregs[BPC_CR])
#define RPT_C (State.cregs[RPT_C_CR])
#define RPT_S (State.cregs[RPT_S_CR])
@ -190,6 +192,7 @@ enum
#define INC_ADDR(x,i) x = ((State.MD && x == (MOD_E & ~((i)-1))) ? MOD_S : (x)+(i))
extern uint8 *dmem_addr PARAMS ((uint32));
extern uint8 *imem_addr PARAMS ((uint32));
extern bfd_vma decode_pc PARAMS ((void));
#define RB(x) (*(dmem_addr(x)))

38
sim/d10v/simops.c
View file

@ -70,10 +70,11 @@ move_to_cr (int cr, reg_t val)
PC<<2);
State.exception = SIGILL;
}
State.cregs[PSW_CR] = (val & ~0x4032);
State.cregs[cr] = (val & ~0x4032);
break;
case BPSW_CR:
State.cregs[BPSW_CR] = (val & ~0x4032);
case DPSW_CR:
State.cregs[cr] = (val & ~0x4032);
break;
case MOD_S_CR:
case MOD_E_CR:
@ -2651,14 +2652,45 @@ OP_5F00 ()
switch (OP[0])
{
default:
#if (DEBUG & DEBUG_TRAP) == 0
{
uint16 vec = OP[0] + TRAP_VECTOR_START;
BPC = PC + 1;
move_to_cr (BPSW_CR, PSW);
move_to_cr (PSW_CR, PSW & PSW_SM_BIT);
JMP (vec);
}
break;
}
#else /* if debugging use trap to print registers */
{
int i;
static int first_time = 1;
if (first_time)
{
first_time = 0;
(*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
for (i = 0; i < 16; i++)
(*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
(*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
}
(*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
for (i = 0; i < 16; i++)
(*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) State.regs[i]);
for (i = 0; i < 2; i++)
(*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
((int)(State.a[i] >> 32) & 0xff),
((unsigned long)State.a[i]) & 0xffffffff);
(*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
State.F0 != 0, State.F1 != 0, State.C != 0);
(*d10v_callback->flush_stdout) (d10v_callback);
break;
}
#endif
case 15: /* new system call trap */
/* Trap 15 is used for simulating low-level I/O */
{