Ensure zero-hardwired bits in DPSW remain zero.
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14926763d6
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19431a0280
3 changed files with 77 additions and 4 deletions
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@ -1,3 +1,41 @@
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Wed Feb 11 16:53:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* d10v_sim.h (enum): Define DPSW_CR.
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* simops.c (move_to_cr): Mask out hardwired zero bits in DPSW.
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Tue Feb 10 18:28:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* interp.c (sim_write_phys): Delete.
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(sim_load): Call sim_load_file with sim_write and LMA.
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Mon Feb 9 12:05:01 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* interp.c: Rewrite xfer_mem so that it translates addresses as -
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0x00... - DMAP translated memory, 0x01... IMAP translated memory,
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0x10... - on-chip data, 0x11... - on-chip insn, 0x12... - unified
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memory.
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(pc_addr): Delete.
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(imem_addr): New function - translate IMEM address.
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(sim_resume): Use imem_addr to translate insn address, abort if
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translation failed.
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(sim_create_inferior): Write ARGV to memory using sim_write. Pass
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argc/argv using r0/r1 not r2/r3.
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(sim_size): Do not initialize IMAP/DMAP here.
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(sim_open): Call sim_create_inferior and sim_size to initialize
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the system.
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(sim_create_inferior): Initialize IMAP/DMAP to hardware reset
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defaults.
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(init_system): Delete.
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(xfer_mem, sim_fetch_register, sim_store_register): Do not call
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init_system.
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(decode_pc): Check prog_bfd is defined before looking up .text
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section.
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Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* configure: Regenerated to track ../common/aclocal.m4 changes.
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Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* configure: Regenerated to track ../common/aclocal.m4 changes.
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@ -12,6 +12,7 @@
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#define DEBUG_LINE_NUMBER 0x00000004
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#define DEBUG_MEMSIZE 0x00000008
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#define DEBUG_INSTRUCTION 0x00000010
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#define DEBUG_TRAP 0x00000020
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#ifndef DEBUG
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#define DEBUG (DEBUG_TRACE | DEBUG_VALUES | DEBUG_LINE_NUMBER)
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@ -115,6 +116,7 @@ enum
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BPSW_CR = 1,
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PC_CR = 2,
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BPC_CR = 3,
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DPSW_CR = 4,
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RPT_C_CR = 7,
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RPT_S_CR = 8,
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RPT_E_CR = 9,
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@ -143,7 +145,7 @@ enum
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or assigned-to directly */
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#define PC (State.cregs[PC_CR])
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#define PSW (move_from_cr (PSW_CR))
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#define BPSW (0 + State.cregs[PSW_CR])
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#define BPSW (0 + State.cregs[BPSW_CR])
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#define BPC (State.cregs[BPC_CR])
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#define RPT_C (State.cregs[RPT_C_CR])
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#define RPT_S (State.cregs[RPT_S_CR])
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@ -190,6 +192,7 @@ enum
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#define INC_ADDR(x,i) x = ((State.MD && x == (MOD_E & ~((i)-1))) ? MOD_S : (x)+(i))
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extern uint8 *dmem_addr PARAMS ((uint32));
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extern uint8 *imem_addr PARAMS ((uint32));
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extern bfd_vma decode_pc PARAMS ((void));
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#define RB(x) (*(dmem_addr(x)))
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@ -70,10 +70,11 @@ move_to_cr (int cr, reg_t val)
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PC<<2);
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State.exception = SIGILL;
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}
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State.cregs[PSW_CR] = (val & ~0x4032);
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State.cregs[cr] = (val & ~0x4032);
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break;
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case BPSW_CR:
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State.cregs[BPSW_CR] = (val & ~0x4032);
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case DPSW_CR:
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State.cregs[cr] = (val & ~0x4032);
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break;
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case MOD_S_CR:
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case MOD_E_CR:
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@ -2651,14 +2652,45 @@ OP_5F00 ()
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switch (OP[0])
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{
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default:
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#if (DEBUG & DEBUG_TRAP) == 0
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{
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uint16 vec = OP[0] + TRAP_VECTOR_START;
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BPC = PC + 1;
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move_to_cr (BPSW_CR, PSW);
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move_to_cr (PSW_CR, PSW & PSW_SM_BIT);
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JMP (vec);
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break;
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}
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break;
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#else /* if debugging use trap to print registers */
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{
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int i;
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static int first_time = 1;
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if (first_time)
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{
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first_time = 0;
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(*d10v_callback->printf_filtered) (d10v_callback, "Trap # PC ");
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for (i = 0; i < 16; i++)
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(*d10v_callback->printf_filtered) (d10v_callback, " %sr%d", (i > 9) ? "" : " ", i);
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(*d10v_callback->printf_filtered) (d10v_callback, " a0 a1 f0 f1 c\n");
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}
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(*d10v_callback->printf_filtered) (d10v_callback, "Trap %2d 0x%.4x:", (int)OP[0], (int)PC);
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for (i = 0; i < 16; i++)
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(*d10v_callback->printf_filtered) (d10v_callback, " %.4x", (int) State.regs[i]);
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for (i = 0; i < 2; i++)
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(*d10v_callback->printf_filtered) (d10v_callback, " %.2x%.8lx",
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((int)(State.a[i] >> 32) & 0xff),
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((unsigned long)State.a[i]) & 0xffffffff);
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(*d10v_callback->printf_filtered) (d10v_callback, " %d %d %d\n",
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State.F0 != 0, State.F1 != 0, State.C != 0);
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(*d10v_callback->flush_stdout) (d10v_callback);
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break;
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}
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#endif
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case 15: /* new system call trap */
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/* Trap 15 is used for simulating low-level I/O */
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{
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