gas/
2008-02-18 Jan Beulich <jbeulich@novell.com> * config/tc-i386.c (match_template): Disallow 'l' suffix when currently selected CPU has no 32-bit support. (parse_real_register): Do not return registers not available on currently selected CPU. gas/testsuite/ 2008-02-18 Jan Beulich <jbeulich@novell.com> * gas/i386/att-regs.s, gas/i386/att-regs.d, gas/i386/intel-regs.s, gas/i386/intel-regs.d: New. * gas/i386/i386.exp: Run new tests.
This commit is contained in:
Jan Beulich
parent
fca143f2c4
commit
192dc9c6fd
8 changed files with 232 additions and 0 deletions
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@ -1,3 +1,10 @@
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2008-02-18 Jan Beulich <jbeulich@novell.com>
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* config/tc-i386.c (match_template): Disallow 'l' suffix when
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currently selected CPU has no 32-bit support.
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(parse_real_register): Do not return registers not available on
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currently selected CPU.
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2008-02-16 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (process_immext): Fix format.
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@ -3337,6 +3337,19 @@ match_template (void)
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|| t->extension_opcode != 1 /* cmpxchg8b */))
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continue;
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/* In general, don't allow 32-bit operands on pre-386. */
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else if (i.suffix == LONG_MNEM_SUFFIX
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&& !cpu_arch_flags.bitfield.cpui386
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&& (intel_syntax
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? (!t->opcode_modifier.ignoresize
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&& !intel_float_operand (t->name))
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: intel_float_operand (t->name) != 2)
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&& ((!operand_types[0].bitfield.regmmx
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&& !operand_types[0].bitfield.regxmm)
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|| (!operand_types[t->operands > 1].bitfield.regmmx
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&& !!operand_types[t->operands > 1].bitfield.regxmm)))
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continue;
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/* Do not verify operands when there are none. */
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else
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{
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@ -7114,6 +7127,20 @@ parse_real_register (char *reg_string, char **end_op)
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if (operand_type_all_zero (&r->reg_type))
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return (const reg_entry *) NULL;
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if ((r->reg_type.bitfield.reg32
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|| r->reg_type.bitfield.sreg3
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|| r->reg_type.bitfield.control
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|| r->reg_type.bitfield.debug
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|| r->reg_type.bitfield.test)
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&& !cpu_arch_flags.bitfield.cpui386)
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return (const reg_entry *) NULL;
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if (r->reg_type.bitfield.regmmx && !cpu_arch_flags.bitfield.cpummx)
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return (const reg_entry *) NULL;
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if (r->reg_type.bitfield.regxmm && !cpu_arch_flags.bitfield.cpusse)
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return (const reg_entry *) NULL;
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/* Don't allow fake index register unless allow_index_reg isn't 0. */
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if (!allow_index_reg
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&& (r->reg_num == RegEiz || r->reg_num == RegRiz))
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@ -1,3 +1,9 @@
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2008-02-18 Jan Beulich <jbeulich@novell.com>
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* gas/i386/att-regs.s, gas/i386/att-regs.d,
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gas/i386/intel-regs.s, gas/i386/intel-regs.d: New.
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* gas/i386/i386.exp: Run new tests.
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2008-02-14 Nick Clifton <nickc@redhat.com>
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PR gas/5712
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45
gas/testsuite/gas/i386/att-regs.d
Normal file
45
gas/testsuite/gas/i386/att-regs.d
Normal file
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@ -0,0 +1,45 @@
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#objdump: -drw
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#name: i386 AT&T register names
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.*: +file format .*i386.*
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Disassembly of section \.text:
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0+0 <.*>:
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.*[ ]+R_386_16[ ]+eax
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.*[ ]+R_386_16[ ]+rax
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.*[ ]+R_386_16[ ]+axl
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.*[ ]+R_386_16[ ]+r8b
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.*[ ]+R_386_16[ ]+r8w
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.*[ ]+R_386_16[ ]+r8d
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.*[ ]+R_386_16[ ]+r8
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.*[ ]+R_386_16[ ]+fs
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#.*[ ]+R_386_16[ ]+st
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.*[ ]+R_386_16[ ]+cr0
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.*[ ]+R_386_16[ ]+dr0
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.*[ ]+R_386_16[ ]+tr0
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.*[ ]+R_386_16[ ]+mm0
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.*[ ]+R_386_16[ ]+xmm0
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.*[ ]+R_386_32[ ]+rax
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.*[ ]+R_386_32[ ]+axl
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.*[ ]+R_386_32[ ]+r8b
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.*[ ]+R_386_32[ ]+r8w
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.*[ ]+R_386_32[ ]+r8d
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.*[ ]+R_386_32[ ]+r8
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#.*[ ]+R_386_32[ ]+st
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.*:[ ]+0f 20 c0[ ]+mov[ ]+%cr0,%eax
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.*:[ ]+0f 21 c0[ ]+mov[ ]+%db0,%eax
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.*:[ ]+0f 24 c0[ ]+mov[ ]+%tr0,%eax
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.*[ ]+R_386_32[ ]+mm0
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.*[ ]+R_386_32[ ]+xmm0
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.*:[ ]+dd c0[ ]+ffree[ ]+%st(\(0\))?
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.*:[ ]+0f ef c0[ ]+pxor[ ]+%mm0,%mm0
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.*:[ ]+0f 57 c0[ ]+xorps[ ]+%xmm0,%xmm0
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.*:[ ]+44[ ]+inc %esp
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.*:[ ]+88 c0[ ]+mov[ ]+%al,%al
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.*:[ ]+66 44[ ]+inc[ ]+%sp
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.*:[ ]+89 c0[ ]+mov[ ]+%eax,%eax
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.*:[ ]+44[ ]+inc %esp
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.*:[ ]+89 c0[ ]+mov[ ]+%eax,%eax
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.*:[ ]+4c[ ]+dec %esp
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.*:[ ]+89 c0[ ]+mov[ ]+%eax,%eax
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#pass
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50
gas/testsuite/gas/i386/att-regs.s
Normal file
50
gas/testsuite/gas/i386/att-regs.s
Normal file
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@ -0,0 +1,50 @@
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.text
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.att_syntax noprefix
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.arch i286
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.code16
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mov eax, ax ; add al, (bx,si)
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mov rax, ax ; add al, (bx,si)
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mov axl, ax ; add al, (bx,si)
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mov r8b, ax ; add al, (bx,si)
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mov r8w, ax ; add al, (bx,si)
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mov r8d, ax ; add al, (bx,si)
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mov r8, ax ; add al, (bx,si)
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mov fs, ax ; add al, (bx,si)
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#todo mov st, ax ; add al, (bx,si)
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mov cr0, ax ; add al, (bx,si)
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mov dr0, ax ; add al, (bx,si)
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mov tr0, ax ; add al, (bx,si)
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mov mm0, ax ; add al, (bx,si)
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mov xmm0, ax ; add al, (bx,si)
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.arch generic32
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.code32
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mov rax, eax
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mov axl, eax
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mov r8b, eax
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mov r8w, eax
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mov r8d, eax
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mov r8, eax
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#todo mov st, eax
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mov cr0, eax
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mov dr0, eax
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mov tr0, eax
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mov mm0, eax
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mov xmm0, eax
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#todo .arch i387
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ffree st
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.arch .mmx
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pxor mm0, mm0
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.arch .sse
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xorps xmm0, xmm0
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.arch generic64
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.code64
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mov r8b, axl
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mov r8w, ax
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mov r8d, eax
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mov r8, rax
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@ -146,6 +146,8 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "reloc32"
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run_list_test "reloc32" "--defsym _bad_=1"
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run_dump_test "mixed-mode-reloc32"
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run_dump_test "att-regs"
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run_dump_test "intel-regs"
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}
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# This is a PE specific test.
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45
gas/testsuite/gas/i386/intel-regs.d
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45
gas/testsuite/gas/i386/intel-regs.d
Normal file
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@ -0,0 +1,45 @@
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#objdump: -drw
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#name: i386 Intel register names
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.*: +file format .*i386.*
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Disassembly of section \.text:
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0+0 <.*>:
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.*[ ]+R_386_16[ ]+eax
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.*[ ]+R_386_16[ ]+rax
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.*[ ]+R_386_16[ ]+axl
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.*[ ]+R_386_16[ ]+r8b
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.*[ ]+R_386_16[ ]+r8w
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.*[ ]+R_386_16[ ]+r8d
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.*[ ]+R_386_16[ ]+r8
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.*[ ]+R_386_16[ ]+fs
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#.*[ ]+R_386_16[ ]+st
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.*[ ]+R_386_16[ ]+cr0
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.*[ ]+R_386_16[ ]+dr0
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.*[ ]+R_386_16[ ]+tr0
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.*[ ]+R_386_16[ ]+mm0
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.*[ ]+R_386_16[ ]+xmm0
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.*[ ]+R_386_32[ ]+rax
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.*[ ]+R_386_32[ ]+axl
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.*[ ]+R_386_32[ ]+r8b
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.*[ ]+R_386_32[ ]+r8w
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.*[ ]+R_386_32[ ]+r8d
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.*[ ]+R_386_32[ ]+r8
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#.*[ ]+R_386_32[ ]+st
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.*:[ ]+0f 20 c0[ ]+mov[ ]+%cr0,%eax
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.*:[ ]+0f 21 c0[ ]+mov[ ]+%db0,%eax
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.*:[ ]+0f 24 c0[ ]+mov[ ]+%tr0,%eax
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.*[ ]+R_386_32[ ]+mm0
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.*[ ]+R_386_32[ ]+xmm0
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.*:[ ]+dd c0[ ]+ffree[ ]+%st(\(0\))?
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.*:[ ]+0f ef c0[ ]+pxor[ ]+%mm0,%mm0
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.*:[ ]+0f 57 c0[ ]+xorps[ ]+%xmm0,%xmm0
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.*:[ ]+44[ ]+inc %esp
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.*:[ ]+88 c0[ ]+mov[ ]+%al,%al
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.*:[ ]+66 44[ ]+inc[ ]+%sp
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.*:[ ]+89 c0[ ]+mov[ ]+%eax,%eax
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.*:[ ]+44[ ]+inc %esp
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.*:[ ]+89 c0[ ]+mov[ ]+%eax,%eax
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.*:[ ]+4c[ ]+dec %esp
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.*:[ ]+89 c0[ ]+mov[ ]+%eax,%eax
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#pass
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50
gas/testsuite/gas/i386/intel-regs.s
Normal file
50
gas/testsuite/gas/i386/intel-regs.s
Normal file
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@ -0,0 +1,50 @@
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.text
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.intel_syntax noprefix
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.arch i286
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.code16
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mov ax, eax ; add [bx+si], al
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mov ax, rax ; add [bx+si], al
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mov ax, axl ; add [bx+si], al
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mov ax, r8b ; add [bx+si], al
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mov ax, r8w ; add [bx+si], al
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mov ax, r8d ; add [bx+si], al
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mov ax, r8 ; add [bx+si], al
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mov ax, fs ; add [bx+si], al
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#todo mov ax, st ; add [bx+si], al
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mov ax, cr0 ; add [bx+si], al
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mov ax, dr0 ; add [bx+si], al
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mov ax, tr0 ; add [bx+si], al
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mov ax, mm0 ; add [bx+si], al
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mov ax, xmm0 ; add [bx+si], al
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.arch generic32
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.code32
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mov eax, rax
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mov eax, axl
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mov eax, r8b
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mov eax, r8w
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mov eax, r8d
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mov eax, r8
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#todo mov eax, st
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mov eax, cr0
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mov eax, dr0
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mov eax, tr0
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mov eax, mm0
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mov eax, xmm0
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#todo .arch i387
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ffree st
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.arch .mmx
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pxor mm0, mm0
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.arch .sse
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xorps xmm0, xmm0
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.arch generic64
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.code64
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mov axl, r8b
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mov ax, r8w
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mov eax, r8d
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mov rax, r8
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