* rs6k.h: Remove obsolete file.
This commit is contained in:
Ian Lance Taylor
parent
55745b34b0
commit
180b9a3805
3 changed files with 4 additions and 255 deletions
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@ -49,7 +49,6 @@ ns32k.h
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pn.h
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ppc.h
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pyr.h
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rs6k.h
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sparc.h
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tahoe.h
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vax.h
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@ -1,3 +1,7 @@
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Thu Jun 20 15:02:57 1996 Ian Lance Taylor <ian@cygnus.com>
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* rs6k.h: Remove obsolete file.
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Wed Jun 19 15:29:38 1996 Ian Lance Taylor <ian@cygnus.com>
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* i386.h: Correct opcode values for faddp, fsubp, fsubrp, fmulp,
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@ -1,254 +0,0 @@
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/* IBM RS/6000 instruction set definitions, for GNU software. */
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/* These are all possible instruction formats as used in IBM Assembler
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Language Reference, Appendix A. */
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typedef enum { A=0, B, D, I, M, SC, X, XL, XO, XFL, XFX } InsnFmt;
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/* Extended opcode masks. Used for extracting extended opcode values from
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instructions. Each instruction's format decides which mask applies.
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They *should* retain the same order as the above formats. */
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static int eopMask[] =
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{ 0x1f, 0, 0, 0, 0, 0, 0x3ff, 0x3ff, 0x1ff, 0x3ff, 0x3ff };
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/* All the things you need to know about an opcode. */
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typedef struct rs6000_insn {
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char *operator; /* opcode name */
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char *opr_ext; /* opcode name extension */
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InsnFmt format; /* opcode format */
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char p_opcode; /* primary opcode */
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int e_opcode; /* extended opcode */
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char oprnd_format[6]; /* operand format */
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} OPCODE;
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/* operand format specifiers */
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#define TO 1
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#define RA 2
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#define SI 3
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#define RT 4
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#define UI 5
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#define BF 6
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#define BFA 7
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#define BT 8
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#define BA 9
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#define BB 10
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#define BO 11
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#define BI 12
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#define RB 13
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#define RS 14
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#define SH 15
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#define MB 16
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#define ME 17
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#define SPR 18
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#define DIS 19
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#define FXM 21
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#define FRT 22
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#define NB 23
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#define FRS 24
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#define FRA 25
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#define FRB 26
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#define FRC 27
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#define FLM 28
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#define I 29
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#define LI 30
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#define A2 31
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#define TA14 32 /* 14 bit representation of target address */
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#define TA24 33 /* 24 bit representation of target address */
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#define FL1 34
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#define FL2 35
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#define LEV 36
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/* RS/6000 INSTRUCTION SET
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(sorted on primary and extended opcode)
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oprtr primary ext.
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operator ext format opcode opcode operand format
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------- ------- ------ ------- ------ --------------- */
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struct rs6000_insn rs6k_ops [] = {
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{"ti", 0, D, 3, -1, {TO,RA,SI,0} },
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{"muli", 0, D, 7, -1, {RT,RA,SI,0} },
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{"sfi", 0, D, 8, -1, {RT,RA,SI,0} },
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{"dozi", 0, D, 9, -1, {RT,RA,SI,0} },
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{"cmpli", 0, D, 10, -1, {BF,RA,UI,0} },
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{"cmpi", 0, D, 11, -1, {BF,RA,SI,0} },
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{"ai", 0, D, 12, -1, {RT,RA,SI,0} },
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{"ai.", 0, D, 13, -1, {RT,RA,SI,0} },
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{"lil", 0, D, 14, -1, {RT,SI,0} }, /* same as `cal' */
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{"cal", 0, D, 14, -1, {RT,DIS,RA,0} },
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{"liu", 0, D, 15, -1, {RT, UI,0} }, /* same as `cau' */
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{"cau", 0, D, 15, -1, {RT,RA,UI,0} },
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/* "1" indicates an exception--"bb" is only usable for some values of
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BO, so the disassembler first matches this instruction and then changes
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it to "bc" if that is the case. */
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{"bb", "1tfla", B, 16, -1, {LI,A2,0} },
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{"bc", "la", B, 16, -1, {BO,BI,TA14,0} },
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{"svc", "la", SC, 17, -1, {LEV,FL1,FL2,0} },
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{"b", "la", I, 18, -1, {TA24,0} },
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{"mcrf", 0, XL, 19, 0, {BF,BFA,0} },
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{"bcr", "l", XL, 19, 16, {BO,BI,0} },
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{"crnor", 0, XL, 19, 33, {BT,BA,BB,0} },
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{"rfi", 0, X, 19, 50, {0} },
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{"rfsvc", 0, X, 19, 82, {0} },
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{"crandc", 0, XL, 19, 129, {BT,BA,BB,0} },
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{"ics", 0, X, 19, 150, {0} },
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{"crxor", 0, XL, 19, 193, {BT,BA,BB,0} },
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{"crnand", 0, XL, 19, 225, {BT,BA,BB,0} },
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{"crand", 0, XL, 19, 257, {BT,BA,BB,0} },
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{"creqv", 0, XL, 19, 289, {BT,BA,BB,0} },
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{"crorc", 0, XL, 19, 417, {BT,BA,BB,0} },
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{"cror", 0, XL, 19, 449, {BT,BA,BB,0} },
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{"bcc", "l", XL, 19, 528, {BO,BI,0} },
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{"rlimi", ".", M, 20, -1, {RA,RS,SH,MB,ME,0} /*??*/},
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{"rlinm", ".", M, 21, -1, {RA,RS,SH,MB,ME,0} /*??*/},
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{"rlmi", ".", M, 22, -1, {RA,RS,RB,MB,ME,0} /*??*/},
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{"rlnm", ".", M, 23, -1, {RA,RS,RB,MB,ME,0} /*??*/},
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{"oril", 0, D, 24, -1, {RA,RS,UI,0} },
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{"oriu", 0, D, 25, -1, {RA,RS,UI,0} },
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{"xoril", 0, D, 26, -1, {RA,RS,UI,0} },
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{"xoriu", 0, D, 27, -1, {RA,RS,UI,0} },
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{"andil.", 0, D, 28, -1, {RA,RS,UI,0} },
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{"andiu.", 0, D, 29, -1, {RA,RS,UI,0} },
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{"cmp", 0, X, 31, 0, {BF,RA,RB,0} },
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{"t", 0, X, 31, 4, {TO,RA,RB,0} },
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{"sf", "o.", XO, 31, 8, {RT,RA,RB,0} },
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{"a", "o.", XO, 31, 10, {RT,RA,RB,0} },
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{"mfcr", 0, X, 31, 19, {RT,0} },
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{"lx", 0, X, 31, 23, {RT,RA,RB,0} },
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{"sl", ".", X, 31, 24, {RA,RS,RB,0} },
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{"cntlz", ".", XO, 31, 26, {RA,RS,0} },
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{"and", ".", X, 31, 28, {RA,RS,RB,0} },
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{"maskg", ".", X, 31, 29, {RA,RS,RB,0} },
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{"cmpl", 0, X, 31, 32, {BF,RA,RB,0} },
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{"sfe", "o.", XO, 31, 136, {RT,RA,RB,0} },
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{"lux", 0, X, 31, 55, {RT,RA,RB,0} },
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{"andc", ".", X, 31, 60, {RA,RS,RB,0} },
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{"mfmsr", 0, X, 31, 83, {RT,0} },
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{"lbzx", 0, X, 31, 87, {RT,RA,RB,0} },
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{"neg", "o.", XO, 31, 104, {RT,RA,0} },
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{"mul", "o.", XO, 31, 107, {RT,RA,RB,0} },
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{"lbzux", 0, X, 31, 119, {RT,RA,RB,0} },
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{"nor", ".", X, 31, 124, {RA,RS,RB,0} },
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{"ae", "o.", XO, 31, 138, {RT,RA,RB,0} },
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{"mtcrf", 0, XFX, 31, 144, {FXM,RS,0} },
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{"stx", 0, X, 31, 151, {RS,RA,RB,0} },
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{"slq", ".", X, 31, 152, {RA,RS,RB,0} },
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{"sle", ".", X, 31, 153, {RA,RS,RB,0} },
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{"stux", 0, X, 31, 183, {RS,RA,RB,0} },
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{"sliq", ".", X, 31, 184, {RA,RS,SH,0} },
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{"sfze", "o.", XO, 31, 200, {RT,RA,0} },
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{"aze", "o.", XO, 31, 202, {RT,RA,0} },
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{"stbx", 0, X, 31, 215, {RS,RA,RB,0} },
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{"sllq", ".", X, 31, 216, {RA,RS,RB,0} },
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{"sleq", ".", X, 31, 217, {RA,RS,RB,0} },
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{"sfme", "o.", XO, 31, 232, {RT,RA,0} },
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{"ame", "o.", XO, 31, 234, {RT,RA,0} },
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{"muls", "o.", XO, 31, 235, {RT,RA,RB,0} },
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{"stbux", 0, X, 31, 247, {RS,RA,RB,0} },
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{"slliq", ".", X, 31, 248, {RA,RS,SH,0} },
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{"doz", "o.", X, 31, 264, {RT,RA,RB,0} },
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{"cax", "o.", XO, 31, 266, {RT,RA,RB,0} },
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{"lscbx", ".", X, 31, 277, {RT,RA,RB,0} },
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{"lhzx", 0, X, 31, 279, {RT,RA,RB,0} },
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{"eqv", ".", X, 31, 284, {RA,RS,RB,0} },
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{"lhzux", 0, X, 31, 311, {RT,RA,RB,0} },
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{"xor", ".", X, 31, 316, {RA,RS,RB,0} },
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{"div", "o.", XO, 31, 331, {RT,RA,RB,0} },
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{"mfspr", 0, X, 31, 339, {RT,SPR,0} },
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{"lhax", 0, X, 31, 343, {RT,RA,RB,0} },
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{"abs", "o.", XO, 31, 360, {RT,RA,0} },
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{"divs", "o.", XO, 31, 363, {RT,RA,RB,0} },
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{"lhaux", 0, X, 31, 375, {RT,RA,RB,0} },
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{"sthx", 0, X, 31, 407, {RS,RA,RB,0} },
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{"orc", ".", X, 31, 412, {RA,RS,RB,0} },
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{"sthux", 0, X, 31, 439, {RS,RA,RB,0} },
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{"or", ".", X, 31, 444, {RA,RS,RB,0} },
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{"mtspr", 0, X, 31, 467, {SPR,RS,0} },
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{"nand", ".", X, 31, 476, {RA,RS,RB,0} },
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{"nabs", "o.", XO, 31, 488, {RT,RA,0} },
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{"mcrxr", 0, X, 31, 512, {BF,0} },
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{"lsx", 0, X, 31, 533, {RT,RA,RB,0} },
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{"lbrx", 0, X, 31, 534, {RT,RA,RB,0} },
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{"lfsx", 0, X, 31, 535, {FRT,RA,RB,0} },
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{"sr", ".", X, 31, 536, {RA,RS,RB,0} },
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{"rrib", ".", X, 31, 537, {RA,RS,RB,0} },
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{"maskir", ".", X, 31, 541, {RA,RS,RB,0} },
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{"lfsux", 0, X, 31, 567, {FRT,RA,RB,0} },
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{"lsi", 0, X, 31, 597, {RT,RA,NB,0} },
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{"lfdx", 0, X, 31, 599, {FRT,RA,RB,0} },
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{"lfdux", 0, X, 31, 631, {FRT,RA,RB,0} },
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{"stsx", 0, X, 31, 661, {RS,RA,RB,0} },
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{"stbrx", 0, X, 31, 662, {RS,RA,RB,0} },
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{"stfsx", 0, X, 31, 663, {FRS,RA,RB,0} },
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{"srq", ".", X, 31, 664, {RA,RS,RB,0} },
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{"sre", ".", X, 31, 665, {RA,RS,RB,0} },
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{"stfsux", 0, X, 31, 695, {FRS,RA,RB,0} },
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{"sriq", ".", X, 31, 696, {RA,RS,SH,0} },
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{"stsi", 0, X, 31, 725, {RS,RA,NB,0} },
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{"stfdx", 0, X, 31, 727, {FRS,RA,RB,0} },
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{"srlq", ".", X, 31, 728, {RA,RS,RB,0} },
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{"sreq", ".", X, 31, 729, {RA,RS,RB,0} },
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{"stfdux", 0, X, 31, 759, {FRS,RA,RB,0} },
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{"srliq", ".", X, 31, 760, {RA,RS,SH,0} },
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{"lhbrx", 0, X, 31, 790, {RT,RA,RB,0} },
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{"sra", ".", X, 31, 792, {RA,RS,RB,0} },
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{"srai", ".", X, 31, 824, {RA,RS,SH,0} },
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{"sthbrx", 0, X, 31, 918, {RS,RA,RB,0} },
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{"sraq", ".", X, 31, 920, {RA,RS,RB,0} },
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{"srea", ".", X, 31, 921, {RA,RS,RB,0} },
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{"exts", ".", X, 31, 922, {RA,RS,0} },
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{"sraiq", ".", X, 31, 952, {RA,RS,SH,0} },
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{"l", 0, D, 32, -1, {RT,DIS,RA,0} },
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{"lu", 0, D, 33, -1, {RT,DIS,RA,0} },
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{"lbz", 0, D, 34, -1, {RT,DIS,RA,0} },
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{"lbzu", 0, D, 35, -1, {RT,DIS,RA,0} },
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{"st", 0, D, 36, -1, {RS,DIS,RA,0} },
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{"stu", 0, D, 37, -1, {RS,DIS,RA,0} },
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{"stb", 0, D, 38, -1, {RS,DIS,RA,0} },
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{"stbu", 0, D, 39, -1, {RS,DIS,RA,0} },
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{"lhz", 0, D, 40, -1, {RT,DIS,RA,0} },
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{"lhzu", 0, D, 41, -1, {RT,DIS,RA,0} },
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{"lha", 0, D, 42, -1, {RT,DIS,RA,0} },
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{"lhau", 0, D, 43, -1, {RT,DIS,RA,0} },
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{"sth", 0, D, 44, -1, {RS,DIS,RA,0} },
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{"sthu", 0, D, 45, -1, {RS,DIS,RA,0} },
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{"lm", 0, D, 46, -1, {RT,DIS,RA,0} },
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{"stm", 0, D, 47, -1, {RS,DIS,RA,0} },
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{"lfs", 0, D, 48, -1, {FRT,DIS,RA,0} },
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{"lfsu", 0, D, 49, -1, {FRT,DIS,RA,0} },
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{"lfd", 0, D, 50, -1, {FRT,DIS,RA,0} },
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{"lfdu", 0, D, 51, -1, {FRT,DIS,RA,0} },
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{"stfs", 0, D, 52, -1, {FRS,DIS,RA,0} },
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{"stfsu", 0, D, 53, -1, {FRS,DIS,RA,0} },
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{"stfd", 0, D, 54, -1, {FRS,DIS,RA,0} },
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{"stfdu", 0, D, 55, -1, {FRS,DIS,RA,0} },
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{"fcmpu", 0, X, 63, 0, {BF,FRA,FRB,0} },
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{"frsp", ".", X, 63, 12, {FRT,FRB,0} },
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{"fd", ".", A, 63, 18, {FRT,FRA,FRB,0} },
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{"fs", ".", A, 63, 20, {FRT,FRA,FRB,0} },
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{"fa", ".", A, 63, 21, {FRT,FRA,FRB,0} },
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{"fm", ".", A, 63, 25, {FRT,FRA,FRC,0} },
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{"fms", ".", A, 63, 28, {FRT,FRA,FRC,FRB,0} },
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{"fma", ".", A, 63, 29, {FRT,FRA,FRC,FRB,0} },
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{"fnms", ".", A, 63, 30, {FRT,FRA,FRC,FRB,0} },
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{"fnma", ".", A, 63, 31, {FRT,FRA,FRC,FRB,0} },
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{"fcmpo", 0, X, 63, 32, {BF,FRA,FRB,0} },
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{"mtfsb1", ".", X, 63, 38, {BT,0} },
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{"fneg", ".", X, 63, 40, {FRT,FRB,0} },
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{"mcrfs", 0, X, 63, 64, {BF,BFA,0} },
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{"mtfsb0", ".", X, 63, 70, {BT,0} },
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{"fmr", ".", X, 63, 72, {FRT,FRB,0} },
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{"mtfsfi", ".", X, 63, 134, {BF,I,0} },
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{"fnabs", ".", X, 63, 136, {FRT,FRB,0} },
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{"fabs", ".", X, 63, 264, {FRT,FRB,0} },
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{"mffs", ".", X, 63, 583, {FRT,0} },
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{"mtfsf", ".", XFL, 63, 711, {FLM,FRB,0} },
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};
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#define NOPCODES (sizeof (rs6k_ops) / sizeof (struct rs6000_insn))
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