* config/sh/tm-sh.h (REGISTER_NAMES): Move fp registers to
be consistent with GCC. (FPUL_REGNUM, etc): Renumber to match list changes. (ADDR_BITS_REMOVE): Delete. * sh-tdep.c (sh_reg_names, sh3_reg_names, sh3e_reg_names): Rearrange to match REGISTER_NAMES. * sh3-rom.c (sh3_regnames, sh3e_regnames): Ditto. PR 9457
This commit is contained in:
Stan Shebs
parent
c58a1ec2aa
commit
12ffa10c1d
4 changed files with 74 additions and 64 deletions
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@ -1,3 +1,13 @@
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Fri Sep 20 16:10:58 1996 Stan Shebs <shebs@andros.cygnus.com>
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* config/sh/tm-sh.h (REGISTER_NAMES): Move fp registers to
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be consistent with GCC.
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(FPUL_REGNUM, etc): Renumber to match list changes.
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(ADDR_BITS_REMOVE): Delete.
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* sh-tdep.c (sh_reg_names, sh3_reg_names, sh3e_reg_names):
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Rearrange to match REGISTER_NAMES.
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* sh3-rom.c (sh3_regnames, sh3e_regnames): Ditto.
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start-sanitize-d10v
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Thu Sep 19 16:19:01 1996 Martin M. Hunt <hunt@pizza.cygnus.com>
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@ -109,25 +109,25 @@ extern CORE_ADDR sh_skip_prologue ();
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Entries beyond the first NUM_REGS are ignored. */
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#define REGISTER_NAMES \
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{"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
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"r8", "r9", "r10","r11","r12", "r13", "r14","r15",\
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"pc", "pr", "gbr","vbr","mach","macl","sr", \
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"ssr", "spc", \
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"r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", \
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"r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", \
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"fpul","fpscr", \
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"fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
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"fr8", "fr9", "fr10","fr11","fr12","fr13","fr14","fr15"\
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{ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
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"pc", "pr", "gbr", "vbr", "mach", "macl", "sr", \
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"fpul", "fpscr", \
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"fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \
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"fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15" \
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"ssr", "spc", \
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"r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0", \
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"r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1", \
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}
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#define NUM_REGS 59
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/* Register numbers of various important registers.
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Note that some of these values are "real" register numbers,
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and correspond to the general registers of the machine,
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and some are "phony" register numbers which are too large
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to be actual register numbers as far as the user is concerned
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but do serve to get the desired values when passed to read_register. */
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/* Register numbers of various important registers. Note that some of
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these values are "real" register numbers, and correspond to the
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general registers of the machine, and some are "phony" register
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numbers which are too large to be actual register numbers as far as
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the user is concerned but do serve to get the desired values when
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passed to read_register. */
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#define R0_REGNUM 0
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#define FP_REGNUM 14
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@ -139,12 +139,15 @@ extern CORE_ADDR sh_skip_prologue ();
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#define MACH_REGNUM 20
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#define MACL_REGNUM 21
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#define SR_REGNUM 22
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#define NUM_REALREGS 23
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#define FPUL_REGNUM 41
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#define FP0_REGNUM 43
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#define FP15_REGNUM 58
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#undef NUM_REALREGS
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#define NUM_REALREGS 59
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#define FPUL_REGNUM 23
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#define FP0_REGNUM 25
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#define FP15_REGNUM 40
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#define SSR_REGNUM 41
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#define SPC_REGNUM 42
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#define R0B0_REGNUM 43
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#define R0B1_REGNUM 51
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#define NUM_REALREGS 59
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/* Store the address of the place in which to copy the structure the
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subroutine will return. This is called from call_function.
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@ -161,7 +164,6 @@ extern CORE_ADDR sh_skip_prologue ();
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#define EXTRACT_RETURN_VALUE(TYPE,REGBUF,VALBUF) \
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memcpy (VALBUF, (char *)(REGBUF), TYPE_LENGTH(TYPE))
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/* Write into appropriate registers a function return value
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of type TYPE, given in virtual format.
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@ -170,7 +172,6 @@ extern CORE_ADDR sh_skip_prologue ();
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#define STORE_RETURN_VALUE(TYPE,VALBUF) \
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write_register_bytes (REGISTER_BYTE(4), VALBUF, TYPE_LENGTH (TYPE))
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/* Extract from an array REGBUF containing the (raw) register state
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the address in which a function should return its structure value,
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as a CORE_ADDR (or an expression that can be used as one). */
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@ -226,16 +227,13 @@ extern CORE_ADDR sh_skip_prologue ();
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typedef unsigned short INSN_WORD;
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#define ADDR_BITS_REMOVE(addr) ((addr))
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#define CALL_DUMMY_LENGTH 10
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/* Discard from the stack the innermost frame,
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restoring all saved registers. */
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/* Discard from the stack the innermost frame, restoring all saved
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registers. */
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#define POP_FRAME pop_frame();
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#define NOP {0x20, 0x0b}
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#define REGISTER_SIZE 4
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@ -50,39 +50,39 @@ char *tmp_sh_processor_type;
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char *sh_generic_reg_names[] = REGISTER_NAMES;
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char *sh_reg_names[] = {
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"pc", "pr", "gbr", "vbr", "mach","macl", "sr",
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"", "",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "",
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"","",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", ""
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
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"", "",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "",
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"", "",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "",
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};
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char *sh3_reg_names[] = {
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"pc", "pr", "gbr", "vbr", "mach","macl","sr",
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"ssr", "spc",
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
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"", "",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", "",
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"ssr", "spc",
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"r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
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"r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
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"", "",
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"", "", "", "", "", "", "", "",
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"", "", "", "", "", "", "", ""
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"r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
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};
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char *sh3e_reg_names[] = {
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"pc", "pr", "gbr", "vbr", "mach","macl","sr",
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"ssr", "spc",
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
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"fpul", "fpscr",
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"fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
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"fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
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"ssr", "spc",
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"r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
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"r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
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"fpul", "fpscr",
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"fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
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"fr8", "fr9", "fr10","fr11","fr12","fr13","fr14","fr15"
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};
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struct {
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@ -361,6 +361,8 @@ sh_set_processor_type_command (args, from_tty)
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}
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}
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/* This is a dummy not actually run. */
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static void
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sh_show_processor_type_command (args, from_tty)
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char *args;
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@ -70,14 +70,12 @@ sh3_supply_register (regname, regnamelen, val, vallen)
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else
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regno = GBR_REGNUM;
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break;
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#if 0
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case 'S':
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if (regname[1] == 'S' && regname[2] == 'R')
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regno = SSR_REGNUM;
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else if (regname[1] == 'P' && regname[2] == 'C')
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regno = SPC_REGNUM;
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break;
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#endif
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}
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}
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else if (regnamelen == 4)
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@ -108,7 +106,10 @@ sh3_supply_register (regname, regnamelen, val, vallen)
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numregs = 8;
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}
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}
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else if (regnamelen == 17)
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{
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}
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if (regno >= 0)
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while (numregs-- > 0)
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val = monitor_supply_register (regno++, val);
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@ -146,33 +147,32 @@ sh3_load (desc, file, hashmark)
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than does GDB, and don't necessarily support all the registers
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either. So, typing "info reg sp" becomes a "r30". */
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static char *sh3_regnames[NUM_REGS] = {
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"R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
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"R8", "R9", "R10", "R11","R12", "R13", "R14", "R15",
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"PC", "PR", "GBR", "VBR","MACH","MACL", "SR",
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NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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"SSR", "SPC",
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"R0_BANK0", "R1_BANK0", "R2_BANK0", "R3_BANK0",
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"R4_BANK0", "R5_BANK0", "R6_BANK0", "R7_BANK0",
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"R0_BANK1", "R1_BANK1", "R2_BANK1", "R3_BANK1",
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"R4_BANK1", "R5_BANK1", "R6_BANK1", "R7_BANK1",
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NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
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"R4_BANK1", "R5_BANK1", "R6_BANK1", "R7_BANK1"
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};
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static char *sh3e_regnames[NUM_REGS] = {
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"R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7",
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"R8", "R9", "R10", "R11","R12", "R13", "R14", "R15",
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"PC", "PR", "GBR", "VBR","MACH","MACL", "SR",
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"FPUL", "FPSCR",
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"FR0", "FR1", "FR2", "FR3", "FR4", "FR5", "FR6", "FR7",
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"FR8", "FR9", "FR10", "FR11", "FR12", "FR13", "FR14", "FR15",
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"SSR","SPC",
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"R0_BANK0", "R1_BANK0", "R2_BANK0", "R3_BANK0",
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"R4_BANK0", "R5_BANK0", "R6_BANK0", "R7_BANK0",
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"R0_BANK1", "R1_BANK1", "R2_BANK1", "R3_BANK1",
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"R4_BANK1", "R5_BANK1", "R6_BANK1", "R7_BANK1",
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"FPUL", "FPSCR",
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"FR0", "FR1", "FR2", "FR3", "FR4", "FR5", "FR6", "FR7",
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"FR8", "FR9", "FR10", "FR11", "FR12", "FR13", "FR14", "FR15"
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"R4_BANK1", "R5_BANK1", "R6_BANK1", "R7_BANK1"
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};
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/* Define the monitor command strings. Since these are passed directly
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