* mips-tdep.c (struct upk_mips16): Delete fields ``inst'' and
``fmt''. Make ``offset'' a CORE_ADDR. (print_unpack): Delete. (extended_offset): Construct and return a CORE_ADDR. (fetch_mips_16): Return an int. Don't assume short is 16 bits. (unpack_mips16): Rewrite. Add ``extension'' parameter instead of incorrectly guessing if the instruction had an extension. (map16): Delete array. (mips16_op): Delete macro. (extended_mips16_next_pc): Rewrite of old mips16_next_pc function. When an extended instruction do a recursive call. (mips16_next_pc): Call extended_mips16_next_pc. (mips_next_pc): Cleanup.
This commit is contained in:
Andrew Cagney
parent
55d8016036
commit
12f02c2abc
2 changed files with 184 additions and 179 deletions
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@ -1,3 +1,19 @@
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Thu Nov 30 01:24:37 2000 Andrew Cagney <cagney@b1.cygnus.com>
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* mips-tdep.c (struct upk_mips16): Delete fields ``inst'' and
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``fmt''. Make ``offset'' a CORE_ADDR.
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(print_unpack): Delete.
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(extended_offset): Construct and return a CORE_ADDR.
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(fetch_mips_16): Return an int. Don't assume short is 16 bits.
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(unpack_mips16): Rewrite. Add ``extension'' parameter instead of
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incorrectly guessing if the instruction had an extension.
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(map16): Delete array.
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(mips16_op): Delete macro.
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(extended_mips16_next_pc): Rewrite of old mips16_next_pc function.
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When an extended instruction do a recursive call.
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(mips16_next_pc): Call extended_mips16_next_pc.
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(mips_next_pc): Cleanup.
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Sat Dec 2 10:40:16 2000 Andrew Cagney <cagney@b1.cygnus.com>
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* ser-e7kpc.c (e7000pc_setstopbits): New function.
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347
gdb/mips-tdep.c
347
gdb/mips-tdep.c
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@ -861,34 +861,23 @@ enum mips16_inst_fmts
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extRi64type, /* 20 5,6,5,5,3,3,5 */
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extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
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};
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/* I am heaping all the fields of the formats into one structure and then,
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only the fields which are involved in instruction extension */
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/* I am heaping all the fields of the formats into one structure and
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then, only the fields which are involved in instruction extension */
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struct upk_mips16
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{
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unsigned short inst;
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enum mips16_inst_fmts fmt;
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unsigned long offset;
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CORE_ADDR offset;
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unsigned int regx; /* Function in i8 type */
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unsigned int regy;
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};
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/* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
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for the bits which make up the immediatate extension. */
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static void
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print_unpack (char *comment,
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struct upk_mips16 *u)
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static CORE_ADDR
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extended_offset (unsigned int extension)
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{
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printf ("%s %04x ,f(%d) off(%s) (x(%x) y(%x)\n",
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comment, u->inst, u->fmt, paddr (u->offset), u->regx, u->regy);
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}
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/* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same
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format for the bits which make up the immediatate extension.
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*/
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static unsigned long
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extended_offset (unsigned long extension)
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{
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unsigned long value;
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CORE_ADDR value;
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value = (extension >> 21) & 0x3f; /* * extract 15:11 */
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value = value << 6;
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value |= (extension >> 16) & 0x1f; /* extrace 10:5 */
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@ -906,7 +895,7 @@ extended_offset (unsigned long extension)
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when the offset is to be used in relative addressing */
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static unsigned short
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static unsigned int
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fetch_mips_16 (CORE_ADDR pc)
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{
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char buf[8];
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@ -917,36 +906,33 @@ fetch_mips_16 (CORE_ADDR pc)
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static void
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unpack_mips16 (CORE_ADDR pc,
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unsigned int extension,
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unsigned int inst,
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enum mips16_inst_fmts insn_format,
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struct upk_mips16 *upk)
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{
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CORE_ADDR extpc;
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unsigned long extension;
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int extended;
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extpc = (pc - 4) & ~0x01; /* Extensions are 32 bit instructions */
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/* Decrement to previous address and loose the 16bit mode flag */
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/* return if the instruction was extendable, but not actually extended */
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extended = ((mips32_op (extension) == 30) ? 1 : 0);
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if (extended)
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{
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extension = mips_fetch_instruction (extpc);
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}
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switch (upk->fmt)
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CORE_ADDR offset;
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int regx;
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int regy;
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switch (insn_format)
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{
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case itype:
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{
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unsigned long value;
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if (extended)
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CORE_ADDR value;
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if (extension)
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{
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value = extended_offset (extension);
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value = value << 11; /* rom for the original value */
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value |= upk->inst & 0x7ff; /* eleven bits from instruction */
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value |= inst & 0x7ff; /* eleven bits from instruction */
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}
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else
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{
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value = upk->inst & 0x7ff;
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value = inst & 0x7ff;
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/* FIXME : Consider sign extension */
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}
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upk->offset = value;
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offset = value;
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regx = -1;
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regy = -1;
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}
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break;
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case ritype:
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@ -954,13 +940,13 @@ unpack_mips16 (CORE_ADDR pc,
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{ /* A register identifier and an offset */
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/* Most of the fields are the same as I type but the
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immediate value is of a different length */
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unsigned long value;
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if (extended)
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CORE_ADDR value;
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if (extension)
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{
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value = extended_offset (extension);
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value = value << 8; /* from the original instruction */
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value |= upk->inst & 0xff; /* eleven bits from instruction */
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upk->regx = (extension >> 8) & 0x07; /* or i8 funct */
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value |= inst & 0xff; /* eleven bits from instruction */
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regx = (extension >> 8) & 0x07; /* or i8 funct */
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if (value & 0x4000) /* test the sign bit , bit 26 */
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{
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value &= ~0x3fff; /* remove the sign bit */
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@ -969,48 +955,41 @@ unpack_mips16 (CORE_ADDR pc,
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}
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else
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{
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value = upk->inst & 0xff; /* 8 bits */
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upk->regx = (upk->inst >> 8) & 0x07; /* or i8 funct */
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value = inst & 0xff; /* 8 bits */
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regx = (inst >> 8) & 0x07; /* or i8 funct */
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/* FIXME: Do sign extension , this format needs it */
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if (value & 0x80) /* THIS CONFUSES ME */
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{
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value &= 0xef; /* remove the sign bit */
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value = -value;
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}
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}
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upk->offset = value;
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offset = value;
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regy = -1;
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break;
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}
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case jalxtype:
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{
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unsigned long value;
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unsigned short nexthalf;
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value = ((upk->inst & 0x1f) << 5) | ((upk->inst >> 5) & 0x1f);
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unsigned int nexthalf;
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value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f);
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value = value << 16;
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nexthalf = mips_fetch_instruction (pc + 2); /* low bit still set */
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value |= nexthalf;
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upk->offset = value;
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offset = value;
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regx = -1;
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regy = -1;
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break;
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}
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default:
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printf_filtered ("Decoding unimplemented instruction format type\n");
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break;
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internal_error ("%s:%d: bad switch", __FILE__, __LINE__);
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}
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/* print_unpack("UPK",upk) ; */
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upk->offset = offset;
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upk->regx = regx;
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upk->regy = regy;
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}
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#define mips16_op(x) (x >> 11)
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/* This is a map of the opcodes which ae known to perform branches */
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static unsigned char map16[32] =
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{0, 0, 1, 1, 1, 1, 0, 0,
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0, 0, 0, 0, 1, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 1, 1, 0
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};
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static CORE_ADDR
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add_offset_16 (CORE_ADDR pc, int offset)
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{
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@ -1018,137 +997,147 @@ add_offset_16 (CORE_ADDR pc, int offset)
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}
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static struct upk_mips16 upk;
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static CORE_ADDR
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extended_mips16_next_pc (CORE_ADDR pc,
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unsigned int extension,
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unsigned int insn)
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{
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int op = (insn >> 11);
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switch (op)
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{
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case 2: /* Branch */
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{
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CORE_ADDR offset;
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struct upk_mips16 upk;
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unpack_mips16 (pc, extension, insn, itype, &upk);
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offset = upk.offset;
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if (offset & 0x800)
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{
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offset &= 0xeff;
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offset = -offset;
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}
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pc += (offset << 1) + 2;
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break;
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}
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case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
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{
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struct upk_mips16 upk;
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unpack_mips16 (pc, extension, insn, jalxtype, &upk);
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pc = add_offset_16 (pc, upk.offset);
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if ((insn >> 10) & 0x01) /* Exchange mode */
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pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */
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else
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pc |= 0x01;
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break;
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}
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case 4: /* beqz */
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{
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struct upk_mips16 upk;
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int reg;
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unpack_mips16 (pc, extension, insn, ritype, &upk);
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reg = read_signed_register (upk.regx);
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if (reg == 0)
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pc += (upk.offset << 1) + 2;
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else
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pc += 2;
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break;
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}
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case 5: /* bnez */
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{
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struct upk_mips16 upk;
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int reg;
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unpack_mips16 (pc, extension, insn, ritype, &upk);
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reg = read_signed_register (upk.regx);
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if (reg != 0)
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pc += (upk.offset << 1) + 2;
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else
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pc += 2;
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break;
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}
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case 12: /* I8 Formats btez btnez */
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{
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struct upk_mips16 upk;
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int reg;
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unpack_mips16 (pc, extension, insn, i8type, &upk);
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/* upk.regx contains the opcode */
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reg = read_signed_register (24); /* Test register is 24 */
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if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
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|| ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
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/* pc = add_offset_16(pc,upk.offset) ; */
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pc += (upk.offset << 1) + 2;
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else
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pc += 2;
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break;
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}
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case 29: /* RR Formats JR, JALR, JALR-RA */
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{
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struct upk_mips16 upk;
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/* upk.fmt = rrtype; */
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op = insn & 0x1f;
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if (op == 0)
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{
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int reg;
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upk.regx = (insn >> 8) & 0x07;
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upk.regy = (insn >> 5) & 0x07;
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switch (upk.regy)
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{
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case 0:
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reg = upk.regx;
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break;
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case 1:
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reg = 31;
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break; /* Function return instruction */
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case 2:
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reg = upk.regx;
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break;
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default:
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reg = 31;
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break; /* BOGUS Guess */
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}
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pc = read_signed_register (reg);
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}
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else
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pc += 2;
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break;
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}
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case 30:
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/* This is an instruction extension. Fetch the real instruction
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(which follows the extension) and decode things based on
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that. */
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{
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pc += 2;
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pc = extended_mips16_next_pc (pc, insn, fetch_mips_16 (pc));
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break;
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}
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default:
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{
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pc += 2;
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break;
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}
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}
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return pc;
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}
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CORE_ADDR
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mips16_next_pc (CORE_ADDR pc)
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{
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int op;
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t_inst inst;
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/* inst = mips_fetch_instruction(pc) ; - This doesnt always work */
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inst = fetch_mips_16 (pc);
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upk.inst = inst;
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op = mips16_op (upk.inst);
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if (map16[op])
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{
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int reg;
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switch (op)
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{
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case 2: /* Branch */
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upk.fmt = itype;
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unpack_mips16 (pc, &upk);
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{
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long offset;
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offset = upk.offset;
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if (offset & 0x800)
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{
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offset &= 0xeff;
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offset = -offset;
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}
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pc += (offset << 1) + 2;
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}
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break;
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case 3: /* JAL , JALX - Watch out, these are 32 bit instruction */
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upk.fmt = jalxtype;
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unpack_mips16 (pc, &upk);
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pc = add_offset_16 (pc, upk.offset);
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if ((upk.inst >> 10) & 0x01) /* Exchange mode */
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pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode */
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else
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pc |= 0x01;
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break;
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case 4: /* beqz */
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upk.fmt = ritype;
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unpack_mips16 (pc, &upk);
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reg = read_signed_register (upk.regx);
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if (reg == 0)
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pc += (upk.offset << 1) + 2;
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else
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pc += 2;
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break;
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case 5: /* bnez */
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upk.fmt = ritype;
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unpack_mips16 (pc, &upk);
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reg = read_signed_register (upk.regx);
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if (reg != 0)
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pc += (upk.offset << 1) + 2;
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else
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pc += 2;
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break;
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case 12: /* I8 Formats btez btnez */
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upk.fmt = i8type;
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unpack_mips16 (pc, &upk);
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/* upk.regx contains the opcode */
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reg = read_signed_register (24); /* Test register is 24 */
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if (((upk.regx == 0) && (reg == 0)) /* BTEZ */
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|| ((upk.regx == 1) && (reg != 0))) /* BTNEZ */
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/* pc = add_offset_16(pc,upk.offset) ; */
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pc += (upk.offset << 1) + 2;
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else
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pc += 2;
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break;
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case 29: /* RR Formats JR, JALR, JALR-RA */
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upk.fmt = rrtype;
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op = upk.inst & 0x1f;
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if (op == 0)
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{
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upk.regx = (upk.inst >> 8) & 0x07;
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upk.regy = (upk.inst >> 5) & 0x07;
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switch (upk.regy)
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{
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case 0:
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reg = upk.regx;
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break;
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case 1:
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reg = 31;
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break; /* Function return instruction */
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case 2:
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reg = upk.regx;
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break;
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default:
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reg = 31;
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break; /* BOGUS Guess */
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}
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pc = read_signed_register (reg);
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}
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else
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pc += 2;
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break;
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case 30: /* This is an extend instruction */
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pc += 4; /* Dont be setting breakpoints on the second half */
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break;
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default:
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printf ("Filtered - next PC probably incorrect due to jump inst\n");
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pc += 2;
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break;
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}
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}
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else
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pc += 2; /* just a good old instruction */
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/* See if we CAN actually break on the next instruction */
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/* printf("NXTm16PC %08x\n",(unsigned long)pc) ; */
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return pc;
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} /* mips16_next_pc */
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unsigned int insn = fetch_mips_16 (pc);
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return extended_mips16_next_pc (pc, 0, insn);
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}
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/* The mips_next_pc function supports single_step when the remote
|
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/* The mips_next_pc function supports single_step when the remote
|
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target monitor or stub is not developed enough to do a single_step.
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It works by decoding the current instruction and predicting where a branch
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will go. This isnt hard because all the data is available.
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The MIPS32 and MIPS16 variants are quite different
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*/
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It works by decoding the current instruction and predicting where a
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branch will go. This isnt hard because all the data is available.
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The MIPS32 and MIPS16 variants are quite different */
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CORE_ADDR
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mips_next_pc (CORE_ADDR pc)
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{
|
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t_inst inst;
|
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/* inst = mips_fetch_instruction(pc) ; */
|
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/* if (pc_is_mips16) <----- This is failing */
|
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if (pc & 0x01)
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return mips16_next_pc (pc);
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else
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return mips32_next_pc (pc);
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} /* mips_next_pc */
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||||
}
|
||||
|
||||
/* Guaranteed to set fci->saved_regs to some values (it never leaves it
|
||||
NULL). */
|
||||
|
|
|
|||
Loading…
Reference in a new issue