diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 64684cfac8..9191de98ec 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,4 +1,10 @@
 start-sanitize-tic80
+Thu Feb  6 17:30:15 1997  Fred Fish  <fnf@cygnus.com>
+
+	* tic80.h (TIC80_OPERAND_ENDMASK): Add for flagging TIc80
+	endmask fields, which are somewhat weird in that 0 and 32 are
+	treated exactly the same.
+
 Thu Jan 30 13:46:18 1997  Fred Fish  <fnf@cygnus.com>
 
 	* tic80.h: Change all the OPERAND defines to use the form (1 << X)
diff --git a/include/opcode/tic80.h b/include/opcode/tic80.h
index 4065528b7d..f37d938667 100644
--- a/include/opcode/tic80.h
+++ b/include/opcode/tic80.h
@@ -200,6 +200,15 @@ extern const struct tic80_operand tic80_operands[];
 
 #define TIC80_OPERAND_BASEREL	(1 << 11)
 
+/* This operand is an "endmask" field for a shift instruction.
+   It is treated special in that it can have values of 0-32,
+   where 0 and 32 result in the same instruction.  The assembler
+   must be able to accept both endmask values.  This disassembler
+   has no way of knowing from the instruction which value was 
+   given at assembly time, so it just uses '0'. */
+
+#define TIC80_OPERAND_ENDMASK	(1 << 12)
+
 /* This operand is one of the 32 general purpose registers.
    The disassembler prints these with a leading 'r'. */