Fix formatting. Update copyright date.
This commit is contained in:
Nick Clifton
parent
98a91d6ae2
commit
112290abe5
2 changed files with 66 additions and 63 deletions
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@ -1,3 +1,7 @@
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2003-03-17 Nick Clifton <nickc@redhat.com>
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* ppc-opc.c: Fix formatting. Update copyright date.
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2003-03-14 Daniel Jacobowitz <drow@mvista.com>
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* ppc-opc.c (powerpc_opcodes): Readd tlbre for PPC403.
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@ -1,24 +1,24 @@
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/* ppc-opc.c -- PowerPC opcode list
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Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002
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Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003
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Free Software Foundation, Inc.
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Written by Ian Lance Taylor, Cygnus Support
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This file is part of GDB, GAS, and the GNU binutils.
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This file is part of GDB, GAS, and the GNU binutils.
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version
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2, or (at your option) any later version.
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version
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2, or (at your option) any later version.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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the GNU General Public License for more details.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the Free
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Software Foundation, 59 Temple Place - Suite 330, Boston, MA
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02111-1307, USA. */
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the Free
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Software Foundation, 59 Temple Place - Suite 330, Boston, MA
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02111-1307, USA. */
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#include <stdio.h>
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#include "sysdep.h"
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@ -497,52 +497,52 @@ const struct powerpc_operand powerpc_operands[] =
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#define UI U + 1
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{ 16, 0, 0, 0, 0 },
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/* The VA field in a VA, VX or VXR form instruction. */
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/* The VA field in a VA, VX or VXR form instruction. */
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#define VA UI + 1
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#define VA_MASK (0x1f << 16)
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{ 5, 16, 0, 0, PPC_OPERAND_VR },
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/* The VB field in a VA, VX or VXR form instruction. */
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/* The VB field in a VA, VX or VXR form instruction. */
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#define VB VA + 1
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#define VB_MASK (0x1f << 11)
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{ 5, 11, 0, 0, PPC_OPERAND_VR },
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/* The VC field in a VA form instruction. */
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/* The VC field in a VA form instruction. */
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#define VC VB + 1
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#define VC_MASK (0x1f << 6)
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{ 5, 6, 0, 0, PPC_OPERAND_VR },
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/* The VD or VS field in a VA, VX, VXR or X form instruction. */
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/* The VD or VS field in a VA, VX, VXR or X form instruction. */
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#define VD VC + 1
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#define VS VD
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#define VD_MASK (0x1f << 21)
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{ 5, 21, 0, 0, PPC_OPERAND_VR },
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/* The SIMM field in a VX form instruction. */
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/* The SIMM field in a VX form instruction. */
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#define SIMM VD + 1
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{ 5, 16, 0, 0, PPC_OPERAND_SIGNED},
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/* The UIMM field in a VX form instruction. */
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/* The UIMM field in a VX form instruction. */
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#define UIMM SIMM + 1
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{ 5, 16, 0, 0, 0 },
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/* The SHB field in a VA form instruction. */
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/* The SHB field in a VA form instruction. */
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#define SHB UIMM + 1
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{ 4, 6, 0, 0, 0 },
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/* The other UIMM field in a EVX form instruction. */
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/* The other UIMM field in a EVX form instruction. */
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#define EVUIMM SHB + 1
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{ 5, 11, 0, 0, 0 },
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/* The other UIMM field in a half word EVX form instruction. */
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/* The other UIMM field in a half word EVX form instruction. */
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#define EVUIMM_2 EVUIMM + 1
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{ 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS },
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/* The other UIMM field in a word EVX form instruction. */
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/* The other UIMM field in a word EVX form instruction. */
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#define EVUIMM_4 EVUIMM_2 + 1
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{ 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS },
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/* The other UIMM field in a double EVX form instruction. */
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/* The other UIMM field in a double EVX form instruction. */
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#define EVUIMM_8 EVUIMM_4 + 1
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{ 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS },
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@ -1499,22 +1499,22 @@ extract_tbr (insn, dialect, invalid)
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#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
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#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)
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/* An VX form instruction. */
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/* An VX form instruction. */
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#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))
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/* The mask for an VX form instruction. */
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/* The mask for an VX form instruction. */
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#define VX_MASK VX(0x3f, 0x7ff)
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/* An VA form instruction. */
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/* An VA form instruction. */
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#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))
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/* The mask for an VA form instruction. */
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/* The mask for an VA form instruction. */
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#define VXA_MASK VXA(0x3f, 0x3f)
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/* An VXR form instruction. */
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/* An VXR form instruction. */
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#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))
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/* The mask for a VXR form instruction. */
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/* The mask for a VXR form instruction. */
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#define VXR_MASK VXR(0x3f, 0x3ff, 1)
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/* An X form instruction. */
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@ -1538,7 +1538,7 @@ extract_tbr (insn, dialect, invalid)
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/* An X_MASK with the RA and RB fields fixed. */
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#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
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/* An XRARB_MASK, but with the L bit clear. */
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/* An XRARB_MASK, but with the L bit clear. */
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#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
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/* An X_MASK with the RT and RA fields fixed. */
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@ -2349,34 +2349,34 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA,SISIGNOPT } },
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{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA, NSI } },
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{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
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{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
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{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
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{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
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{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
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{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
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{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
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{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
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{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
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{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
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{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
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{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
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{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
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{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
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{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
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{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
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{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
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{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
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{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
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{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
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{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
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{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
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{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
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{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
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{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
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{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
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{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
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{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
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{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
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{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
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{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } },
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{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } },
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{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
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{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
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{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } },
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{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } },
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{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
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{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
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{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } },
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{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } },
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{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
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{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
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{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } },
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{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } },
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{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } },
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{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } },
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{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } },
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{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } },
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{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } },
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{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } },
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{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } },
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{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } },
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{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } },
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{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } },
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{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } },
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{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } },
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{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } },
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{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } },
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{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } },
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@ -2625,7 +2625,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "ba", B(18,1,0), B_MASK, COM, { LIA } },
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{ "bla", B(18,1,1), B_MASK, COM, { LIA } },
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{ "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } },
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{ "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } },
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{ "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
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{ "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } },
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@ -2854,8 +2854,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } },
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{ "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } },
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{ "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
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{ "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } },
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{ "rfi", XL(19,50), 0xffffffff, COM, { 0 } },
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{ "rfci", XL(19,51), 0xffffffff, PPC403, { 0 } },
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