2002-11-30 Andrew Cagney <cagney@redhat.com>
* simops.c: Use int, 1, 0 instead of boolean, true and false. * sim-main.h: Ditto.
This commit is contained in:
parent
020cc13c3a
commit
0da2b66558
3 changed files with 26 additions and 21 deletions
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@ -1,3 +1,8 @@
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2002-11-30 Andrew Cagney <cagney@redhat.com>
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* simops.c: Use int, 1, 0 instead of boolean, true and false.
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* sim-main.h: Ditto.
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2002-09-27 Jim Wilson <wilson@redhat.com>
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* simops.c (OP_E6077E0): And op1 with 7 after reading register, not
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@ -374,14 +374,14 @@ extern void divun ( unsigned int N,
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unsigned long int sfi,
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unsigned32 /*unsigned long int*/ * quotient_ptr,
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unsigned32 /*unsigned long int*/ * remainder_ptr,
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boolean * overflow_ptr
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int *overflow_ptr
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);
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extern void divn ( unsigned int N,
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unsigned long int als,
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unsigned long int sfi,
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signed32 /*signed long int*/ * quotient_ptr,
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signed32 /*signed long int*/ * remainder_ptr,
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boolean * overflow_ptr
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int *overflow_ptr
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);
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extern int type1_regs[];
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extern int type2_regs[];
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@ -329,7 +329,7 @@ Add32 (unsigned long a1, unsigned long a2, int * carry)
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}
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static void
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Multiply64 (boolean sign, unsigned long op0)
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Multiply64 (int sign, unsigned long op0)
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{
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unsigned long op1;
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unsigned long lo;
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@ -1911,7 +1911,7 @@ OP_22207E0 (void)
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{
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trace_input ("mulu", OP_REG_REG_REG, 0);
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Multiply64 (false, State.regs[ OP[0] ]);
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Multiply64 (0, State.regs[ OP[0] ]);
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trace_output (OP_REG_REG_REG);
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@ -1982,7 +1982,7 @@ divun
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unsigned long int sfi,
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unsigned32 /*unsigned long int*/ * quotient_ptr,
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unsigned32 /*unsigned long int*/ * remainder_ptr,
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boolean * overflow_ptr
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int * overflow_ptr
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)
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{
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unsigned long ald = sfi >> (N - 1);
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@ -2056,7 +2056,7 @@ divn
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unsigned long int sfi,
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signed32 /*signed long int*/ * quotient_ptr,
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signed32 /*signed long int*/ * remainder_ptr,
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boolean * overflow_ptr
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int * overflow_ptr
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)
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{
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unsigned long ald = (signed long) sfi >> (N - 1);
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@ -2155,7 +2155,7 @@ OP_1C207E0 (void)
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unsigned32 /*unsigned long int*/ remainder;
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unsigned long int divide_by;
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unsigned long int divide_this;
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boolean overflow = false;
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int overflow = 0;
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unsigned int imm5;
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trace_input ("sdivun", OP_IMM_REG_REG_REG, 0);
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@ -2190,7 +2190,7 @@ OP_1C007E0 (void)
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signed32 /*signed long int*/ remainder;
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signed long int divide_by;
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signed long int divide_this;
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boolean overflow = false;
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int overflow = 0;
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unsigned int imm5;
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trace_input ("sdivn", OP_IMM_REG_REG_REG, 0);
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@ -2225,7 +2225,7 @@ OP_18207E0 (void)
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unsigned32 /*unsigned long int*/ remainder;
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unsigned long int divide_by;
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unsigned long int divide_this;
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boolean overflow = false;
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int overflow = 0;
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unsigned int imm5;
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trace_input ("sdivhun", OP_IMM_REG_REG_REG, 0);
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@ -2260,7 +2260,7 @@ OP_18007E0 (void)
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signed32 /*signed long int*/ remainder;
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signed long int divide_by;
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signed long int divide_this;
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boolean overflow = false;
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int overflow = 0;
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unsigned int imm5;
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trace_input ("sdivhn", OP_IMM_REG_REG_REG, 0);
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@ -2295,7 +2295,7 @@ OP_2C207E0 (void)
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unsigned long int remainder;
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unsigned long int divide_by;
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unsigned long int divide_this;
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boolean overflow = false;
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int overflow = 0;
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trace_input ("divu", OP_REG_REG_REG, 0);
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@ -2306,7 +2306,7 @@ OP_2C207E0 (void)
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if (divide_by == 0)
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{
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overflow = true;
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overflow = 1;
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divide_by = 1;
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}
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@ -2333,7 +2333,7 @@ OP_2C007E0 (void)
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signed long int remainder;
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signed long int divide_by;
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signed long int divide_this;
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boolean overflow = false;
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int overflow = 0;
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trace_input ("div", OP_REG_REG_REG, 0);
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@ -2344,7 +2344,7 @@ OP_2C007E0 (void)
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if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
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{
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overflow = true;
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overflow = 1;
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divide_by = 1;
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}
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@ -2371,7 +2371,7 @@ OP_28207E0 (void)
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unsigned long int remainder;
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unsigned long int divide_by;
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unsigned long int divide_this;
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boolean overflow = false;
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int overflow = 0;
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trace_input ("divhu", OP_REG_REG_REG, 0);
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@ -2382,7 +2382,7 @@ OP_28207E0 (void)
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if (divide_by == 0)
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{
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overflow = true;
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overflow = 1;
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divide_by = 1;
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}
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@ -2409,7 +2409,7 @@ OP_28007E0 (void)
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signed long int remainder;
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signed long int divide_by;
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signed long int divide_this;
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boolean overflow = false;
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int overflow = 0;
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trace_input ("divh", OP_REG_REG_REG, 0);
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@ -2420,7 +2420,7 @@ OP_28007E0 (void)
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if (divide_by == 0 || (divide_by == -1 && divide_this == (1 << 31)))
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{
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overflow = true;
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overflow = 1;
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divide_by = 1;
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}
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@ -2445,7 +2445,7 @@ OP_24207E0 (void)
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{
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trace_input ("mulu", OP_IMM_REG_REG, 0);
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Multiply64 (false, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
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Multiply64 (0, (OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0));
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trace_output (OP_IMM_REG_REG);
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@ -2458,7 +2458,7 @@ OP_24007E0 (void)
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{
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trace_input ("mul", OP_IMM_REG_REG, 0);
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Multiply64 (true, SEXT9 ((OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0)));
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Multiply64 (1, SEXT9 ((OP[3] & 0x1f) | ((OP[3] >> 13) & 0x1e0)));
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trace_output (OP_IMM_REG_REG);
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@ -2608,7 +2608,7 @@ OP_22007E0 (void)
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{
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trace_input ("mul", OP_REG_REG_REG, 0);
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Multiply64 (true, State.regs[ OP[0] ]);
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Multiply64 (1, State.regs[ OP[0] ]);
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trace_output (OP_REG_REG_REG);
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