From 0bf55db8fd2e1022e91392223925e93541da72be Mon Sep 17 00:00:00 2001 From: Doug Evans Date: Mon, 23 Feb 1998 21:20:37 +0000 Subject: [PATCH] * m32r-asm.c,m32r-dis.c,m32r-opc.h,m32r-opc.c: Regenerate. --- opcodes/ChangeLog | 2 + opcodes/m32r-asm.c | 349 +++++++-------- opcodes/m32r-dis.c | 33 +- opcodes/m32r-opc.c | 1035 ++++++++++++++++++++++++-------------------- opcodes/m32r-opc.h | 8 +- 5 files changed, 738 insertions(+), 689 deletions(-) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 9b3b25edfd..9a1646433c 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -3,6 +3,8 @@ Mon Feb 23 13:16:17 1998 Doug Evans * cgen-asm.c: Include symcat.h. * cgen-dis.c,cgen-opc.c,cgen-asm.in,cgen-dis.in: Ditto. + * m32r-asm.c,m32r-dis.c,m32r-opc.h,m32r-opc.c: Regenerate. + start-sanitize-sky Mon Feb 23 09:51:39 1998 Doug Evans diff --git a/opcodes/m32r-asm.c b/opcodes/m32r-asm.c index 318fa2df9a..27f5ea98ae 100644 --- a/opcodes/m32r-asm.c +++ b/opcodes/m32r-asm.c @@ -3,7 +3,7 @@ This file is used to generate m32r-asm.c. -Copyright (C) 1996, 1997 Free Software Foundation, Inc. +Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -26,6 +26,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include #include "ansidecl.h" #include "bfd.h" +#include "symcat.h" #include "m32r-opc.h" /* ??? The layout of this stuff is still work in progress. @@ -37,34 +38,64 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ static const char * parse_insn_normal PARAMS ((const CGEN_INSN *, const char **, CGEN_FIELDS *)); -static void insert_insn_normal +static const char * insert_insn_normal PARAMS ((const CGEN_INSN *, CGEN_FIELDS *, cgen_insn_t *)); /* Default insertion routine. - SHIFT is negative for left shifts, positive for right shifts. - All bits of VALUE to be inserted must be valid as we don't handle - signed vs unsigned shifts. + ATTRS is a mask of the boolean attributes. + LENGTH is the length of VALUE in bits. + TOTAL_LENGTH is the total length of the insn (currently 8,16,32). - ATTRS is a mask of the boolean attributes. We don't need any at the - moment, but for consistency with extract_normal we have them. */ + The result is an error message or NULL if success. */ -/* FIXME: This duplicates functionality with bfd's howto table and +/* ??? This duplicates functionality with bfd's howto table and bfd_install_relocation. */ -/* FIXME: For architectures where insns can be representable as ints, - store insn in `field' struct and add registers, etc. while parsing. */ +/* ??? For architectures where insns can be representable as ints, + store insn in `field' struct and add registers, etc. while parsing? */ -static CGEN_INLINE void +static const char * insert_normal (value, attrs, start, length, shift, total_length, buffer) - long value; + long value; unsigned int attrs; - int start; - int length; - int shift; - int total_length; - char * buffer; + int start; + int length; + int shift; + int total_length; + char * buffer; { bfd_vma x; + static char buf[100]; + + if (shift < 0) + value <<= -shift; + else + value >>= shift; + + /* Ensure VALUE will fit. */ + if ((attrs & (1 << CGEN_OPERAND_UNSIGNED)) != 0) + { + unsigned long max = (1 << length) - 1; + if ((unsigned long) value > max) + { + const char *err = "operand out of range (%lu not between 0 and %lu)"; + + sprintf (buf, err, value, max); + return buf; + } + } + else + { + long min = - (1 << (length - 1)); + long max = (1 << (length - 1)) - 1; + if (value < min || value > max) + { + const char *err = "operand out of range (%ld not between %ld and %ld)"; + + sprintf (buf, err, value, min, max); + return buf; + } + } #if 0 /*def CGEN_INT_INSN*/ *buffer |= ((value & ((1 << length) - 1)) @@ -91,11 +122,6 @@ insert_normal (value, attrs, start, length, shift, total_length, buffer) abort (); } - if (shift < 0) - value <<= -shift; - else - value >>= shift; - x |= ((value & ((1 << length) - 1)) << (total_length - (start + length))); @@ -120,6 +146,8 @@ insert_normal (value, attrs, start, length, shift, total_length, buffer) abort (); } #endif + + return NULL; } /* -- assembler routines inserted here */ @@ -128,10 +156,9 @@ insert_normal (value, attrs, start, length, shift, total_length, buffer) /* Handle shigh(), high(). */ static const char * -parse_h_hi16 (strp, opindex, min, max, valuep) +parse_h_hi16 (strp, opindex, valuep) const char **strp; int opindex; - unsigned long min, max; unsigned long *valuep; { const char *errmsg; @@ -168,7 +195,7 @@ parse_h_hi16 (strp, opindex, min, max, valuep) return errmsg; } - return cgen_parse_unsigned_integer (strp, opindex, min, max, valuep); + return cgen_parse_unsigned_integer (strp, opindex, valuep); } /* Handle low() in a signed context. Also handle sda(). @@ -176,10 +203,9 @@ parse_h_hi16 (strp, opindex, min, max, valuep) handles the case where low() isn't present. */ static const char * -parse_h_slo16 (strp, opindex, min, max, valuep) +parse_h_slo16 (strp, opindex, valuep) const char **strp; int opindex; - long min, max; long *valuep; { const char *errmsg; @@ -197,6 +223,9 @@ parse_h_slo16 (strp, opindex, min, max, valuep) if (**strp != ')') return "missing `)'"; ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + *valuep &= 0xffff; return errmsg; } @@ -210,7 +239,7 @@ parse_h_slo16 (strp, opindex, min, max, valuep) return errmsg; } - return cgen_parse_signed_integer (strp, opindex, min, max, valuep); + return cgen_parse_signed_integer (strp, opindex, valuep); } /* Handle low() in an unsigned context. @@ -218,10 +247,9 @@ parse_h_slo16 (strp, opindex, min, max, valuep) handles the case where low() isn't present. */ static const char * -parse_h_ulo16 (strp, opindex, min, max, valuep) +parse_h_ulo16 (strp, opindex, valuep) const char **strp; int opindex; - unsigned long min, max; unsigned long *valuep; { const char *errmsg; @@ -239,10 +267,13 @@ parse_h_ulo16 (strp, opindex, min, max, valuep) if (**strp != ')') return "missing `)'"; ++*strp; + if (errmsg == NULL + && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) + *valuep &= 0xffff; return errmsg; } - return cgen_parse_unsigned_integer (strp, opindex, min, max, valuep); + return cgen_parse_unsigned_integer (strp, opindex, valuep); } /* -- */ @@ -261,7 +292,7 @@ parse_h_ulo16 (strp, opindex, min, max, valuep) the handlers. */ -CGEN_INLINE const char * +const char * m32r_cgen_parse_operand (opindex, strp, fields) int opindex; const char ** strp; @@ -290,23 +321,23 @@ m32r_cgen_parse_operand (opindex, strp, fields) errmsg = cgen_parse_keyword (strp, & m32r_cgen_opval_h_cr, & fields->f_r1); break; case M32R_OPERAND_SIMM8 : - errmsg = cgen_parse_signed_integer (strp, 7, -128, 127, &fields->f_simm8); + errmsg = cgen_parse_signed_integer (strp, M32R_OPERAND_SIMM8, &fields->f_simm8); break; case M32R_OPERAND_SIMM16 : - errmsg = cgen_parse_signed_integer (strp, 8, -32768, 32767, &fields->f_simm16); + errmsg = cgen_parse_signed_integer (strp, M32R_OPERAND_SIMM16, &fields->f_simm16); break; case M32R_OPERAND_UIMM4 : - errmsg = cgen_parse_unsigned_integer (strp, 9, 0, 15, &fields->f_uimm4); + errmsg = cgen_parse_unsigned_integer (strp, M32R_OPERAND_UIMM4, &fields->f_uimm4); break; case M32R_OPERAND_UIMM5 : - errmsg = cgen_parse_unsigned_integer (strp, 10, 0, 31, &fields->f_uimm5); + errmsg = cgen_parse_unsigned_integer (strp, M32R_OPERAND_UIMM5, &fields->f_uimm5); break; case M32R_OPERAND_UIMM16 : - errmsg = cgen_parse_unsigned_integer (strp, 11, 0, 65535, &fields->f_uimm16); + errmsg = cgen_parse_unsigned_integer (strp, M32R_OPERAND_UIMM16, &fields->f_uimm16); break; /* start-sanitize-m32rx */ case M32R_OPERAND_IMM1 : - errmsg = cgen_parse_unsigned_integer (strp, 12, 0, 1, &fields->f_imm1); + errmsg = cgen_parse_unsigned_integer (strp, M32R_OPERAND_IMM1, &fields->f_imm1); break; /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ @@ -325,25 +356,25 @@ m32r_cgen_parse_operand (opindex, strp, fields) break; /* end-sanitize-m32rx */ case M32R_OPERAND_HI16 : - errmsg = parse_h_hi16 (strp, 16, 0, 65535, &fields->f_hi16); + errmsg = parse_h_hi16 (strp, M32R_OPERAND_HI16, &fields->f_hi16); break; case M32R_OPERAND_SLO16 : - errmsg = parse_h_slo16 (strp, 17, -32768, 32767, &fields->f_simm16); + errmsg = parse_h_slo16 (strp, M32R_OPERAND_SLO16, &fields->f_simm16); break; case M32R_OPERAND_ULO16 : - errmsg = parse_h_ulo16 (strp, 18, 0, 65535, &fields->f_uimm16); + errmsg = parse_h_ulo16 (strp, M32R_OPERAND_ULO16, &fields->f_uimm16); break; case M32R_OPERAND_UIMM24 : - errmsg = cgen_parse_address (strp, 19, 0, NULL, & fields->f_uimm24); + errmsg = cgen_parse_address (strp, M32R_OPERAND_UIMM24, 0, NULL, & fields->f_uimm24); break; case M32R_OPERAND_DISP8 : - errmsg = cgen_parse_address (strp, 20, 0, NULL, & fields->f_disp8); + errmsg = cgen_parse_address (strp, M32R_OPERAND_DISP8, 0, NULL, & fields->f_disp8); break; case M32R_OPERAND_DISP16 : - errmsg = cgen_parse_address (strp, 21, 0, NULL, & fields->f_disp16); + errmsg = cgen_parse_address (strp, M32R_OPERAND_DISP16, 0, NULL, & fields->f_disp16); break; case M32R_OPERAND_DISP24 : - errmsg = cgen_parse_address (strp, 22, 0, NULL, & fields->f_disp24); + errmsg = cgen_parse_address (strp, M32R_OPERAND_DISP24, 0, NULL, & fields->f_disp24); break; default : @@ -369,87 +400,101 @@ m32r_cgen_parse_operand (opindex, strp, fields) resolved during parsing. */ -CGEN_INLINE void +const char * m32r_cgen_insert_operand (opindex, fields, buffer) int opindex; CGEN_FIELDS * fields; - cgen_insn_t * buffer; + char * buffer; { + const char * errmsg; + switch (opindex) { case M32R_OPERAND_SR : - insert_normal (fields->f_r2, 0|(1<f_r2, 0|(1<f_r1, 0|(1<f_r1, 0|(1<f_r1, 0|(1<f_r1, 0|(1<f_r2, 0|(1<f_r2, 0|(1<f_r2, 0|(1<f_r2, 0|(1<f_r1, 0|(1<f_r1, 0|(1<f_simm8, 0, 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), buffer); + errmsg = insert_normal (fields->f_simm8, 0, 8, 8, 0, CGEN_FIELDS_BITSIZE (fields), buffer); break; case M32R_OPERAND_SIMM16 : - insert_normal (fields->f_simm16, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer); + errmsg = insert_normal (fields->f_simm16, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer); break; case M32R_OPERAND_UIMM4 : - insert_normal (fields->f_uimm4, 0|(1<f_uimm4, 0|(1<f_uimm5, 0|(1<f_uimm5, 0|(1<f_uimm16, 0|(1<f_uimm16, 0|(1<f_imm1, 0|(1<f_imm1) - (1)); + errmsg = insert_normal (value, 0|(1<f_accd, 0|(1<f_accd, 0|(1<f_accs, 0|(1<f_accs, 0|(1<f_acc, 0|(1<f_acc, 0|(1<f_hi16, 0|(1<f_hi16, 0|(1<f_simm16, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer); + errmsg = insert_normal (fields->f_simm16, 0, 16, 16, 0, CGEN_FIELDS_BITSIZE (fields), buffer); break; case M32R_OPERAND_ULO16 : - insert_normal (fields->f_uimm16, 0|(1<f_uimm16, 0|(1<f_uimm24, 0|(1<f_uimm24, 0|(1<f_disp8, 0|(1<f_disp8) >> (2)); + errmsg = insert_normal (value, 0|(1<f_disp16, 0|(1<f_disp16) >> (2)); + errmsg = insert_normal (value, 0|(1<f_disp24, 0|(1<f_disp24) >> (2)); + errmsg = insert_normal (value, 0|(1<f_simm8, -128, 127); - break; - case M32R_OPERAND_SIMM16 : - errmsg = cgen_validate_signed_integer (fields->f_simm16, -32768, 32767); - break; - case M32R_OPERAND_UIMM4 : - errmsg = cgen_validate_unsigned_integer (fields->f_uimm4, 0, 15); - break; - case M32R_OPERAND_UIMM5 : - errmsg = cgen_validate_unsigned_integer (fields->f_uimm5, 0, 31); - break; - case M32R_OPERAND_UIMM16 : - errmsg = cgen_validate_unsigned_integer (fields->f_uimm16, 0, 65535); - break; -/* start-sanitize-m32rx */ - case M32R_OPERAND_IMM1 : - errmsg = cgen_validate_unsigned_integer (fields->f_imm1, 0, 1); - break; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - case M32R_OPERAND_ACCD : - /* nothing to do */ - break; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - case M32R_OPERAND_ACCS : - /* nothing to do */ - break; -/* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - case M32R_OPERAND_ACC : - /* nothing to do */ - break; -/* end-sanitize-m32rx */ - case M32R_OPERAND_HI16 : - errmsg = cgen_validate_unsigned_integer (fields->f_hi16, 0, 65535); - break; - case M32R_OPERAND_SLO16 : - errmsg = cgen_validate_signed_integer (fields->f_simm16, -32768, 32767); - break; - case M32R_OPERAND_ULO16 : - errmsg = cgen_validate_unsigned_integer (fields->f_uimm16, 0, 65535); - break; - case M32R_OPERAND_UIMM24 : - /* nothing to do */ - break; - case M32R_OPERAND_DISP8 : - /* nothing to do */ - break; - case M32R_OPERAND_DISP16 : - /* nothing to do */ - break; - case M32R_OPERAND_DISP24 : - /* nothing to do */ - break; - - default : - fprintf (stderr, "Unrecognized field %d while validating operand.\n", - opindex); - abort (); - } return errmsg; } @@ -600,17 +545,17 @@ m32r_cgen_init_asm (mach, endian) static const char * parse_insn_normal (insn, strp, fields) - const CGEN_INSN * insn; - const char ** strp; - CGEN_FIELDS * fields; + const CGEN_INSN * insn; + const char ** strp; + CGEN_FIELDS * fields; { - const CGEN_SYNTAX * syntax = CGEN_INSN_SYNTAX (insn); - const char * str = *strp; - const char * errmsg; - const char * p; + const CGEN_SYNTAX * syntax = CGEN_INSN_SYNTAX (insn); + const char * str = *strp; + const char * errmsg; + const char * p; const unsigned char * syn; #ifdef CGEN_MNEMONIC_OPERANDS - int past_opcode_p; + int past_opcode_p; #endif /* For now we assume the mnemonic is first (there are no leading operands). @@ -630,13 +575,13 @@ parse_insn_normal (insn, strp, fields) /* We don't check for (*str != '\0') here because we want to parse any trailing fake arguments in the syntax string. */ syn = CGEN_SYNTAX_STRING (CGEN_INSN_SYNTAX (insn)); - + /* Mnemonics come first for now, ensure valid string. */ if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) abort (); - + ++syn; - + while (* syn != 0) { /* Non operand chars must match exactly. */ @@ -655,7 +600,8 @@ parse_insn_normal (insn, strp, fields) else { /* Syntax char didn't match. Can't be this insn. */ - /* FIXME: would like to return "expected char `c'" */ + /* FIXME: would like to return something like + "expected char `c'" */ return "syntax error"; } continue; @@ -692,16 +638,18 @@ parse_insn_normal (insn, strp, fields) } /* Default insn builder (insert handler). - The instruction is recorded in target byte order. */ + The instruction is recorded in target byte order. + The result is an error message or NULL if success. */ +/* FIXME: change buffer to char *? */ -static void +static const char * insert_insn_normal (insn, fields, buffer) - const CGEN_INSN * insn; - CGEN_FIELDS * fields; - cgen_insn_t * buffer; + const CGEN_INSN * insn; + CGEN_FIELDS * fields; + cgen_insn_t * buffer; { - const CGEN_SYNTAX * syntax = CGEN_INSN_SYNTAX (insn); - bfd_vma value; + const CGEN_SYNTAX * syntax = CGEN_INSN_SYNTAX (insn); + bfd_vma value; const unsigned char * syn; CGEN_INIT_INSERT (); @@ -741,11 +689,18 @@ insert_insn_normal (insn, fields, buffer) for (syn = CGEN_SYNTAX_STRING (syntax); * syn != '\0'; ++ syn) { + const char *errmsg; + if (CGEN_SYNTAX_CHAR_P (* syn)) continue; - m32r_cgen_insert_operand (CGEN_SYNTAX_FIELD (*syn), fields, buffer); + errmsg = m32r_cgen_insert_operand (CGEN_SYNTAX_FIELD (*syn), fields, + (char *) buffer); + if (errmsg) + return errmsg; } + + return NULL; } /* Main entry point. @@ -758,12 +713,12 @@ insert_insn_normal (insn, fields, buffer) const CGEN_INSN * m32r_cgen_assemble_insn (str, fields, buf, errmsg) - const char * str; + const char * str; CGEN_FIELDS * fields; cgen_insn_t * buf; - char ** errmsg; + char ** errmsg; { - const char * start; + const char * start; CGEN_INSN_LIST * ilist; /* Skip leading white space. */ @@ -802,16 +757,10 @@ m32r_cgen_assemble_insn (str, fields, buf, errmsg) /* FIXME: wip */ CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); - /* ??? The extent to which moving the parse and insert handlers into - this function (thus removing the function call) will speed things up - is unclear. The simplicity and flexibility of the current scheme is - appropriate for now. One could have the best of both worlds with - inline functions but of course that would only work for gcc. Since - we're machine generating some code we could do that here too. Maybe - later. */ if (! CGEN_PARSE_FN (insn) (insn, & str, fields)) { - CGEN_INSERT_FN (insn) (insn, fields, buf); + if (CGEN_INSERT_FN (insn) (insn, fields, buf) != NULL) + continue; /* It is up to the caller to actually output the insn and any queued relocs. */ return insn; diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c index 9b467eb053..dbe52826ca 100644 --- a/opcodes/m32r-dis.c +++ b/opcodes/m32r-dis.c @@ -26,6 +26,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "ansidecl.h" #include "dis-asm.h" #include "bfd.h" +#include "symcat.h" #include "m32r-opc.h" /* ??? The layout of this stuff is still work in progress. @@ -87,6 +88,8 @@ extract_normal (buf_ctrl, insn_value, attrs, start, length, shift, total_length, value <<= shift; *valuep = value; + + /* FIXME: for now */ return 1; } @@ -194,7 +197,7 @@ my_print_insn (pc, info, buf, buflen) the handlers. */ -CGEN_INLINE int +int m32r_cgen_extract_operand (opindex, buf_ctrl, insn_value, fields) int opindex; PTR buf_ctrl; @@ -240,7 +243,11 @@ m32r_cgen_extract_operand (opindex, buf_ctrl, insn_value, fields) break; /* start-sanitize-m32rx */ case M32R_OPERAND_IMM1 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_imm1); + { + long value; + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_imm1 = ((value) + (1)); + } break; /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ @@ -271,13 +278,25 @@ m32r_cgen_extract_operand (opindex, buf_ctrl, insn_value, fields) length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_uimm24); break; case M32R_OPERAND_DISP8 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_disp8); + { + long value; + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_disp8 = ((value) << (2)); + } break; case M32R_OPERAND_DISP16 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_disp16); + { + long value; + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_disp16 = ((value) << (2)); + } break; case M32R_OPERAND_DISP24 : - length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_disp24); + { + long value; + length = extract_normal (NULL /*FIXME*/, insn_value, 0|(1<f_disp24 = ((value) << (2)); + } break; default : @@ -303,7 +322,7 @@ m32r_cgen_extract_operand (opindex, buf_ctrl, insn_value, fields) the handlers. */ -CGEN_INLINE void +void m32r_cgen_print_operand (opindex, info, fields, attrs, pc, length) int opindex; disassemble_info * info; @@ -448,7 +467,7 @@ extract_insn_normal (insn, buf_ctrl, insn_value, fields) continue; length = m32r_cgen_extract_operand (CGEN_SYNTAX_FIELD (*syn), - buf_ctrl, insn_value, fields); + buf_ctrl, insn_value, fields); if (length == 0) return 0; } diff --git a/opcodes/m32r-opc.c b/opcodes/m32r-opc.c index b69de02ee7..f42f141bff 100644 --- a/opcodes/m32r-opc.c +++ b/opcodes/m32r-opc.c @@ -314,6 +314,7 @@ static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] = #define OPERAND(op) CONCAT2 (M32R_OPERAND_,op) #define OP_ENT(op) m32r_cgen_operand_table[OPERAND (op)] + const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] = { /* pc: program counter */ @@ -399,11 +400,6 @@ const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] = /* accum: accumulator */ { "accum", & HW_ENT (HW_H_ACCUM), 0, 0, { 0, 0|(1< $dr,$sr */ -/* 0 */ { MNEM, ' ', OP (DR), ',', OP (SR), 0 }, -/* $dr,$sr,#$slo16 */ -/* 1 */ { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (SLO16), 0 }, -/* $dr,$sr,$slo16 */ -/* 2 */ { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SLO16), 0 }, -/* $dr,$sr,#$uimm16 */ -/* 3 */ { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (UIMM16), 0 }, -/* $dr,$sr,$uimm16 */ -/* 4 */ { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (UIMM16), 0 }, -/* $dr,$sr,#$ulo16 */ -/* 5 */ { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (ULO16), 0 }, -/* $dr,$sr,$ulo16 */ -/* 6 */ { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (ULO16), 0 }, -/* $dr,#$simm8 */ -/* 7 */ { MNEM, ' ', OP (DR), ',', '#', OP (SIMM8), 0 }, -/* $dr,$simm8 */ -/* 8 */ { MNEM, ' ', OP (DR), ',', OP (SIMM8), 0 }, -/* $dr,$sr,#$simm16 */ -/* 9 */ { MNEM, ' ', OP (DR), ',', OP (SR), ',', '#', OP (SIMM16), 0 }, -/* $dr,$sr,$simm16 */ -/* 10 */ { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 }, -/* $disp8 */ -/* 11 */ { MNEM, ' ', OP (DISP8), 0 }, -/* $disp24 */ -/* 12 */ { MNEM, ' ', OP (DISP24), 0 }, -/* $src1,$src2,$disp16 */ -/* 13 */ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (DISP16), 0 }, -/* $src2,$disp16 */ -/* 14 */ { MNEM, ' ', OP (SRC2), ',', OP (DISP16), 0 }, -/* $src1,$src2 */ -/* 15 */ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), 0 }, -/* $src2,#$simm16 */ -/* 16 */ { MNEM, ' ', OP (SRC2), ',', '#', OP (SIMM16), 0 }, -/* $src2,$simm16 */ -/* 17 */ { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 }, -/* $src2,#$uimm16 */ -/* 18 */ { MNEM, ' ', OP (SRC2), ',', '#', OP (UIMM16), 0 }, -/* $src2,$uimm16 */ -/* 19 */ { MNEM, ' ', OP (SRC2), ',', OP (UIMM16), 0 }, -/* $src2 */ -/* 20 */ { MNEM, ' ', OP (SRC2), 0 }, -/* $sr */ -/* 21 */ { MNEM, ' ', OP (SR), 0 }, -/* $dr,@$sr */ -/* 22 */ { MNEM, ' ', OP (DR), ',', '@', OP (SR), 0 }, -/* $dr,@($sr) */ -/* 23 */ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ')', 0 }, -/* $dr,@($slo16,$sr) */ -/* 24 */ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SLO16), ',', OP (SR), ')', 0 }, -/* $dr,@($sr,$slo16) */ -/* 25 */ { MNEM, ' ', OP (DR), ',', '@', '(', OP (SR), ',', OP (SLO16), ')', 0 }, -/* $dr,@$sr+ */ -/* 26 */ { MNEM, ' ', OP (DR), ',', '@', OP (SR), '+', 0 }, -/* $dr,#$uimm24 */ -/* 27 */ { MNEM, ' ', OP (DR), ',', '#', OP (UIMM24), 0 }, -/* $dr,$uimm24 */ -/* 28 */ { MNEM, ' ', OP (DR), ',', OP (UIMM24), 0 }, -/* $dr,$slo16 */ -/* 29 */ { MNEM, ' ', OP (DR), ',', OP (SLO16), 0 }, -/* $src1,$src2,$acc */ -/* 30 */ { MNEM, ' ', OP (SRC1), ',', OP (SRC2), ',', OP (ACC), 0 }, -/* $dr */ -/* 31 */ { MNEM, ' ', OP (DR), 0 }, -/* $dr,$accs */ -/* 32 */ { MNEM, ' ', OP (DR), ',', OP (ACCS), 0 }, -/* $dr,$scr */ -/* 33 */ { MNEM, ' ', OP (DR), ',', OP (SCR), 0 }, -/* $src1 */ -/* 34 */ { MNEM, ' ', OP (SRC1), 0 }, -/* $src1,$accs */ -/* 35 */ { MNEM, ' ', OP (SRC1), ',', OP (ACCS), 0 }, -/* $sr,$dcr */ -/* 36 */ { MNEM, ' ', OP (SR), ',', OP (DCR), 0 }, -/* */ -/* 37 */ { MNEM, 0 }, -/* $accd */ -/* 38 */ { MNEM, ' ', OP (ACCD), 0 }, -/* $accd,$accs */ -/* 39 */ { MNEM, ' ', OP (ACCD), ',', OP (ACCS), 0 }, -/* $accd,$accs,#$imm1 */ -/* 40 */ { MNEM, ' ', OP (ACCD), ',', OP (ACCS), ',', '#', OP (IMM1), 0 }, -/* $dr,#$hi16 */ -/* 41 */ { MNEM, ' ', OP (DR), ',', '#', OP (HI16), 0 }, -/* $dr,$hi16 */ -/* 42 */ { MNEM, ' ', OP (DR), ',', OP (HI16), 0 }, -/* $dr,#$uimm5 */ -/* 43 */ { MNEM, ' ', OP (DR), ',', '#', OP (UIMM5), 0 }, -/* $dr,$uimm5 */ -/* 44 */ { MNEM, ' ', OP (DR), ',', OP (UIMM5), 0 }, -/* $src1,@$src2 */ -/* 45 */ { MNEM, ' ', OP (SRC1), ',', '@', OP (SRC2), 0 }, -/* $src1,@($src2) */ -/* 46 */ { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ')', 0 }, -/* $src1,@($slo16,$src2) */ -/* 47 */ { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SLO16), ',', OP (SRC2), ')', 0 }, -/* $src1,@($src2,$slo16) */ -/* 48 */ { MNEM, ' ', OP (SRC1), ',', '@', '(', OP (SRC2), ',', OP (SLO16), ')', 0 }, -/* $src1,@+$src2 */ -/* 49 */ { MNEM, ' ', OP (SRC1), ',', '@', '+', OP (SRC2), 0 }, -/* $src1,@-$src2 */ -/* 50 */ { MNEM, ' ', OP (SRC1), ',', '@', '-', OP (SRC2), 0 }, -/* #$uimm4 */ -/* 51 */ { MNEM, ' ', '#', OP (UIMM4), 0 }, -/* $uimm4 */ -/* 52 */ { MNEM, ' ', OP (UIMM4), 0 }, -}; - -#undef MNEM -#undef OP - -static const CGEN_FORMAT format_table[] = -{ -/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(dr SI)(sr SI)(dr SI) */ -/* 0 */ { 16, 16, 0xf0f0 }, -/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16)(slo16 HI)(sr SI)(dr SI) */ -/* 1 */ { 32, 32, 0xf0f00000 }, -/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-uimm16 uimm16)(sr SI)(uimm16 USI)(dr SI) */ -/* 2 */ { 32, 32, 0xf0f00000 }, -/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-uimm16 ulo16)(sr SI)(ulo16 UHI)(dr SI) */ -/* 3 */ { 32, 32, 0xf0f00000 }, -/* (f-op1 #)(f-r1 dr)(f-simm8 simm8)(dr SI)(simm8 SI)(dr SI) */ -/* 4 */ { 16, 16, 0xf000 }, -/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(dr SI)(sr SI)(condbit UBI)(dr SI) */ -/* 5 */ { 16, 16, 0xf0f0 }, -/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 simm16)(simm16 SI)(sr SI)(condbit UBI)(dr SI) */ -/* 6 */ { 32, 32, 0xf0f00000 }, -/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(condbit UBI)(dr SI)(sr SI)(condbit UBI)(dr SI) */ -/* 7 */ { 16, 16, 0xf0f0 }, -/* (f-op1 #)(f-r1 #)(f-disp8 disp8)(condbit UBI)(disp8 VM)(pc USI) */ -/* 8 */ { 16, 16, 0xff00 }, -/* (f-op1 #)(f-r1 #)(f-disp8 disp8) */ -/* 9 */ { 16, 16, 0xff00 }, -/* (f-op1 #)(f-r1 #)(f-disp24 disp24)(condbit UBI)(disp24 VM)(pc USI) */ -/* 10 */ { 32, 32, 0xff000000 }, -/* (f-op1 #)(f-r1 #)(f-disp24 disp24) */ -/* 11 */ { 32, 32, 0xff000000 }, -/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-disp16 disp16)(disp16 VM)(src1 SI)(src2 SI)(pc USI) */ -/* 12 */ { 32, 32, 0xf0f00000 }, -/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(f-disp16 disp16)(disp16 VM)(src2 SI)(pc USI) */ -/* 13 */ { 32, 32, 0xfff00000 }, -/* (f-op1 #)(f-r1 #)(f-disp8 disp8)(disp8 VM)(pc USI)(pc USI)(h-gr-14 SI) */ -/* 14 */ { 16, 16, 0xff00 }, -/* (f-op1 #)(f-r1 #)(f-disp24 disp24)(disp24 VM)(pc USI)(pc USI)(h-gr-14 SI) */ -/* 15 */ { 32, 32, 0xff000000 }, -/* (f-op1 #)(f-r1 #)(f-disp8 disp8)(condbit UBI)(disp8 VM)(pc USI)(pc USI)(h-gr-14 SI) */ -/* 16 */ { 16, 16, 0xff00 }, -/* (f-op1 #)(f-r1 #)(f-disp24 disp24)(condbit UBI)(disp24 VM)(pc USI)(pc USI)(h-gr-14 SI) */ -/* 17 */ { 32, 32, 0xff000000 }, -/* (f-op1 #)(f-r1 #)(f-disp8 disp8)(disp8 VM)(pc USI) */ -/* 18 */ { 16, 16, 0xff00 }, -/* (f-op1 #)(f-r1 #)(f-disp24 disp24)(disp24 VM)(pc USI) */ -/* 19 */ { 32, 32, 0xff000000 }, -/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(condbit UBI) */ -/* 20 */ { 16, 16, 0xf0f0 }, -/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(f-simm16 simm16)(simm16 SI)(src2 SI)(condbit UBI) */ -/* 21 */ { 32, 32, 0xfff00000 }, -/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(f-uimm16 uimm16)(src2 SI)(uimm16 USI)(condbit UBI) */ -/* 22 */ { 32, 32, 0xfff00000 }, -/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 src2)(src2 SI)(condbit UBI) */ -/* 23 */ { 16, 16, 0xfff0 }, -/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 #)(dr SI)(sr SI)(dr SI) */ -/* 24 */ { 32, 32, 0xf0f0ffff }, -/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 sr)(condbit UBI)(sr SI)(pc USI) */ -/* 25 */ { 16, 16, 0xfff0 }, -/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 sr)(pc USI)(sr SI)(pc USI)(h-gr-14 SI) */ -/* 26 */ { 16, 16, 0xfff0 }, -/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 sr)(sr SI)(pc USI) */ -/* 27 */ { 16, 16, 0xfff0 }, -/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr SI)(sr SI)(dr SI) */ -/* 28 */ { 16, 16, 0xf0f0 }, -/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr) */ -/* 29 */ { 16, 16, 0xf0f0 }, -/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16)(h-memory-add-WI-sr-slo16 SI)(slo16 HI)(sr SI)(dr SI) */ -/* 30 */ { 32, 32, 0xf0f00000 }, -/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16) */ -/* 31 */ { 32, 32, 0xf0f00000 }, -/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr QI)(sr SI)(dr SI) */ -/* 32 */ { 16, 16, 0xf0f0 }, -/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16)(h-memory-add-WI-sr-slo16 QI)(slo16 HI)(sr SI)(dr SI) */ -/* 33 */ { 32, 32, 0xf0f00000 }, -/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr HI)(sr SI)(dr SI) */ -/* 34 */ { 16, 16, 0xf0f0 }, -/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 slo16)(h-memory-add-WI-sr-slo16 HI)(slo16 HI)(sr SI)(dr SI) */ -/* 35 */ { 32, 32, 0xf0f00000 }, -/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr SI)(sr SI)(dr SI)(sr SI) */ -/* 36 */ { 16, 16, 0xf0f0 }, -/* (f-op1 #)(f-r1 dr)(f-uimm24 uimm24)(uimm24 VM)(dr SI) */ -/* 37 */ { 32, 32, 0xf0000000 }, -/* (f-op1 #)(f-r1 dr)(f-simm8 simm8)(simm8 SI)(dr SI) */ -/* 38 */ { 16, 16, 0xf000 }, -/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #)(f-simm16 slo16)(slo16 HI)(dr SI) */ -/* 39 */ { 32, 32, 0xf0ff0000 }, -/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(h-memory-sr SI)(sr SI)(dr SI)(h-lock-0 UBI) */ -/* 40 */ { 16, 16, 0xf0f0 }, -/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(accum DI)(src1 SI)(src2 SI)(accum DI) */ -/* 41 */ { 16, 16, 0xf0f0 }, -/* (f-op1 #)(f-r1 src1)(f-acc acc)(f-op23 #)(f-r2 src2)(acc DI)(src1 SI)(src2 SI)(acc DI) */ -/* 42 */ { 16, 16, 0xf070 }, -/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(accum DI) */ -/* 43 */ { 16, 16, 0xf0f0 }, -/* (f-op1 #)(f-r1 src1)(f-acc acc)(f-op23 #)(f-r2 src2)(src1 SI)(src2 SI)(acc DI) */ -/* 44 */ { 16, 16, 0xf070 }, -/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(sr SI)(dr SI) */ -/* 45 */ { 16, 16, 0xf0f0 }, -/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #)(accum DI)(dr SI) */ -/* 46 */ { 16, 16, 0xf0ff }, -/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-accs accs)(f-op3 #)(accs DI)(dr SI) */ -/* 47 */ { 16, 16, 0xf0f3 }, -/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 scr)(scr USI)(dr SI) */ -/* 48 */ { 16, 16, 0xf0f0 }, -/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 #)(accum DI)(src1 SI)(accum DI) */ -/* 49 */ { 16, 16, 0xf0ff }, -/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-accs accs)(f-op3 #)(accs DI)(src1 SI)(accs DI) */ -/* 50 */ { 16, 16, 0xf0f3 }, -/* (f-op1 #)(f-r1 dcr)(f-op2 #)(f-r2 sr)(sr SI)(dcr USI) */ -/* 51 */ { 16, 16, 0xf0f0 }, -/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #) */ -/* 52 */ { 16, 16, 0xffff }, -/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(accum DI)(accum DI) */ -/* 53 */ { 16, 16, 0xffff }, -/* (f-op1 #)(f-accd accd)(f-bits67 #)(f-op2 #)(f-accs #)(f-bit14 #)(f-imm1 #) */ -/* 54 */ { 16, 16, 0xf3ff }, -/* (f-op1 #)(f-accd accd)(f-bits67 #)(f-op2 #)(f-accs accs)(f-bit14 #)(f-imm1 #) */ -/* 55 */ { 16, 16, 0xf3f3 }, -/* (f-op1 #)(f-accd accd)(f-bits67 #)(f-op2 #)(f-accs accs)(f-bit14 #)(f-imm1 imm1)(accs DI)(imm1 USI)(accd DI) */ -/* 56 */ { 16, 16, 0xf3f2 }, -/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(h-bcond-0 VM)(h-bie-0 VM)(h-bpc-0 VM)(h-bsm-0 VM)(condbit UBI)(pc USI)(h-ie-0 VM)(h-sm-0 VM) */ -/* 57 */ { 16, 16, 0xffff }, -/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #)(f-hi16 hi16)(hi16 UHI)(dr SI) */ -/* 58 */ { 32, 32, 0xf0ff0000 }, -/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-simm16 simm16)(simm16 SI)(sr SI)(dr SI) */ -/* 59 */ { 32, 32, 0xf0f00000 }, -/* (f-op1 #)(f-r1 dr)(f-shift-op2 #)(f-uimm5 uimm5)(dr SI)(uimm5 USI)(dr SI) */ -/* 60 */ { 16, 16, 0xf0e0 }, -/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-memory-src2 SI) */ -/* 61 */ { 16, 16, 0xf0f0 }, -/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2) */ -/* 62 */ { 16, 16, 0xf0f0 }, -/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-simm16 slo16)(slo16 HI)(src1 SI)(src2 SI)(h-memory-add-WI-src2-slo16 SI) */ -/* 63 */ { 32, 32, 0xf0f00000 }, -/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-simm16 slo16) */ -/* 64 */ { 32, 32, 0xf0f00000 }, -/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-memory-src2 QI) */ -/* 65 */ { 16, 16, 0xf0f0 }, -/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-simm16 slo16)(slo16 HI)(src1 SI)(src2 SI)(h-memory-add-WI-src2-slo16 QI) */ -/* 66 */ { 32, 32, 0xf0f00000 }, -/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-memory-src2 HI) */ -/* 67 */ { 16, 16, 0xf0f0 }, -/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(f-simm16 slo16)(slo16 HI)(src1 SI)(src2 SI)(h-memory-add-WI-src2-slo16 HI) */ -/* 68 */ { 32, 32, 0xf0f00000 }, -/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-memory-src2 SI)(src2 SI) */ -/* 69 */ { 16, 16, 0xf0f0 }, -/* (f-op1 #)(f-r1 #)(f-op2 #)(f-uimm4 uimm4)(pc USI)(h-cr-0 SI)(uimm4 USI)(pc USI)(h-cr-0 SI)(h-cr-6 SI) */ -/* 70 */ { 16, 16, 0xfff0 }, -/* (f-op1 #)(f-r1 #)(f-op2 #)(f-uimm4 uimm4) */ -/* 71 */ { 16, 16, 0xfff0 }, -/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(h-lock-0 UBI)(src1 SI)(src2 SI)(h-memory-src2 SI)(h-lock-0 UBI) */ -/* 72 */ { 16, 16, 0xf0f0 }, -/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 #) */ -/* 73 */ { 16, 16, 0xf0ff }, -/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 #) */ -/* 74 */ { 16, 16, 0xf0ff }, -/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-uimm16 #)(sr SI)(dr SI) */ -/* 75 */ { 32, 32, 0xf0f0ffff }, -/* (f-op1 #)(f-r1 dr)(f-op2 #)(f-r2 sr)(f-uimm16 #)(condbit UBI)(sr SI)(dr SI) */ -/* 76 */ { 32, 32, 0xf0f0ffff }, -/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(h-accums-0 DI)(h-accums-1 DI)(h-accums-0 DI) */ -/* 77 */ { 16, 16, 0xffff }, -/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(h-accums-1 DI)(src1 SI)(src2 SI)(h-accums-1 DI) */ -/* 78 */ { 16, 16, 0xf0f0 }, -/* (f-op1 #)(f-r1 src1)(f-op2 #)(f-r2 src2)(src1 SI)(src2 SI)(h-accums-1 DI) */ -/* 79 */ { 16, 16, 0xf0f0 }, -/* (f-op1 #)(f-r1 #)(f-op2 #)(f-r2 #)(condbit UBI)(abort-parallel-execution UBI) */ -/* 80 */ { 16, 16, 0xffff }, -}; - -#define A(a) (1 << CGEN_CAT3 (CGEN_INSN,_,a)) -#define SYN(n) (& syntax_table[n]) -#define FMT(n) (& format_table[n]) - /* The instruction table. */ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = @@ -1210,231 +923,297 @@ const CGEN_INSN m32r_cgen_insn_table_entries[MAX_INSNS] = /* add $dr,$sr */ { { 1, 1, 1, 1 }, - "add", "add", SYN (0), FMT (0), 0xa0, + "add", "add", + { MNEM, ' ', OP (DR), ',', OP (SR), 0 }, + { 16, 16, 0xf0f0 }, 0xa0, & fmt_0_add_ops[0], { CGEN_INSN_NBOOL_ATTRS, 0|A(PARALLEL), { (1<. */ -#define CGEN_SYM(s) CGEN_CAT3 (m32r,_cgen_,s) +#define CGEN_SYM(s) CONCAT3 (m32r,_cgen_,s) /* Selected cpu families. */ #define HAVE_CPU_M32R @@ -89,11 +89,7 @@ typedef enum cgen_operand_type { /* end-sanitize-m32rx */ , M32R_OPERAND_HI16, M32R_OPERAND_SLO16, M32R_OPERAND_ULO16, M32R_OPERAND_UIMM24 , M32R_OPERAND_DISP8, M32R_OPERAND_DISP16, M32R_OPERAND_DISP24, M32R_OPERAND_CONDBIT - , M32R_OPERAND_ACCUM -/* start-sanitize-m32rx */ - , M32R_OPERAND_ABORT_PARALLEL_EXECUTION -/* end-sanitize-m32rx */ - , M32R_OPERAND_MAX + , M32R_OPERAND_ACCUM, M32R_OPERAND_MAX } CGEN_OPERAND_TYPE; /* Non-boolean attributes. */