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* simops.c (signed multiply instructions): Cast input operands to

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signed32 before casting them to signed64 so that the sign bit
        is propagated properly.
This commit is contained in:
Jeff Law 1998-02-25 08:58:23 +00:00
parent c248113005
commit 097e6924c2
2 changed files with 16 additions and 10 deletions
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6
sim/mn10300/ChangeLog
View file

@ -1,3 +1,9 @@
Wed Feb 25 01:59:29 1998 Jeffrey A Law (law@cygnus.com)
* simops.c (signed multiply instructions): Cast input operands to
signed32 before casting them to signed64 so that the sign bit
is propagated properly.
Mon Feb 23 20:23:19 1998 Mark Alexander <marka@cygnus.com>
* Makefile.in: Last change was bad. Define NL_TARGET

20
sim/mn10300/simops.c
View file

@ -1433,8 +1433,8 @@ void OP_F240 (insn, extension)
unsigned long long temp;
int n, z;
temp = ((signed64)State.regs[REG_D0 + REG0 (insn)]
* (signed64)State.regs[REG_D0 + REG1 (insn)]);
temp = ((signed64)(signed32)State.regs[REG_D0 + REG0 (insn)]
* (signed64)(signed32)State.regs[REG_D0 + REG1 (insn)]);
State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + REG0 (insn)] == 0);
@ -3061,8 +3061,8 @@ void OP_F600 (insn, extension)
unsigned long long temp;
int n, z;
temp = ((signed64)State.regs[REG_D0 + REG0 (insn)]
* (signed64)State.regs[REG_D0 + REG1 (insn)]);
temp = ((signed64)(signed32)State.regs[REG_D0 + REG0 (insn)]
* (signed64)(signed32)State.regs[REG_D0 + REG1 (insn)]);
State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + REG0 (insn)] == 0);
@ -3078,8 +3078,8 @@ void OP_F90000 (insn, extension)
unsigned long long temp;
int n, z;
temp = ((signed64)State.regs[REG_D0 + REG0_8 (insn)]
* (signed64)SEXT8 (insn & 0xff));
temp = ((signed64)(signed32)State.regs[REG_D0 + REG0_8 (insn)]
* (signed64)(signed32)SEXT8 (insn & 0xff));
State.regs[REG_D0 + REG0_8 (insn)] = temp & 0xffffffff;
State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
@ -3095,8 +3095,8 @@ void OP_FB000000 (insn, extension)
unsigned long long temp;
int n, z;
temp = ((signed64)State.regs[REG_D0 + REG0_16 (insn)]
* (signed64)SEXT16 (insn & 0xffff));
temp = ((signed64)(signed32)State.regs[REG_D0 + REG0_16 (insn)]
* (signed64)(signed32)SEXT16 (insn & 0xffff));
State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff;
State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
@ -3112,8 +3112,8 @@ void OP_FD000000 (insn, extension)
unsigned long long temp;
int n, z;
temp = ((signed64)State.regs[REG_D0 + REG0_16 (insn)]
* (signed64)(((insn & 0xffff) << 16) + extension));
temp = ((signed64)(signed32)State.regs[REG_D0 + REG0_16 (insn)]
* (signed64)(signed32)(((insn & 0xffff) << 16) + extension));
State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff;
State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);