* dv-pal.c (hw_pal_countdown, hw_pal_countdown_value,
hw_pal_timer, hw_pal_timer_value): Define. (hw_pal_io_read_buffer, hw_pal_io_write_buffer): Add timer support (do_counter_event, do_counter_read, do_counter_value, do_counter_write): new functions. * hw-tree.c (hw_printf): Send tree dump to stderr, same as other trace output. * hw-base.c (hw_create): Stop searching for a device when one is found.
This commit is contained in:
Andrew Cagney
parent
d89fa2d80a
commit
05d7918e53
3 changed files with 277 additions and 63 deletions
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@ -1,3 +1,19 @@
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Wed Mar 25 09:18:34 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* dv-pal.c (hw_pal_countdown, hw_pal_countdown_value,
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hw_pal_timer, hw_pal_timer_value): Define.
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(hw_pal_io_read_buffer, hw_pal_io_write_buffer): Add timer support
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(do_counter_event, do_counter_read, do_counter_value,
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do_counter_write): new functions.
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Tue Mar 24 12:24:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* hw-tree.c (hw_printf): Send tree dump to stderr, same as other
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trace output.
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* hw-base.c (hw_create): Stop searching for a device when one is
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found.
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Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
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* configure: Regenerated to track ../common/aclocal.m4 changes.
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@ -54,46 +54,70 @@
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to gain access to all the things the firmware needs (but the OS
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doesn't).
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The pal contains the following registers. Except for the interrupt
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level register, each of the below is 8 bytes in size and must be
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accessed using correct alignment. For 16 and 32 bit accesses the
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bytes not directed to the register are ignored:
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|0 reset register (write)
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|4 processor id register (read)
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|8 interrupt port (write)
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|9 interrupt level (write)
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|12 processor count register (read)
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|16 tty input fifo register (read)
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|20 tty input status register (read)
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|24 tty output fifo register (write)
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|28 tty output status register (read)
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The pal contains the following registers:
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Reset register (write) halts the simulator exiting with the
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value written.
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|0 reset register (write, 8bit)
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|4 processor id register (read, 8bit)
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|8 interrupt register (8 - port, 9 - level) (write, 16bit)
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|12 processor count register (read, 8bit)
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|16 tty input fifo register (read, 8bit)
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|20 tty input status register (read, 8bit)
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|24 tty output fifo register (write, 8bit)
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|28 tty output status register (read, 8bit)
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|32 countdown register (read/write, 32bit, big-endian)
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|36 countdown value register (read, 32bit, big-endian)
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|40 timer register (read/write, 32bit, big-endian)
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|44 timer value register (read, 32bit, big-endian)
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RESET (write): halts the simulator. The value written to the
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register is used as an exit status.
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Processor id register (read) returns the processor number (0
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.. N-1) of the processor performing the read.
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PROCESSOR ID (read): returns the processor identifier (0 .. N-1) of
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the processor performing the read.
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The interrupt registers should be accessed as a pair (using a 16 or
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32 bit store). The low byte specifies the interrupt port while the
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high byte specifies the level to drive that port at. By
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INTERRUPT (write): This register must be written using a two byte
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store. The low byte specifies a port and the upper byte specifies
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the a level. LEVEL is driven on the specified port. By
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convention, the pal's interrupt ports (int0, int1, ...) are wired
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up to the corresponding processor's level sensative external
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interrupt pin. Eg: A two byte write to address 8 of 0x0102
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(big-endian) will result in processor 2's external interrupt pin to
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be asserted.
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(big-endian) will result in processor 2's external interrupt pin
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being asserted.
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Processor count register (read) returns the total number of
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processors active in the current simulation.
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PROCESSOR COUNT (read): returns the total number of processors
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active in the current simulation.
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TTY input fifo register (read), if the TTY input status register
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indicates a character is available by being nonzero, returns the
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next available character from the pal's tty input port.
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TTY INPUT FIFO (read): if the TTY input status register indicates a
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character is available by being nonzero, returns the next available
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character from the pal's tty input port.
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Similarly, the TTY output fifo register (write), if the TTY output
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status register indicates the output fifo is not full by being
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nonzero, outputs the character written to the tty's output port.
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TTY OUTPUT FIFO (write): if the TTY output status register
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indicates the output fifo is not full by being nonzero, outputs the
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character written to the tty's output port.
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COUNDOWN (read/write): The countdown registers provide a
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non-repeating timed interrupt source. Writing a 32 bit big-endian
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zero value to this register clears the countdown timer. Writing a
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non-zero 32 bit big-endian value to this register sets the
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countdown timer to expire in VALUE ticks (ticks is target
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dependant). Reading the countdown register returns the last value
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writen.
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COUNTDOWN VALUE (read): Reading this 32 bit big-endian register
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returns the number of ticks remaining until the countdown timer
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expires.
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TIMER (read/write): The timer registers provide a periodic timed
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interrupt source. Writing a 32 bit big-endian zero value to this
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register clears the periodic timer. Writing a 32 bit non-zero
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value to this register sets the periodic timer to triger every
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VALUE ticks (ticks is target dependant). Reading the timer
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register returns the last value written.
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TIMER VALUE (read): Reading this 32 bit big-endian register returns
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the number of ticks until the next periodic interrupt.
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PROPERTIES
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@ -102,7 +126,7 @@
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reg = <address> <size> (required)
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Specify the address (within the parent bus) that this device is to
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live.
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be located.
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PORTS
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@ -114,6 +138,22 @@
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interrupt-level register pair.
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countdown
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Driven whenever the countdown counter reaches zero.
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timer
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Driven whenever the timer counter reaches zero.
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BUGS
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At present the common simulator framework does not support input
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polling.
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*/
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@ -126,7 +166,11 @@ enum {
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hw_pal_read_status = 0x14,
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hw_pal_write_fifo = 0x18,
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hw_pal_write_status = 0x1a,
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hw_pal_address_mask = 0x1f,
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hw_pal_countdown = 0x20,
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hw_pal_countdown_value = 0x24,
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hw_pal_timer = 0x28,
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hw_pal_timer_value = 0x2c,
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hw_pal_address_mask = 0x2f,
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};
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@ -135,12 +179,118 @@ typedef struct _hw_pal_console_buffer {
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int status;
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} hw_pal_console_buffer;
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typedef struct _hw_pal_counter {
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hw_event *handler;
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signed64 start;
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unsigned32 delta;
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int periodic_p;
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} hw_pal_counter;
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typedef struct _hw_pal_device {
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hw_pal_console_buffer input;
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hw_pal_console_buffer output;
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hw_pal_counter countdown;
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hw_pal_counter timer;
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struct hw *disk;
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} hw_pal_device;
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enum {
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COUNTDOWN_PORT,
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TIMER_PORT,
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INT_PORT,
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};
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static const struct hw_port_descriptor hw_pal_ports[] = {
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{ "countdown", COUNTDOWN_PORT, 0, output_port, },
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{ "timer", TIMER_PORT, 0, output_port, },
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{ "int", INT_PORT, MAX_NR_PROCESSORS, output_port, },
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{ NULL }
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};
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/* countdown and simple timer */
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static void
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do_counter_event (struct hw *me,
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void *data)
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{
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hw_pal_counter *counter = (hw_pal_counter *) data;
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if (counter->periodic_p)
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{
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HW_TRACE ((me, "timer expired"));
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counter->start = hw_event_queue_time (me);
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hw_port_event (me, TIMER_PORT, 1, NULL, NULL_CIA);
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hw_event_queue_schedule (me, counter->delta, do_counter_event, counter);
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}
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else
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{
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HW_TRACE ((me, "countdown expired"));
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counter->delta = 0;
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hw_port_event (me, COUNTDOWN_PORT, 1, NULL, NULL_CIA);
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}
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}
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static void
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do_counter_read (struct hw *me,
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hw_pal_device *pal,
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const char *reg,
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hw_pal_counter *counter,
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unsigned32 *word,
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unsigned nr_bytes)
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{
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unsigned32 val;
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if (nr_bytes != 4)
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hw_abort (me, "%s - bad read size must be 4 bytes", reg);
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val = counter->delta;
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HW_TRACE ((me, "read - %s %ld", reg, (long) val));
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*word = H2BE_4 (val);
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}
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static void
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do_counter_value (struct hw *me,
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hw_pal_device *pal,
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const char *reg,
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hw_pal_counter *counter,
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unsigned32 *word,
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unsigned nr_bytes)
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{
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unsigned32 val;
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if (nr_bytes != 4)
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hw_abort (me, "%s - bad read size must be 4 bytes", reg);
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if (counter->delta != 0)
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val = (counter->start + counter->delta
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- hw_event_queue_time (me));
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else
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val = 0;
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HW_TRACE ((me, "read - %s %ld", reg, (long) val));
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*word = H2BE_4 (val);
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}
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static void
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do_counter_write (struct hw *me,
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hw_pal_device *pal,
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const char *reg,
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hw_pal_counter *counter,
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const unsigned32 *word,
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unsigned nr_bytes)
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{
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if (nr_bytes != 4)
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hw_abort (me, "%s - bad write size must be 4 bytes", reg);
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if (counter->handler != NULL)
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{
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hw_event_queue_deschedule (me, counter->handler);
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counter->handler = NULL;
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}
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counter->delta = BE2H_4 (*word);
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counter->start = hw_event_queue_time (me);
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HW_TRACE ((me, "write - %s %ld", reg, (long) counter->delta));
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if (counter->delta > 0)
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hw_event_queue_schedule (me, counter->delta, do_counter_event, counter);
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}
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/* check the console for an available character */
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static void
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@ -168,6 +318,7 @@ scan_hw_pal (struct hw *me)
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}
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/* write the character to the hw_pal */
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static void
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write_hw_pal (struct hw *me,
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char val)
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@ -179,6 +330,8 @@ write_hw_pal (struct hw *me,
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}
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/* Reads/writes */
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static unsigned
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hw_pal_io_read_buffer (struct hw *me,
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void *dest,
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@ -189,44 +342,71 @@ hw_pal_io_read_buffer (struct hw *me,
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sim_cia cia)
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{
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hw_pal_device *hw_pal = (hw_pal_device *) hw_data (me);
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unsigned_1 val;
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unsigned_1 *byte = (unsigned_1 *) dest;
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memset (dest, 0, nr_bytes);
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switch (addr & hw_pal_address_mask)
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{
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case hw_pal_cpu_nr_register:
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#ifdef CPU_INDEX
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val = CPU_INDEX (cpu);
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*byte = CPU_INDEX (cpu);
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#else
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val = 0;
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*byte = 0;
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#endif
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HW_TRACE ((me, "read - cpu-nr %d\n", val));
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HW_TRACE ((me, "read - cpu-nr %d\n", *byte));
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break;
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case hw_pal_nr_cpu_register:
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val = hw_tree_find_integer_property (me, "/openprom/options/smp");
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HW_TRACE ((me, "read - nr-cpu %d\n", val));
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*byte = hw_tree_find_integer_property (me, "/openprom/options/smp");
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HW_TRACE ((me, "read - nr-cpu %d\n", *byte));
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break;
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case hw_pal_read_fifo:
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val = hw_pal->input.buffer;
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HW_TRACE ((me, "read - input-fifo %d\n", val));
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*byte = hw_pal->input.buffer;
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HW_TRACE ((me, "read - input-fifo %d\n", *byte));
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break;
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case hw_pal_read_status:
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scan_hw_pal (me);
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val = hw_pal->input.status;
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HW_TRACE ((me, "read - input-status %d\n", val));
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*byte = hw_pal->input.status;
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HW_TRACE ((me, "read - input-status %d\n", *byte));
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break;
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case hw_pal_write_fifo:
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val = hw_pal->output.buffer;
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HW_TRACE ((me, "read - output-fifo %d\n", val));
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*byte = hw_pal->output.buffer;
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HW_TRACE ((me, "read - output-fifo %d\n", *byte));
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break;
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case hw_pal_write_status:
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val = hw_pal->output.status;
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HW_TRACE ((me, "read - output-status %d\n", val));
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*byte = hw_pal->output.status;
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HW_TRACE ((me, "read - output-status %d\n", *byte));
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break;
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case hw_pal_countdown:
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do_counter_read (me, hw_pal, "countdown",
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&hw_pal->countdown, dest, nr_bytes);
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break;
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case hw_pal_countdown_value:
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do_counter_value (me, hw_pal, "countdown-value",
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&hw_pal->countdown, dest, nr_bytes);
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break;
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case hw_pal_timer:
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do_counter_read (me, hw_pal, "timer",
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&hw_pal->timer, dest, nr_bytes);
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break;
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case hw_pal_timer_value:
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do_counter_value (me, hw_pal, "timer-value",
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&hw_pal->timer, dest, nr_bytes);
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break;
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default:
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val = 0;
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HW_TRACE ((me, "read - ???\n"));
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break;
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}
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memset (dest, 0, nr_bytes);
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*(unsigned_1*)dest = val;
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return nr_bytes;
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}
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@ -241,35 +421,52 @@ hw_pal_io_write_buffer (struct hw *me,
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sim_cia cia)
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{
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hw_pal_device *hw_pal = (hw_pal_device*) hw_data (me);
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unsigned_1 *byte = (unsigned_1*) source;
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unsigned_1 *byte = (unsigned_1 *) source;
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switch (addr & hw_pal_address_mask)
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{
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case hw_pal_reset_register:
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sim_engine_halt (NULL, cpu, NULL, cia, sim_exited, byte[0]);
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sim_engine_halt (hw_system (me), cpu, NULL, cia, sim_exited, byte[0]);
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break;
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case hw_pal_int_register:
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hw_port_event (me,
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byte[0], /*port*/
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INT_PORT + byte[0], /*port*/
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(nr_bytes > 1 ? byte[1] : 0), /* val */
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cpu, cia);
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break;
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|
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case hw_pal_read_fifo:
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hw_pal->input.buffer = byte[0];
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HW_TRACE ((me, "write - input-fifo %d\n", byte[0]));
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break;
|
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|
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case hw_pal_read_status:
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hw_pal->input.status = byte[0];
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HW_TRACE ((me, "write - input-status %d\n", byte[0]));
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break;
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case hw_pal_write_fifo:
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write_hw_pal (me, byte[0]);
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HW_TRACE ((me, "write - output-fifo %d\n", byte[0]));
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break;
|
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|
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case hw_pal_write_status:
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hw_pal->output.status = byte[0];
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HW_TRACE ((me, "write - output-status %d\n", byte[0]));
|
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break;
|
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|
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case hw_pal_countdown:
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do_counter_write (me, hw_pal, "countdown",
|
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&hw_pal->countdown, source, nr_bytes);
|
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break;
|
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|
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case hw_pal_timer:
|
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do_counter_write (me, hw_pal, "timer",
|
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&hw_pal->timer, source, nr_bytes);
|
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break;
|
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|
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}
|
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return nr_bytes;
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}
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|
|
@ -335,11 +532,6 @@ hw_pal_create_instance (struct hw *me,
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}
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#endif
|
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|
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static const struct hw_port_descriptor hw_pal_ports[] = {
|
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{ "int", 0, MAX_NR_PROCESSORS },
|
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{ NULL }
|
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};
|
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|
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|
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static void
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hw_pal_attach_address (struct hw *me,
|
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|
|
@ -386,7 +578,10 @@ hw_pal_finish (struct hw *hw)
|
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set_hw_io_write_buffer (hw, hw_pal_io_write_buffer);
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set_hw_ports (hw, hw_pal_ports);
|
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/* attach ourselves */
|
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do_hw_attach_regs (me);
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do_hw_attach_regs (hw);
|
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|
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/* tag the periodic timer */
|
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hw_pal->timer.periodic_p = 1;
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}
|
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|
||||
|
||||
|
|
|
|||
|
|
@ -831,10 +831,13 @@ hw_tree_parse (struct hw *current,
|
|||
char *dest_hw_name = split_value (&spec);
|
||||
struct hw *dest;
|
||||
/* find my name */
|
||||
my_port = hw_port_decode (current, my_port_name,
|
||||
output_port);
|
||||
if (!hw_finished_p (current))
|
||||
hw_finish (current);
|
||||
my_port = hw_port_decode (current, my_port_name, output_port);
|
||||
/* find the dest device and port */
|
||||
dest = split_fill_path(current, dest_hw_name, &dest_spec);
|
||||
dest = split_fill_path (current, dest_hw_name, &dest_spec);
|
||||
if (!hw_finished_p (dest))
|
||||
hw_finish (dest);
|
||||
dest_port = hw_port_decode (dest, dest_port_name,
|
||||
input_port);
|
||||
/* connect the two */
|
||||
|
|
@ -981,7 +984,7 @@ hw_printf (struct hw *me,
|
|||
{
|
||||
va_list ap;
|
||||
va_start (ap, fmt);
|
||||
sim_io_vprintf (hw_system (me), fmt, ap);
|
||||
sim_io_evprintf (hw_system (me), fmt, ap);
|
||||
va_end (ap);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue