Update the machine code decode algorithm using hash table.
This commit is contained in:
M R Swami Reddy
parent
fcfb8b02aa
commit
052d9a542f
1 changed files with 579 additions and 451 deletions
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@ -14,8 +14,8 @@
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program. If not, see <http://www.gnu.org/licenses/>. */
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#include <signal.h>
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#include "sysdep.h"
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@ -28,8 +28,6 @@
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#include "gdb/signals.h"
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#include "opcode/cr16.h"
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enum _leftright { LEFT_FIRST, RIGHT_FIRST };
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static char *myname;
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static SIM_OPEN_KIND sim_kind;
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int cr16_debug;
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@ -52,8 +50,10 @@ asection *text;
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bfd_vma text_start;
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bfd_vma text_end;
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static void get_operands PARAMS ((operand_desc *s, uint64 mcode, int isize));
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static void do_run PARAMS ((inst *ins, uint64 mc));
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static long hash PARAMS ((uint64 linsn, int));
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static struct hash_entry *lookup_hash PARAMS ((uint64 ins, int size));
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static void get_operands PARAMS ((operand_desc *s, uint64 mcode, int isize, int nops));
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static int do_run PARAMS ((uint64 mc));
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static char *add_commas PARAMS ((char *buf, int sizeof_buf, unsigned long value));
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extern void sim_set_profile PARAMS ((int n));
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extern void sim_set_profile_size PARAMS ((int n));
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@ -77,9 +77,72 @@ extern int (*deprecated_ui_loop_hook) PARAMS ((int signo));
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#define INLINE
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#endif
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#endif
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#define MAX_HASH 16
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struct hash_entry
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{
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struct hash_entry *next;
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uint32 opcode;
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uint32 mask;
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int format;
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int size;
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struct simops *ops;
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};
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struct hash_entry hash_table[MAX_HASH+1];
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INLINE static long
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hash(unsigned long long insn, int format)
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{
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unsigned int i = 4, tmp;
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if (format)
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{
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while ((insn >> i) != 0) i +=4;
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return ((insn >> (i-4)) & 0xf); /* Use last 4 bits as hask key. */
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}
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return ((insn & 0xF)); /* Use last 4 bits as hask key. */
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}
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INLINE static struct hash_entry *
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lookup_hash (uint64 ins, int size)
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{
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uint32 mask;
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struct hash_entry *h;
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h = &hash_table[hash(ins,1)];
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mask = (((1 << (32 - h->mask)) -1) << h->mask);
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/* Adjuest mask for branch with 2 word instructions. */
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if ((h->ops->mnimonic != NULL) &&
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((streq(h->ops->mnimonic,"b") && h->size == 2)))
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mask = 0xff0f0000;
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while ((ins & mask) != (BIN(h->opcode, h->mask)))
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{
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if (h->next == NULL)
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{
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State.exception = SIGILL;
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State.pc_changed = 1; /* Don't increment the PC. */
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return NULL;
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}
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h = h->next;
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mask = (((1 << (32 - h->mask)) -1) << h->mask);
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/* Adjuest mask for branch with 2 word instructions. */
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if ((streq(h->ops->mnimonic,"b")) && h->size == 2)
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mask = 0xff0f0000;
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}
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return (h);
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}
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INLINE static void
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get_operands (operand_desc *s, uint64 ins, int isize)
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get_operands (operand_desc *s, uint64 ins, int isize, int nops)
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{
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uint32 i, opn = 0, start_bit = 0, op_type = 0;
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int32 op_size = 0, mask = 0;
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@ -87,13 +150,11 @@ get_operands (operand_desc *s, uint64 ins, int isize)
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if (isize == 1) /* Trunkcate the extra 16 bits of INS. */
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ins = ins >> 16;
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for (i=0; i < 3; ++i,++opn)
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for (i=0; i < 4; ++i,++opn)
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{
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if ((s[opn].op_type == dummy) || (s[opn].op_type > cr16_num_optab))
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break;
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else
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op_type = s[opn].op_type;
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if (s[opn].op_type == dummy) break;
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op_type = s[opn].op_type;
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start_bit = s[opn].shift;
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op_size = cr16_optab[op_type].bit_size;
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@ -116,10 +177,16 @@ get_operands (operand_desc *s, uint64 ins, int isize)
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break;
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case uimm3: case uimm3_1: case uimm4_1:
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if (isize == 1)
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OP[i] = ((ins >> 4) & ((1 << op_size) -1));
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else
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OP[i] = ((ins >> (32 - start_bit)) & ((1 << op_size) -1));
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switch (isize)
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{
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case 1:
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OP[i] = ((ins >> 4) & ((1 << op_size) -1)); break;
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case 2:
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OP[i] = ((ins >> (32 - start_bit)) & ((1 << op_size) -1));break;
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default: /* for case 3. */
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OP[i] = ((ins >> (16 + start_bit)) & ((1 << op_size) -1)); break;
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break;
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}
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break;
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case uimm4:
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@ -280,18 +347,18 @@ get_operands (operand_desc *s, uint64 ins, int isize)
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default: break;
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}
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/* For ESC on uimm4_1 operand */
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/* For ESC on uimm4_1 operand. */
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if (op_type == uimm4_1)
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if (OP[i] == 9)
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OP[i] = -1;
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/* For increment by 1. */
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if ((op_type == pregr) || (op_type == pregrp))
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OP[i] += 1;
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}
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/* FIXME: for tracing, update values that need to be updated each
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instruction decode cycle */
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#if 0 // DEBUG
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(*cr16_callback->printf_filtered) (cr16_callback, "OP0=0x%X\t,OP1=0x%X\t,OP2=0x%X\t,OP3=0X%X\n",OP[0],OP[1],OP[2],OP[3]);
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#endif
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State.trace.psw = PSR;
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}
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bfd_vma
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@ -316,35 +383,44 @@ decode_pc ()
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static void
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do_run(inst *instruction, uint64 mcode)
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static int
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do_run(uint64 mcode)
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{
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struct simops *s= Simops;
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struct hash_entry *h;
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char func[12]="\0";
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uint8 *iaddr;
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#ifdef DEBUG
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if ((cr16_debug & DEBUG_INSTRUCTION) != 0)
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(*cr16_callback->printf_filtered) (cr16_callback, "do_long 0x%x\n", instruction);
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(*cr16_callback->printf_filtered) (cr16_callback, "do_long 0x%x\n", mcode);
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#endif
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/* Re-set OP list */
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h = lookup_hash(mcode, 1);
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if ((h == NULL) || (h->opcode == NULL)) return 0;
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if (h->size == 3)
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{
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iaddr = imem_addr ((uint32)PC + 2);
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mcode = (mcode << 16) | get_longword( iaddr );
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}
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/* Re-set OP list. */
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OP[0] = OP[1] = OP[2] = OP[3] = sign_flag = 0;
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/* for push/pop/pushrtn with RA instructions */
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if ((INST_HAS_REG_LIST) && (mcode & 0x800000))
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OP[2] = 1; /* Set 1 for RA operand */
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/* for push/pop/pushrtn with RA instructions. */
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if ((h->format & REG_LIST) && (mcode & 0x800000))
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OP[2] = 1; /* Set 1 for RA operand. */
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get_operands (&instruction->operands, mcode, instruction->size);
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/* numops == 0 means, no operands. */
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if (((h->ops) != NULL) && (((h->ops)->numops) != 0))
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get_operands ((h->ops)->operands, mcode, h->size, (h->ops)->numops);
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State.ins_type = instruction->flags;
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//ins_type_counters[ (int)State.ins_type ]++;
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sprintf(func,"OP_%X_%X",instruction->match,(32 - instruction->match_bits));
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/* Check for appropriate opcode function */
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for ( ;s->opcode!=0;s++)
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{
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if (strcmp(s->fname,func) == 0)
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break;
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}
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(s->func)();
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//State.ins_type = h->flags;
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(h->ops->func)();
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return h->size;
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}
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static char *
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@ -600,10 +676,8 @@ sim_cr16_translate_imap_addr (unsigned long offset,
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}
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unsigned long
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sim_cr16_translate_addr (unsigned long memaddr,
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int nr_bytes,
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unsigned long *targ_addr,
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void *regcache,
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sim_cr16_translate_addr (unsigned long memaddr, int nr_bytes,
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unsigned long *targ_addr, void *regcache,
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unsigned long (*dmap_register) (void *regcache,
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int reg_nr),
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unsigned long (*imap_register) (void *regcache,
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@ -828,11 +902,11 @@ sim_read (sd, addr, buffer, size)
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return xfer_mem( addr, buffer, size, 0);
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}
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SIM_DESC
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sim_open (SIM_OPEN_KIND kind, struct host_callback_struct *callback, struct bfd *abfd, char **argv)
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{
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struct simops *s;
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struct hash_entry *h;
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static int init_p = 0;
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char **p;
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@ -860,6 +934,112 @@ sim_open (SIM_OPEN_KIND kind, struct host_callback_struct *callback, struct bfd
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}
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#endif
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/* put all the opcodes in the hash table. */
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if (!init_p++)
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{
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for (s = Simops; s->func; s++)
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{
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switch(32 - s->mask)
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{
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case 0x4:
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h = &hash_table[hash(s->opcode, 0)];
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break;
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case 0x7:
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if (((s->opcode << 1) >> 4) != 0)
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h = &hash_table[hash((s->opcode << 1) >> 4, 0)];
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else
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h = &hash_table[hash((s->opcode << 1), 0)];
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break;
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case 0x8:
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if ((s->opcode >> 4) != 0)
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h = &hash_table[hash(s->opcode >> 4, 0)];
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else
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h = &hash_table[hash(s->opcode, 0)];
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break;
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case 0x9:
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if (((s->opcode >> 1) >> 4) != 0)
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h = &hash_table[hash((s->opcode >>1) >> 4, 0)];
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else
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h = &hash_table[hash((s->opcode >> 1), 0)];
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break;
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case 0xa:
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if ((s->opcode >> 8) != 0)
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h = &hash_table[hash(s->opcode >> 8, 0)];
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else if ((s->opcode >> 4) != 0)
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h = &hash_table[hash(s->opcode >> 4, 0)];
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else
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h = &hash_table[hash(s->opcode, 0)];
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break;
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case 0xc:
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if ((s->opcode >> 8) != 0)
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h = &hash_table[hash(s->opcode >> 8, 0)];
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else if ((s->opcode >> 4) != 0)
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h = &hash_table[hash(s->opcode >> 4, 0)];
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else
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h = &hash_table[hash(s->opcode, 0)];
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break;
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case 0xd:
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if (((s->opcode >> 1) >> 8) != 0)
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h = &hash_table[hash((s->opcode >>1) >> 8, 0)];
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else if (((s->opcode >> 1) >> 4) != 0)
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h = &hash_table[hash((s->opcode >>1) >> 4, 0)];
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else
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h = &hash_table[hash((s->opcode >>1), 0)];
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break;
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case 0x10:
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if ((s->opcode >> 0xc) != 0)
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h = &hash_table[hash(s->opcode >> 12, 0)];
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else if ((s->opcode >> 8) != 0)
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h = &hash_table[hash(s->opcode >> 8, 0)];
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else if ((s->opcode >> 4) != 0)
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h = &hash_table[hash(s->opcode >> 4, 0)];
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else
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h = &hash_table[hash(s->opcode, 0)];
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break;
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case 0x14:
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if ((s->opcode >> 16) != 0)
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h = &hash_table[hash(s->opcode >> 16, 0)];
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else if ((s->opcode >> 12) != 0)
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h = &hash_table[hash(s->opcode >> 12, 0)];
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else if ((s->opcode >> 8) != 0)
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h = &hash_table[hash(s->opcode >> 8, 0)];
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else if ((s->opcode >> 4) != 0)
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h = &hash_table[hash(s->opcode >> 4, 0)];
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else
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h = &hash_table[hash(s->opcode, 0)];
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break;
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default:
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break;
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}
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/* go to the last entry in the chain. */
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while (h->next)
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h = h->next;
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if (h->ops)
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{
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h->next = (struct hash_entry *) calloc(1,sizeof(struct hash_entry));
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if (!h->next)
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perror ("malloc failure");
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h = h->next;
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}
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h->ops = s;
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h->mask = s->mask;
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h->opcode = s->opcode;
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h->format = s->format;
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h->size = s->size;
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}
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}
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/* reset the processor state */
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if (!State.mem.data[0])
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sim_size (1);
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@ -969,7 +1149,7 @@ sim_stop (sd)
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void
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sim_resume (SIM_DESC sd, int step, int siggnal)
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{
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uint32 mask = 0, ins_found = 0;
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uint32 curr_ins_size = 0;
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uint64 mcode = 0;
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uint8 *iaddr;
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@ -1009,7 +1189,6 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
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do
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{
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iaddr = imem_addr ((uint32)PC);
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ins_found = 0;
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if (iaddr == State.mem.fault)
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{
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State.exception = SIGBUS;
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@ -1020,77 +1199,26 @@ sim_resume (SIM_DESC sd, int step, int siggnal)
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State.pc_changed = 0;
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/* Start searching from end of instruction table. */
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const inst *instruction = &cr16_instruction[NUMOPCODES - 2];
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/* Loop over instruction table until a full match is found. */
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while (instruction >= cr16_instruction)
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{
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mask = (((1 << (32 - instruction->match_bits)) -1) <<
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instruction->match_bits);
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/* Adjuest mask for branch with 2 word instructions. */
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if ((IS_INSN_MNEMONIC("b") && instruction->size == 2))
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mask = 0xff0f0000;
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if ((mcode & mask) == (BIN(instruction->match, instruction->match_bits)))
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{
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ins_found = 1;
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break;
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}
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else
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instruction--;
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}
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curr_ins_size = do_run(mcode);
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#if CR16_DEBUG
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(*cr16_callback->printf_filtered) (cr16_callback, "INS: PC=0x%X, mcode=0x%X\n",PC,mcode);
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#endif
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if ((mcode == 0x0L) /*|| (!ins_found )*/)
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if (!State.pc_changed)
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{
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if (curr_ins_size == 0)
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{
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State.exception = SIG_CR16_EXIT; /* exit trap */
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break;
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}
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/* Check if the ins_found is '0', then set illigel instruction trap */
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if ( !ins_found )
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State.exception = SIGILL;
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else
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{
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/* For 3 word instructions only */
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if (instruction->size == 3)
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{
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iaddr = imem_addr ((uint32)PC + 2);
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mcode = (mcode << 16) | get_longword( iaddr );
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}
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do_run(instruction, mcode);
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}
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/* If the PC of the current instruction matches RPT_E then
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schedule a branch to the loop start. If one of those
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instructions happens to be a branch, than that instruction
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will be ignored */
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if (!State.pc_changed)
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{
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switch (instruction->size)
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{
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case 1:
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SET_PC (PC + 2); /* For 1 word instructions */
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break;
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case 2:
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SET_PC (PC + 4); /* For 2 word instructions */
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break;
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case 3:
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SET_PC (PC + 6); /* For 3 word instructions */
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break;
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default: break;
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}
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SET_PC (PC + (curr_ins_size * 2)); /* For word instructions. */
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}
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#if 0
|
||||
/* Check for a breakpoint trap on this instruction. This
|
||||
overrides any pending branches or loops */
|
||||
#if 0
|
||||
if (PSR_DB && PC == DBS)
|
||||
{
|
||||
SET_BPC (PC);
|
||||
|
|
|
|||
Loading…
Reference in a new issue