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[AArch64] Match instruction "STP with base register" in prologue

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Nowadays, we only match pre-indexed STP in prologue.  Due to the change
in gcc, https://gcc.gnu.org/ml/gcc-patches/2016-07/msg01933.html, it
may generate "STP with base register" in prologue, which GDB doesn't
handle.  That is to say, previously GCC generates prologue like this,

 sub sp, sp, #490
 stp x29, x30, [sp, #-96]!
 mov x29, sp

with the gcc patch above, GCC generates prologue like like this,

 sub sp, sp, #4f0
 stp x29, x30, [sp]
 mov x29, sp

This patch is to teach GDB to recognize this instruction in prologue
analysis.

gdb:

2016-08-19  Yao Qi  <yao.qi@linaro.org>

	* aarch64-tdep.c (aarch64_analyze_prologue): Handle register
	based STP instruction.
This commit is contained in:
Yao Qi 2016-08-19 14:49:31 +01:00
parent bbfa2517de
commit 03bcd7394e
2 changed files with 8 additions and 2 deletions
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5
gdb/ChangeLog
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@ -1,3 +1,8 @@
2016-08-19 Yao Qi <yao.qi@linaro.org>
* aarch64-tdep.c (aarch64_analyze_prologue): Handle register
based STP instruction.
2016-08-19 Yao Qi <yao.qi@linaro.org>
* completer.c (linespec_location_completer): Make file_to_match

5
gdb/aarch64-tdep.c
View file

@ -322,10 +322,11 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch,
is64 ? 8 : 4, regs[rt]);
}
else if ((inst.opcode->iclass == ldstpair_off
|| inst.opcode->iclass == ldstpair_indexed)
&& inst.operands[2].addr.preind
|| (inst.opcode->iclass == ldstpair_indexed
&& inst.operands[2].addr.preind))
&& strcmp ("stp", inst.opcode->name) == 0)
{
/* STP with addressing mode Pre-indexed and Base register. */
unsigned rt1 = inst.operands[0].reg.regno;
unsigned rt2 = inst.operands[1].reg.regno;
unsigned rn = inst.operands[2].addr.base_regno;