Fixed typo in previous delta and added more sanitization.
This commit is contained in:
Nick Clifton
parent
052d7984df
commit
035d8553d7
1 changed files with 289 additions and 64 deletions
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@ -60,15 +60,17 @@ const relax_typeS md_relax_table[] = {
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{0x1fffff, -0x200000, 6, 0},
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};
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/* start-sanitize-v850e */
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static boolean support_v850e = false;
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/* end-sanitize-v850e */
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/* start-sanitize-v850eq */
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static boolean support_v850eq = false;
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/* end-sanitize-v850eq */
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/* local functions */
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static unsigned long v850_insert_operand
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PARAMS ((unsigned long insn, const struct v850_operand *operand,
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offsetT val, char *file, unsigned int line));
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static int reg_name_search PARAMS ((const struct reg_name *, int, const char *));
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static boolean register_name PARAMS ((expressionS *expressionP));
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static boolean system_register_name PARAMS ((expressionS *expressionP));
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static boolean cc_name PARAMS ((expressionS *expressionP));
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static bfd_reloc_code_real_type v850_reloc_prefix PARAMS ((void));
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/* fixups */
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@ -82,12 +84,6 @@ struct v850_fixup
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struct v850_fixup fixups[MAX_INSN_FIXUPS];
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static int fc;
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const char *md_shortopts = "";
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struct option md_longopts[] = {
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{NULL, no_argument, NULL, 0}
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};
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size_t md_longopts_size = sizeof(md_longopts);
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/* The target specific pseudo-ops which we support. */
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const pseudo_typeS md_pseudo_table[] =
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{
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@ -349,19 +345,141 @@ cc_name (expressionP)
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}
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}
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/* start-sanitize-v850e */
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/* Summary of parse_register_list ().
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*
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* in: Input_line_pointer points to 1st char of a list of registers.
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* insn is the partially constructed instruction.
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* operand is the operand being inserted.
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*
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* out: True if the parse completed successfully, False otherwise.
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* If the parse completes the correct bit fields in the
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* instruction will be filled in.
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*/
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static boolean
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parse_register_list
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(
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unsigned long * insn,
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const struct v850_operand * operand
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)
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{
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static int type1_regs[ 32 ] = { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 };
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/* start-sanitize-v850eq */
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static int type2_regs[ 32 ] = { 19, 18, 17, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 30, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 };
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static int type3_regs[ 32 ] = { 3, 2, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 14, 15, 13, 12, 7, 6, 5, 4, 11, 10, 9, 8 };
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/* end-sanitize-v850eq */
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int * regs;
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/* Select a register array to parse. */
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switch (operand->shift)
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{
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case 0xffe00001: regs = type1_regs; break;
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/* start-sanitize-v850eq */
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case 0xfff8000f: regs = type2_regs; break;
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case 0xfff8001f: regs = type3_regs; break;
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/* end-sanitize-v850eq */
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default:
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fprintf (stderr, "unknown operand shift: %x\n", operand->shift );
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return false;
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}
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/* Parse the register list until a terminator (comma or new-line) is found. */
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for (;;)
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{
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expressionS exp;
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int i;
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if (register_name (& exp))
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{
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/* Locate the given register in the list, and if it is there, insert the corresponding bit into the instruction. */
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for (i = 0; i < 32; i++)
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{
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if (regs[ i ] == exp.X_add_number)
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{
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* insn |= (1 << i);
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break;
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}
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}
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if (i == 32)
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{
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as_bad( "unable to insert register r%d into list\n", exp.X_add_number );
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return false;
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}
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}
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else if (system_register_name (& exp))
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{
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if (regs == type1_regs)
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{
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as_bad ("system registers cannot be included in this register list" );
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return false;
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}
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else if (exp.X_add_number == 5)
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{
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if (regs == type2_regs)
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as_bad ("PSW cannot be included in this register list" );
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else
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* insn |= 0x8;
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}
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else
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* insn |= 0x80000;
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}
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else
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break;
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/* Skip white space. */
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while (* input_line_pointer == ' ' || * input_line_pointer == '\t')
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++ input_line_pointer;
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}
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return true;
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}
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/* end-sanitize-v850e */
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CONST char * md_shortopts = "m:";
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struct option md_longopts[] =
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{
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{NULL, no_argument, NULL, 0}
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};
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size_t md_longopts_size = sizeof md_longopts;
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void
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md_show_usage (stream)
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FILE *stream;
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{
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fprintf(stream, "V850 options:\n\
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none yet\n");
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fprintf (stream, "V850 options:\n");
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/* start-sanitize-v850e */
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fprintf (stream, " -mcpu=v850e target the V850E processor\n");
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/* end-sanitize-v850e */
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/* start-sanitize-v850eq */
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fprintf (stream, " -mcpu=v850eq target the V850E processor with Quantum's extensions\n");
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/* end-sanitize-v850eq */
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}
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int
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md_parse_option (c, arg)
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int c;
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char *arg;
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int c;
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char * arg;
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{
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/* start-sanitize-v850e */
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if ((c == 'm') && arg != NULL && (strcmp (arg, "cpu=v850e") == 0))
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{
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support_v850e = true;
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return 1;
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}
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/* end-sanitize-v850e */
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/* start-sanitize-v850eq */
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if ((c == 'm') && arg != NULL && (strcmp (arg, "cpu=v850eq") == 0))
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{
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support_v850e = true;
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support_v850eq = true;
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return 1;
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}
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/* end-sanitize-v850eq */
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return 0;
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}
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@ -487,7 +605,7 @@ md_begin ()
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}
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static bfd_reloc_code_real_type
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v850_reloc_prefix()
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v850_reloc_prefix ()
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{
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if (strncmp(input_line_pointer, "hi0(", 4) == 0)
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{
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@ -563,22 +681,30 @@ v850_reloc_prefix()
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void
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md_assemble (str)
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char *str;
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char * str;
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{
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char *s;
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struct v850_opcode *opcode;
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struct v850_opcode *next_opcode;
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const unsigned char *opindex_ptr;
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int next_opindex, relaxable;
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unsigned long insn, insn_size;
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char *f;
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int i;
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int match;
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bfd_reloc_code_real_type reloc;
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char * s;
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char * start_of_operands;
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struct v850_opcode * opcode;
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struct v850_opcode * next_opcode;
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const unsigned char * opindex_ptr;
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int next_opindex;
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int relaxable;
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unsigned long insn;
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unsigned long insn_size;
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char * f;
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int i;
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int match;
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bfd_reloc_code_real_type reloc;
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boolean extra_data_after_insn = false;
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unsigned extra_data_len;
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unsigned long extra_data;
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/* Get the opcode. */
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for (s = str; *s != '\0' && ! isspace (*s); s++)
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;
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continue;
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if (*s != '\0')
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*s++ = '\0';
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@ -587,6 +713,7 @@ md_assemble (str)
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if (opcode == NULL)
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{
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as_bad ("Unrecognized opcode: `%s'", str);
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ignore_rest_of_line ();
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return;
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}
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@ -594,22 +721,42 @@ md_assemble (str)
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while (isspace (*str))
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++str;
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input_line_pointer = str;
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start_of_operands = str;
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for(;;)
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for (;;)
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{
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const char *errmsg = NULL;
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const char * errmsg = NULL;
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relaxable = 0;
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fc = 0;
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match = 0;
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next_opindex = 0;
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insn = opcode->opcode;
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extra_data_after_insn = false;
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input_line_pointer = str = start_of_operands;
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/* start-sanitize-v850e */
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if ((opcode->flags & V850E_INSTRUCTION) && ! support_v850e)
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{
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errmsg = "V850E instructions not allowed";
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goto error;
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}
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/* end-sanitize-v850e */
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/* start-sanitize-v850eq */
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if ((opcode->flags & V850EQ_INSTRUCTION) && ! support_v850eq)
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{
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errmsg = "V850EQ instructions not allowed";
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goto error;
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}
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/* end-sanitize-v850eq */
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for (opindex_ptr = opcode->operands; *opindex_ptr != 0; opindex_ptr++)
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{
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const struct v850_operand *operand;
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char *hold;
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expressionS ex;
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const struct v850_operand * operand;
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char * hold;
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expressionS ex;
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if (next_opindex == 0)
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{
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@ -632,12 +779,13 @@ md_assemble (str)
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/* Gather the operand. */
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hold = input_line_pointer;
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input_line_pointer = str;
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// fprintf (stderr, "operand: %s index = %d, opcode = %s\n", input_line_pointer, opindex_ptr - opcode->operands, opcode->name );
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/* lo(), hi(), hi0(), etc... */
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if ((reloc = v850_reloc_prefix()) != BFD_RELOC_UNUSED)
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{
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expression(&ex);
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expression (& ex);
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if (ex.X_op == O_constant)
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{
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@ -702,26 +850,27 @@ md_assemble (str)
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}
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else
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{
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errmsg = NULL;
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if ((operand->flags & V850_OPERAND_REG) != 0)
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{
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if (!register_name(&ex))
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if (!register_name (& ex))
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{
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errmsg = "invalid register name";
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goto error;
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}
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}
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else if ((operand->flags & V850_OPERAND_SRG) != 0)
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{
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if (!system_register_name(&ex))
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if (!system_register_name (& ex))
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{
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errmsg = "invalid system register name";
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goto error;
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}
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}
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else if ((operand->flags & V850_OPERAND_EP) != 0)
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{
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char *start = input_line_pointer;
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char c = get_symbol_end ();
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char * start = input_line_pointer;
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char c = get_symbol_end ();
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if (strcmp (start, "ep") != 0 && strcmp (start, "r30") != 0)
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{
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/* Put things back the way we found them. */
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@ -730,6 +879,7 @@ md_assemble (str)
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errmsg = "expected EP register";
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goto error;
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}
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*input_line_pointer = c;
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str = input_line_pointer;
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input_line_pointer = hold;
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@ -740,35 +890,92 @@ md_assemble (str)
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}
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else if ((operand->flags & V850_OPERAND_CC) != 0)
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{
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if (!cc_name(&ex))
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if (!cc_name (& ex))
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{
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errmsg = "invalid condition code name";
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goto error;
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}
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}
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else if (operand->flags & V850E_PUSH_POP)
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{
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if (! parse_register_list (& insn, operand))
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{
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errmsg = "invalid register list";
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}
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/* The parse_register_list() function has already done everything, so fake a dummy expression. */
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ex.X_op = O_constant;
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ex.X_add_number = 0;
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}
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else if (operand->flags & V850E_IMMEDIATE16)
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{
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expression (& ex);
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if (ex.X_op != O_constant)
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errmsg = "constant expression expected";
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else if (ex.X_add_number & 0xffff0000)
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{
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if (ex.X_add_number & 0xffff)
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errmsg = "constant too big to fit into instruction";
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else if ((insn & 0x001fffc0) == 0x00130780)
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ex.X_add_number >>= 16;
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else
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errmsg = "constant too big to fit into instruction";
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}
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extra_data_after_insn = true;
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extra_data_len = 2;
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extra_data = ex.X_add_number;
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ex.X_add_number = 0;
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}
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else if (operand->flags & V850E_IMMEDIATE32)
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{
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expression (& ex);
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if (ex.X_op != O_constant)
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errmsg = "constant expression expected";
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extra_data_after_insn = true;
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extra_data_len = 4;
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extra_data = ex.X_add_number;
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ex.X_add_number = 0;
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}
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else if (register_name (&ex)
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&& (operand->flags & V850_OPERAND_REG) == 0)
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{
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errmsg = "syntax error: register not expected";
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goto error;
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}
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else if (system_register_name (&ex)
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&& (operand->flags & V850_OPERAND_SRG) == 0)
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{
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errmsg = "syntax error: system register not expected";
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goto error;
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}
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else if (cc_name (&ex)
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&& (operand->flags & V850_OPERAND_CC) == 0)
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{
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errmsg = "syntax error: condition code not expected";
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goto error;
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}
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else
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{
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expression(&ex);
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expression (& ex);
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/* start-sanitize-v850e */
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/* Special case:
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If we are assembling a MOV instruction (or a CALLT.... :-)
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and the immediate value does not fit into the bits available
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and we are supporting V850e instructions
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then create a fake error so that the next MOV instruction
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will be selected. This one has a 32 bit immediate field. */
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if (((insn & 0x07e0) == 0x0200)
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&& ex.X_op == O_constant
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&& (ex.X_add_number < (- (1 << (operand->bits - 1))) || ex.X_add_number > ((1 << operand->bits) - 1))
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&& support_v850e)
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errmsg = "use bigger instruction";
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/* end-sanitize-v850e */
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}
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if (errmsg)
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goto error;
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switch (ex.X_op)
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{
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case O_illegal:
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@ -783,7 +990,13 @@ md_assemble (str)
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errmsg = "invalid operand";
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goto error;
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}
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#if 0
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if (ex.X_add_number == 0
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&& (operand->shift == 11))
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{
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as_warn ("register 0 being used as destination of instruction" );
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}
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#endif
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insn = v850_insert_operand (insn, operand, ex.X_add_number,
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(char *) NULL, 0);
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break;
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@ -803,7 +1016,6 @@ md_assemble (str)
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++fc;
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break;
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}
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}
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str = input_line_pointer;
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@ -826,6 +1038,7 @@ md_assemble (str)
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}
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as_bad ("%s", errmsg);
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ignore_rest_of_line ();
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return;
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}
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break;
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@ -853,17 +1066,28 @@ md_assemble (str)
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md_number_to_chars (f + 2, 0, 4);
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fc = 0;
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}
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else if ((insn & 0x0600) == 0x0600)
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else
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{
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insn_size = 4;
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f = frag_more (insn_size);
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md_number_to_chars (f, insn, insn_size);
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}
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else
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{
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insn_size = 2;
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if ((insn & 0x0600) == 0x0600)
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||||
insn_size = 4;
|
||||
else
|
||||
insn_size = 2;
|
||||
|
||||
/* Special case: 32 bit MOV */
|
||||
if ((insn & 0xffe0) == 0x0620)
|
||||
insn_size = 2;
|
||||
|
||||
f = frag_more (insn_size);
|
||||
|
||||
md_number_to_chars (f, insn, insn_size);
|
||||
|
||||
if (extra_data_after_insn)
|
||||
{
|
||||
f = frag_more (extra_data_len);
|
||||
md_number_to_chars (f, extra_data, extra_data_len);
|
||||
|
||||
extra_data_after_insn = false;
|
||||
}
|
||||
}
|
||||
|
||||
/* Create any fixups. At this point we do not use a
|
||||
|
|
@ -1072,7 +1296,7 @@ md_apply_fix3 (fixp, valuep, seg)
|
|||
static unsigned long
|
||||
v850_insert_operand (insn, operand, val, file, line)
|
||||
unsigned long insn;
|
||||
const struct v850_operand *operand;
|
||||
const struct v850_operand * operand;
|
||||
offsetT val;
|
||||
char *file;
|
||||
unsigned int line;
|
||||
|
|
@ -1084,7 +1308,7 @@ v850_insert_operand (insn, operand, val, file, line)
|
|||
|
||||
if ((operand->flags & V850_OPERAND_SIGNED) != 0)
|
||||
{
|
||||
max = (1 << (operand->bits - 1)) - 1;
|
||||
max = (1 << (operand->bits - 1)) - 1;
|
||||
min = - (1 << (operand->bits - 1));
|
||||
}
|
||||
else
|
||||
|
|
@ -1095,10 +1319,9 @@ v850_insert_operand (insn, operand, val, file, line)
|
|||
|
||||
test = val;
|
||||
|
||||
|
||||
if (test < (offsetT) min || test > (offsetT) max)
|
||||
{
|
||||
const char *err =
|
||||
const char * err =
|
||||
"operand out of range (%s not between %ld and %ld)";
|
||||
char buf[100];
|
||||
|
||||
|
|
@ -1112,8 +1335,9 @@ v850_insert_operand (insn, operand, val, file, line)
|
|||
|
||||
if (operand->insert)
|
||||
{
|
||||
const char *message = NULL;
|
||||
insn = (*operand->insert) (insn, val, &message);
|
||||
const char * message = NULL;
|
||||
|
||||
insn = (*operand->insert) (insn, val, & message);
|
||||
if (message != NULL)
|
||||
{
|
||||
if (file == (char *) NULL)
|
||||
|
|
@ -1124,6 +1348,7 @@ v850_insert_operand (insn, operand, val, file, line)
|
|||
}
|
||||
else
|
||||
insn |= (((long) val & ((1 << operand->bits) - 1)) << operand->shift);
|
||||
|
||||
return insn;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue