* gas/ppc/test2elf64.s: Rename to..
* gas/ppc/power4.s: ..this. Add mtcr and mfcr testcases. * gas/ppc/test2elf64.d: Rename to.. * gas/ppc/power4.d: ..this. Update. * gas/ppc/ppc.exp: Update.
This commit is contained in:
parent
c168870a29
commit
03417200ae
4 changed files with 61 additions and 32 deletions
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@ -1,3 +1,11 @@
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2003-07-04 Alan Modra <amodra@bigpond.net.au>
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* gas/ppc/test2elf64.s: Rename to..
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* gas/ppc/power4.s: ..this. Add mtcr and mfcr testcases.
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* gas/ppc/test2elf64.d: Rename to..
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* gas/ppc/power4.d: ..this. Update.
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* gas/ppc/ppc.exp: Update.
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2003-07-02 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
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* gas/mips/set-arch.d: Fix GPR names and show raw insns.
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@ -1,6 +1,6 @@
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#objdump: -Drx -Mpower4
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#objdump: -drx -Mpower4
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#as: -mpower4
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#name: PowerPC Test 2, 64 bit elf, power4 instructions
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#name: Power4 instructions
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.*: +file format elf64-powerpc
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.*
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@ -10,7 +10,7 @@ start address 0x0+
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Sections:
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Idx Name +Size +VMA +LMA +File off +Algn
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+0 \.text +0+68 +0+ +0+ +.*
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+0 \.text +0+b8 +0+ +0+ +.*
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+CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
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+1 \.data +0+10 +0+ +0+ +.*
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+CONTENTS, ALLOC, LOAD, DATA
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@ -79,23 +79,23 @@ Disassembly of section \.text:
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+5c: f8 c7 80 02 stq r6,-32768\(r7\)
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+60: f8 c7 7f f2 stq r6,32752\(r7\)
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+64: 00 00 02 00 attn
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Disassembly of section \.data:
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0+ <dsym0>:
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+0: 00 00 00 00 \.long 0x0
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+4: de ad be ef stfdu f21,-16657\(r13\)
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0+8 <dsym1>:
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+8: 00 00 00 00 \.long 0x0
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+c: ca fe ba be lfd f23,-17730\(r30\)
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Disassembly of section \.toc:
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0+ <\.toc>:
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\.\.\.
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0: R_PPC64_ADDR64 dsym0
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8: R_PPC64_ADDR64 dsym1
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10: R_PPC64_ADDR64 usym0
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18: R_PPC64_ADDR64 usym1
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20: R_PPC64_ADDR64 esym0
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28: R_PPC64_ADDR64 esym1
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+68: 7c 6f f1 20 mtcr r3
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+6c: 7c 6f f1 20 mtcr r3
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+70: 7c 68 11 20 mtcrf 129,r3
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+74: 7c 70 11 20 mtcrf 1,r3
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+78: 7c 70 21 20 mtcrf 2,r3
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+7c: 7c 70 41 20 mtcrf 4,r3
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+80: 7c 70 81 20 mtcrf 8,r3
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+84: 7c 71 01 20 mtcrf 16,r3
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+88: 7c 72 01 20 mtcrf 32,r3
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+8c: 7c 74 01 20 mtcrf 64,r3
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+90: 7c 78 01 20 mtcrf 128,r3
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+94: 7c 60 00 26 mfcr r3
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+98: 7c 70 10 26 mfcr r3,1
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+9c: 7c 70 20 26 mfcr r3,2
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+a0: 7c 70 40 26 mfcr r3,4
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+a4: 7c 70 80 26 mfcr r3,8
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+a8: 7c 71 00 26 mfcr r3,16
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+ac: 7c 72 00 26 mfcr r3,32
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+b0: 7c 74 00 26 mfcr r3,64
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+b4: 7c 78 00 26 mfcr r3,128
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@ -1,9 +1,7 @@
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.section ".data"
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dsym0: .llong 0xdeadbeef
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dsym1:
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.section ".toc"
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.L_tsym0:
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.tc ignored0[TC],dsym0
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@ -18,7 +16,6 @@ dsym1:
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.L_tsym5:
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.tc ignored5[TC],esym1
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.section ".text"
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lq 4,dsym0@l(3)
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lq 4,dsym1@l(3)
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@ -40,13 +37,37 @@ dsym1:
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lq 6,dsym1@sectoff(3)
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lq 6,dsym1@sectoff@l(3)
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lq 6,usym1-dsym0@l(4)
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stq 6, 0(7)
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stq 6, 16(7)
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stq 6, -16(7)
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stq 6, -32768(7)
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stq 6, 32752(7)
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stq 6,0(7)
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stq 6,16(7)
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stq 6,-16(7)
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stq 6,-32768(7)
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stq 6,32752(7)
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attn
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mtcr 3
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mtcrf 0xff,3
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mtcrf 0x81,3
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mtcrf 0x01,3
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mtcrf 0x02,3
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mtcrf 0x04,3
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mtcrf 0x08,3
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mtcrf 0x10,3
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mtcrf 0x20,3
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mtcrf 0x40,3
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mtcrf 0x80,3
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mfcr 3
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# mfcr 3,0xff #Error, invalid mask
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# mfcr 3,0x81 #Error, invalid mask
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mfcr 3,0x01
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mfcr 3,0x02
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mfcr 3,0x04
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mfcr 3,0x08
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mfcr 3,0x10
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mfcr 3,0x20
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mfcr 3,0x40
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mfcr 3,0x80
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.section ".data"
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usym0: .llong 0xcafebabe
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usym1:
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@ -10,7 +10,7 @@ if { [istarget powerpc64*-*-*] || [istarget *-*-elf64*]} then {
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run_dump_test "astest64"
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run_dump_test "astest2_64"
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run_dump_test "test1elf64"
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run_dump_test "test2elf64"
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run_dump_test "power4"
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} elseif { [istarget powerpc*-*aix*] } then {
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run_dump_test "test1xcoff32"
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} elseif { [istarget powerpc*-*-*bsd*] \
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