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Fix arm process record code format

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This patch fixes the various code format issues in arm process record
in arm-tdep.c, such as using tab instead of spaces.

gdb:

2016-02-22  Yao Qi  <yao.qi@linaro.org>

	* arm-tdep.c: Fix code format issues.
This commit is contained in:
Yao Qi 2016-02-22 12:08:51 +00:00
parent edbd4e326a
commit 01e57735b0
2 changed files with 140 additions and 136 deletions
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4
gdb/ChangeLog
View file

@ -1,3 +1,7 @@
2016-02-22 Yao Qi <yao.qi@linaro.org>
* arm-tdep.c: Fix code format issues.
2016-02-21 Iain Buclaw <ibuclaw@gdcproject.org> 2016-02-21 Iain Buclaw <ibuclaw@gdcproject.org>
* d-namespace.c (d_lookup_symbol_imports): Remove argument * d-namespace.c (d_lookup_symbol_imports): Remove argument

16
gdb/arm-tdep.c
View file

@ -10789,8 +10789,6 @@ arm_record_b_bl (insn_decode_record *arm_insn_r)
return 0; return 0;
} }
/* Handling opcode 110 insns. */
static int static int
arm_record_unsupported_insn (insn_decode_record *arm_insn_r) arm_record_unsupported_insn (insn_decode_record *arm_insn_r)
{ {
@ -10925,8 +10923,8 @@ arm_record_exreg_ld_st_insn (insn_decode_record *arm_insn_r)
} }
else else
{ {
uint8_t reg_m = (bits (arm_insn_r->arm_insn, 0, 3) << 1) uint8_t reg_m = ((bits (arm_insn_r->arm_insn, 0, 3) << 1)
| bit (arm_insn_r->arm_insn, 5); | bit (arm_insn_r->arm_insn, 5));
if (!single_reg) if (!single_reg)
{ {
@ -12653,7 +12651,8 @@ decode_insn (insn_decode_record *arm_record, record_type_t record_type,
uint32_t insn_size) uint32_t insn_size)
{ {
/* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm instruction. */ /* (Starting from numerical 0); bits 25, 26, 27 decodes type of arm
instruction. */
static const sti_arm_hdl_fp_t arm_handle_insn[8] = static const sti_arm_hdl_fp_t arm_handle_insn[8] =
{ {
arm_record_data_proc_misc_ld_str, /* 000. */ arm_record_data_proc_misc_ld_str, /* 000. */
@ -12666,7 +12665,8 @@ decode_insn (insn_decode_record *arm_record, record_type_t record_type,
arm_record_coproc_data_proc /* 111. */ arm_record_coproc_data_proc /* 111. */
}; };
/* (Starting from numerical 0); bits 13,14,15 decodes type of thumb instruction. */ /* (Starting from numerical 0); bits 13,14,15 decodes type of thumb
instruction. */
static const sti_arm_hdl_fp_t thumb_handle_insn[8] = static const sti_arm_hdl_fp_t thumb_handle_insn[8] =
{ \ { \
thumb_record_shift_add_sub, /* 000. */ thumb_record_shift_add_sub, /* 000. */
@ -12688,7 +12688,8 @@ decode_insn (insn_decode_record *arm_record, record_type_t record_type,
{ {
printf_unfiltered (_("Process record: error reading memory at " printf_unfiltered (_("Process record: error reading memory at "
"addr %s len = %d.\n"), "addr %s len = %d.\n"),
paddress (arm_record->gdbarch, arm_record->this_addr), insn_size); paddress (arm_record->gdbarch,
arm_record->this_addr), insn_size);
} }
return -1; return -1;
} }
@ -12851,4 +12852,3 @@ arm_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
return ret; return ret;
} }