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gas/testsuite/

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2005-05-07  H.J. Lu  <hongjiu.lu@intel.com>

	PR 843
	* gas/i386/i386.exp: Add x86-64-branch.

	* gas/i386/x86-64-branch.d: New.
	* gas/i386/x86-64-branch.s: New.

opcodes/

2005-05-07  H.J. Lu  <hongjiu.lu@intel.com>

	PR 843
	* i386-dis.c (branch_v_mode): New.
	(indirEv): Use branch_v_mode instead of v_mode.
	(OP_E): Handle branch_v_mode.
This commit is contained in:
H.J. Lu 2005-05-07 13:30:02 +00:00
parent 920a34a7b2
commit 003519a7c2
6 changed files with 49 additions and 1 deletions
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8
gas/testsuite/ChangeLog
View file

@ -1,3 +1,11 @@
2005-05-07 H.J. Lu <hongjiu.lu@intel.com>
PR 843
* gas/i386/i386.exp: Add x86-64-branch.
* gas/i386/x86-64-branch.d: New.
* gas/i386/x86-64-branch.s: New.
2005-05-06 Jan Beulich <jbeulich@novell.com>
* gas/macros/badarg.s: Add check for bad qualifier specification.

1
gas/testsuite/gas/i386/i386.exp
View file

@ -127,6 +127,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
run_list_test "x86-64-inval" "-al"
run_list_test "x86-64-segment" "-al"
run_list_test "x86-64-inval-seg" "-al"
run_dump_test "x86-64-branch"
# For ELF targets verify that @unwind works.
if { ([istarget "*-*-elf*"] || [istarget "*-*-linux*"]

13
gas/testsuite/gas/i386/x86-64-branch.d Normal file
View file

@ -0,0 +1,13 @@
#as: -J
#objdump: -drw
#name: x86-64 indirect branch
.*: +file format elf64-x86-64
Disassembly of section .text:
0+000 <.text>:
[ ]*0:[ ]+ff d0[ ]+callq[ ]+\*%rax
[ ]*2:[ ]+ff d0[ ]+callq[ ]+\*%rax
[ ]*4:[ ]+ff e0[ ]+jmpq[ ]+\*%rax
[ ]*6:[ ]+ff e0[ ]+jmpq[ ]+\*%rax

5
gas/testsuite/gas/i386/x86-64-branch.s Normal file
View file

@ -0,0 +1,5 @@
.text
callq *%rax
call *%rax
jmpq *%rax
jmp *%rax

7
opcodes/ChangeLog
View file

@ -1,3 +1,10 @@
2005-05-07 H.J. Lu <hongjiu.lu@intel.com>
PR 843
* i386-dis.c (branch_v_mode): New.
(indirEv): Use branch_v_mode instead of v_mode.
(OP_E): Handle branch_v_mode.
2005-05-07 H.J. Lu <hongjiu.lu@intel.com>
* d10v-dis.c (dis_2_short): Support 64bit host.

16
opcodes/i386-dis.c
View file

@ -197,7 +197,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
#define Eq OP_E, q_mode
#define Edq OP_E, dq_mode
#define Edqw OP_E, dqw_mode
#define indirEv OP_indirE, v_mode
#define indirEv OP_indirE, branch_v_mode
#define indirEp OP_indirE, f_mode
#define Ew OP_E, w_mode
#define Ma OP_E, v_mode
@ -323,6 +323,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
#define dqw_mode 12 /* registers like dq_mode, memory like w_mode. */
#define f_mode 13 /* 4- or 6-byte pointer operand */
#define const_1_mode 14
#define branch_v_mode 15 /* v_mode for branch. */
#define es_reg 100
#define cs_reg 101
@ -3155,6 +3156,18 @@ OP_E (int bytemode, int sizeflag)
else
oappend (names32[rm + add]);
break;
case branch_v_mode:
if (mode_64bit)
oappend (names64[rm + add]);
else
{
if ((sizeflag & DFLAG) || bytemode != branch_v_mode)
oappend (names32[rm + add]);
else
oappend (names16[rm + add]);
used_prefixes |= (prefixes & PREFIX_DATA);
}
break;
case v_mode:
case dq_mode:
case dqw_mode:
@ -3256,6 +3269,7 @@ OP_E (int bytemode, int sizeflag)
case dqw_mode:
oappend ("WORD PTR ");
break;
case branch_v_mode:
case v_mode:
case dq_mode:
USED_REX (REX_MODE64);