2011-03-06 00:20:21 +00:00
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/* Blackfin Memory Management Unit (MMU) model.
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2012-01-04 08:28:28 +00:00
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Copyright (C) 2010-2012 Free Software Foundation, Inc.
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2011-03-06 00:20:21 +00:00
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Contributed by Analog Devices, Inc.
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This file is part of simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program. If not, see <http://www.gnu.org/licenses/>. */
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#ifndef DV_BFIN_MMU_H
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#define DV_BFIN_MMU_H
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void mmu_check_addr (SIM_CPU *, bu32 addr, bool write, bool inst, int size);
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void mmu_check_cache_addr (SIM_CPU *, bu32 addr, bool write, bool inst);
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void mmu_process_fault (SIM_CPU *, bu32 addr, bool write, bool inst, bool unaligned, bool miss);
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void mmu_log_ifault (SIM_CPU *);
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/* MEM_CONTROL */
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#define ENM (1 << 0)
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#define ENCPLB (1 << 1)
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#define MC (1 << 2)
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#define ENDM ENM
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#define ENDCPLB ENCPLB
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#define DMC_AB_SRAM 0x0
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#define DMC_AB_CACHE 0xc
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#define DMC_ACACHE_BSRAM 0x8
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/* CPLB_DATA */
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#define CPLB_VALID (1 << 0)
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#define CPLB_USER_RD (1 << 2)
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#define CPLB_USER_WR (1 << 3)
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#define CPLB_USER_RW (CPLB_USER_RD | CPLB_USER_WR)
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#define CPLB_SUPV_WR (1 << 4)
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#define CPLB_L1SRAM (1 << 5)
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#define CPLB_DA0ACC (1 << 6)
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#define CPLB_DIRTY (1 << 7)
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#define CPLB_L1_CHBL (1 << 12)
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#define CPLB_WT (1 << 14)
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#define PAGE_SIZE (3 << 16)
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#define PAGE_SIZE_1K (0 << 16)
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#define PAGE_SIZE_4K (1 << 16)
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#define PAGE_SIZE_1M (2 << 16)
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#define PAGE_SIZE_4M (3 << 16)
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/* CPLB_STATUS */
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#define FAULT_CPLB0 (1 << 0)
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#define FAULT_CPLB1 (1 << 1)
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#define FAULT_CPLB2 (1 << 2)
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#define FAULT_CPLB3 (1 << 3)
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#define FAULT_CPLB4 (1 << 4)
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#define FAULT_CPLB5 (1 << 5)
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#define FAULT_CPLB6 (1 << 6)
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#define FAULT_CPLB7 (1 << 7)
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#define FAULT_CPLB8 (1 << 8)
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#define FAULT_CPLB9 (1 << 9)
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#define FAULT_CPLB10 (1 << 10)
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#define FAULT_CPLB11 (1 << 11)
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#define FAULT_CPLB12 (1 << 12)
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#define FAULT_CPLB13 (1 << 13)
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#define FAULT_CPLB14 (1 << 14)
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#define FAULT_CPLB15 (1 << 15)
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#define FAULT_READ (0 << 16)
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#define FAULT_WRITE (1 << 16)
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#define FAULT_USER (0 << 17)
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#define FAULT_SUPV (1 << 17)
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#define FAULT_DAG0 (0 << 18)
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#define FAULT_DAG1 (1 << 18)
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#define FAULT_ILLADDR (1 << 19)
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/* DTEST_COMMAND */
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#define TEST_READ (0 << 1)
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#define TEST_WRITE (1 << 1)
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#define TEST_TAG_ARRAY (0 << 2)
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#define TEST_DATA_ARRAY (1 << 2)
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#define TEST_DBANK (1 << 23)
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#define TEST_DATA_SRAM (0 << 24)
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#define TEST_INST_SRAM (1 << 24)
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#endif
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