1993-04-27 01:02:38 +00:00
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/* Simulator for the Hitachi SH architecture.
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Written by Steve Chamberlain of Cygnus Support.
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sac@cygnus.com
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This file is part of SH sim
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THIS SOFTWARE IS NOT COPYRIGHTED
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Cygnus offers the following for use in the public domain. Cygnus
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makes no warranty with regard to the software or it's performance
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and the user accepts the software "AS IS" with all faults.
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CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
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THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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*/
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1993-06-18 01:31:54 +00:00
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#include "sysdep.h"
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1993-04-27 01:02:38 +00:00
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#include <sys/times.h>
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#include <sys/param.h>
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#define O_RECOMPILE 85
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#define DEFINE_TABLE
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#define DISASSEMBLER_TABLE
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#define SBIT(x) ((x)&sbit)
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1993-06-18 01:31:54 +00:00
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#define R0 saved_state.asregs.regs[0]
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#define Rn saved_state.asregs.regs[n]
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#define Rm saved_state.asregs.regs[m]
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#define UR0 (unsigned int)(saved_state.asregs.regs[0])
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#define UR (unsigned int)R
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#define UR (unsigned int)R
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#define SR0 saved_state.asregs.regs[0]
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#define GBR saved_state.asregs.gbr
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#define VBR saved_state.asregs.vbr
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#define MACH saved_state.asregs.mach
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#define MACL saved_state.asregs.macl
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#define M saved_state.asregs.sr.bits.m
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#define Q saved_state.asregs.sr.bits.q
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1993-04-27 01:02:38 +00:00
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#define GET_SR() (saved_state.asregs.sr.bits.t = T, saved_state.asregs.sr.word)
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#define SET_SR(x) {saved_state.asregs.sr.word = (x); T =saved_state.asregs.sr.bits.t;}
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#define PC pc
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#define C cycles
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1993-06-18 01:31:54 +00:00
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#ifdef TARGET_BIG_ENDIAN
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#define LMEM(x) *((long *)(memory+((x)&maskl)))
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#define BMEM(x) *((char *)(memory+((x)&maskb)))
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#define UWMEM(x) *((unsigned short *)(memory+((x)&maskw)))
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#define SWMEM(x) *((short *)(memory+((x)&maskw)))
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#define WLAT(x,value) (LMEM(x) = value)
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#define RLAT(x) (LMEM(x))
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#define WWAT(x,value) (UWMEM(x) = value)
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#define RSWAT(x) (SWMEM(x))
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#define RUWAT(x) (UWMEM(x))
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#define WBAT(x,value) (BMEM(x) = value)
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#define RBAT(x) (BMEM(x))
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#else
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/* For little endian or unknown host machines */
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#define WLAT(x,value)\
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{ int v = value; unsigned char *p = memory + ((x) & maskl);\
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p[0] =v>>24;p[1] = v>>16;p[2]=v>>8;p[3]=v; }
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#define WWAT(x,value)\
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{ int v = value; unsigned char *p = memory + (x & maskw);p[0] =v>>8;p[1] = v ;}
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#define WBAT(x,value)\
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{ unsigned char *p = memory + (x & maskb);p[0] =value;}
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#define RLAT(x)\
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((memory[x&maskl]<<24)|(memory[(x&maskl)+1]<<16)|(memory[(x&maskl)+2]<<8)| (memory[(x&maskl)+3]))
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#define RWAT(x)\
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((memory[x&maskw]<<8)|(memory[(x&maskw)+1]))
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#define RBAT(x)\
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((memory[x&maskb]))
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#define RUWAT(x) (RWAT(x) & 0xffff)
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#define RSWAT(x) ((short)(RWAT(x)))
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#define RSBAT(x) (SEXT(RBAT(x)))
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#endif
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#define SEXT(x) (((x&0xff) ^ (~0x7f))+0x80)
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#define SEXTW(y) ((int)((short)y))
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#define SL(TEMPPC) iword= RUWAT(TEMPPC); goto top;
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#define L(x) thislock = x;
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#define TL(x) if ((x) == prevlock) stalls++;
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#define TB(x,y) if ((x) == prevlock || (y)==prevlock) stalls++;
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int sim_memory_size = 19;
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static int sim_profile_size = 17;
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static int nsamples;
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1993-04-27 01:02:38 +00:00
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typedef union
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{
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struct
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{
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int regs[16];
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int pc;
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int pr;
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int gbr;
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int vbr;
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int mach;
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int macl;
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union
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{
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struct
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{
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1993-06-18 01:31:54 +00:00
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unsigned int d0:22;
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unsigned int m:1;
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unsigned int q:1;
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unsigned int i:4;
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unsigned int d1:2;
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unsigned int s:1;
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unsigned int t:1;
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1993-04-27 01:02:38 +00:00
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}
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bits;
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int word;
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}
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sr;
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int ticks;
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1993-06-18 01:31:54 +00:00
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int stalls;
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1993-04-27 01:02:38 +00:00
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int cycles;
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int insts;
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1993-06-18 01:31:54 +00:00
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int prevlock;
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int thislock;
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int exception;
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int msize;
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#define PROFILE_FREQ 1
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#define PROFILE_SHIFT 2
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int profile;
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unsigned short *profile_hist;
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unsigned char *memory;
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1993-06-18 20:53:58 +00:00
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1993-04-27 01:02:38 +00:00
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}
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asregs;
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1993-06-18 01:31:54 +00:00
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int asints[28];
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1993-04-27 01:02:38 +00:00
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}
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saved_state_type;
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saved_state_type saved_state;
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static int
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get_now ()
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{
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struct tms b;
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times (&b);
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return b.tms_utime + b.tms_stime;
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}
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static int
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now_persec ()
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{
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1993-06-18 01:31:54 +00:00
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#ifdef CLK_TCK
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return CLK_TCK;
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#endif
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#ifdef HZ
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1993-04-27 01:02:38 +00:00
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return HZ;
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1993-06-18 01:31:54 +00:00
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#endif
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return 50;
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}
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static FILE *profile_file;
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1993-06-18 20:53:58 +00:00
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static void
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swap (b, n)
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1993-06-18 01:31:54 +00:00
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unsigned char *b;
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int n;
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1993-06-18 20:53:58 +00:00
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{
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b[0] = n >> 24;
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b[1] = n >> 16;
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b[2] = n >> 8;
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b[3] = n >> 0;
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1993-06-18 01:31:54 +00:00
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}
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1993-06-18 20:53:58 +00:00
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static void
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swap16 (b, n)
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1993-06-18 01:31:54 +00:00
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unsigned char *b;
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int n;
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1993-06-18 20:53:58 +00:00
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{
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b[0] = n >> 8;
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b[1] = n >> 0;
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1993-04-27 01:02:38 +00:00
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}
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1993-06-18 01:31:54 +00:00
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static void
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1993-06-18 20:53:58 +00:00
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swapout (n)
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1993-06-18 01:31:54 +00:00
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int n;
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{
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1993-06-18 20:53:58 +00:00
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if (profile_file)
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1993-06-18 01:31:54 +00:00
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{
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char b[4];
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1993-06-18 20:53:58 +00:00
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swap (b, n);
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fwrite (b, 4, 1, profile_file);
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1993-06-18 01:31:54 +00:00
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}
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1993-06-18 20:53:58 +00:00
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}
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1993-06-18 01:31:54 +00:00
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static void
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1993-06-18 20:53:58 +00:00
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swapout16 (n)
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1993-06-18 01:31:54 +00:00
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int n;
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{
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char b[4];
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1993-06-18 20:53:58 +00:00
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swap16 (b, n);
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fwrite (b, 2, 1, profile_file);
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}
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1993-06-18 01:31:54 +00:00
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/* Turn a pointer in a register into a pointer into real memory. */
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static char *
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ptr (x)
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int x;
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{
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1993-06-18 20:53:58 +00:00
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return (char *) (x + saved_state.asregs.memory);
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1993-06-18 01:31:54 +00:00
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}
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/* Simulate a monitor trap. */
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static void
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1993-04-27 01:02:38 +00:00
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trap (i, regs)
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1993-06-18 01:31:54 +00:00
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int i;
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1993-04-27 01:02:38 +00:00
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int *regs;
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{
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switch (i)
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{
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case 1:
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printf ("%c", regs[0]);
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break;
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case 2:
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saved_state.asregs.exception = SIGQUIT;
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break;
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1993-06-18 01:31:54 +00:00
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case 3:
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{
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extern int errno;
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int perrno = errno;
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errno = 0;
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switch (regs[4])
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{
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case 3:
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regs[4] = read (regs[5], ptr (regs[6]), regs[7]);
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break;
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case 4:
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regs[4] = write (regs[5], ptr (regs[6]), regs[7]);
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break;
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case 19:
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regs[4] = lseek (regs[5], regs[6], regs[7]);
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break;
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case 6:
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regs[4] = close (regs[5]);
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break;
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case 5:
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regs[4] = open (ptr (regs[5]), regs[6]);
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break;
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default:
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abort ();
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}
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regs[0] = errno;
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errno = perrno;
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}
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break;
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1993-04-27 01:02:38 +00:00
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case 255:
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saved_state.asregs.exception = SIGILL;
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break;
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}
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}
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void
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control_c (sig, code, scp, addr)
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int sig;
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int code;
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char *scp;
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char *addr;
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{
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saved_state.asregs.exception = SIGINT;
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}
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1993-06-18 20:53:58 +00:00
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static int
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1993-06-18 01:31:54 +00:00
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div1 (R, iRn2, iRn1, T)
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1993-04-27 01:02:38 +00:00
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int *R;
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1993-06-18 01:31:54 +00:00
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int iRn1;
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int iRn2;
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1993-04-27 01:02:38 +00:00
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int T;
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{
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unsigned long tmp0;
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unsigned char old_q, tmp1;
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1993-06-18 01:31:54 +00:00
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1993-04-27 01:02:38 +00:00
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old_q = Q;
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1993-06-18 01:31:54 +00:00
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Q = (unsigned char) ((0x80000000 & R[iRn1]) != 0);
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R[iRn1] <<= 1;
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R[iRn1] |= (unsigned long) T;
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switch (old_q)
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1993-04-27 01:02:38 +00:00
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{
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1993-06-18 20:53:58 +00:00
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case 0:
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1993-06-18 01:31:54 +00:00
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switch (M)
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1993-06-18 20:53:58 +00:00
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{
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case 0:
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tmp0 = R[iRn1];
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R[iRn1] -= R[iRn2];
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tmp1 = (R[iRn1] > tmp0);
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switch (Q)
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{
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case 0:
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Q = tmp1;
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break;
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case 1:
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Q = (unsigned char) (tmp1 == 0);
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break;
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}
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break;
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case 1:
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tmp0 = R[iRn1];
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R[iRn1] += R[iRn2];
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tmp1 = (R[iRn1] < tmp0);
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switch (Q)
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{
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case 0:
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Q = (unsigned char) (tmp1 == 0);
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break;
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case 1:
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Q = tmp1;
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break;
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}
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break;
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}
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1993-04-27 01:02:38 +00:00
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break;
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case 1:
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switch (M)
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{
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1993-06-18 20:53:58 +00:00
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case 0:
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1993-06-18 01:31:54 +00:00
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tmp0 = R[iRn1];
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R[iRn1] += R[iRn2];
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tmp1 = (R[iRn1] < tmp0);
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switch (Q)
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{
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case 0:
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Q = tmp1;
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break;
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case 1:
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Q = (unsigned char) (tmp1 == 0);
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1993-06-18 20:53:58 +00:00
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break;
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1993-06-18 01:31:54 +00:00
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|
|
}
|
1993-04-27 01:02:38 +00:00
|
|
|
break;
|
1993-06-18 20:53:58 +00:00
|
|
|
case 1:
|
1993-06-18 01:31:54 +00:00
|
|
|
tmp0 = R[iRn1];
|
|
|
|
R[iRn1] -= R[iRn2];
|
|
|
|
tmp1 = (R[iRn1] > tmp0);
|
|
|
|
switch (Q)
|
|
|
|
{
|
|
|
|
case 0:
|
|
|
|
Q = (unsigned char) (tmp1 == 0);
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
Q = tmp1;
|
|
|
|
break;
|
|
|
|
}
|
1993-04-27 01:02:38 +00:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
break;
|
1993-06-18 01:31:54 +00:00
|
|
|
}
|
|
|
|
T = (Q == M);
|
|
|
|
return T;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
1993-06-18 20:53:58 +00:00
|
|
|
static void
|
|
|
|
dmul (sign, rm, rn)
|
|
|
|
int sign;
|
|
|
|
unsigned int rm;
|
|
|
|
unsigned int rn;
|
|
|
|
{
|
|
|
|
unsigned long RnL, RnH;
|
|
|
|
unsigned long RmL, RmH;
|
|
|
|
unsigned long temp0, temp1, temp2, temp3;
|
|
|
|
unsigned long Res2, Res1, Res0;
|
1993-06-18 01:31:54 +00:00
|
|
|
|
1993-04-27 01:02:38 +00:00
|
|
|
|
1993-06-18 20:53:58 +00:00
|
|
|
if (!sign)
|
1993-06-18 01:31:54 +00:00
|
|
|
{
|
1993-04-27 01:02:38 +00:00
|
|
|
|
1993-06-18 20:53:58 +00:00
|
|
|
RnL = rn & 0xffff;
|
|
|
|
RnH = (rn >> 16) & 0xffff;
|
|
|
|
RmL = rm & 0xffff;
|
|
|
|
RmH = (rm >> 16) & 0xffff;
|
|
|
|
temp0 = RmL * RnL;
|
|
|
|
temp1 = RmH * RnL;
|
|
|
|
temp2 = RmL * RnH;
|
|
|
|
temp3 = RmH * RnH;
|
|
|
|
Res2 = 0;
|
|
|
|
Res1 = temp1 + temp2;
|
|
|
|
if (Res1 < temp1)
|
|
|
|
Res2 += 0x00010000;
|
|
|
|
temp1 = (Res1 << 16) & 0xffff0000;
|
|
|
|
Res0 = temp0 + temp1;
|
|
|
|
if (Res0 < temp0)
|
|
|
|
Res2 += 1;
|
|
|
|
Res2 += ((Res1 >> 16) & 0xffff) + temp3;
|
|
|
|
MACH = Res2;
|
|
|
|
MACL = Res0;
|
1993-04-27 01:02:38 +00:00
|
|
|
|
1993-06-18 01:31:54 +00:00
|
|
|
}
|
1993-06-18 20:53:58 +00:00
|
|
|
|
|
|
|
else
|
1993-06-18 01:31:54 +00:00
|
|
|
{
|
1993-06-18 20:53:58 +00:00
|
|
|
abort ();
|
1993-06-18 01:31:54 +00:00
|
|
|
}
|
1993-06-18 20:53:58 +00:00
|
|
|
|
1993-04-27 01:02:38 +00:00
|
|
|
}
|
|
|
|
|
1993-06-18 20:53:58 +00:00
|
|
|
|
1993-06-18 01:31:54 +00:00
|
|
|
/* Set the memory size to the power of two provided. */
|
|
|
|
|
|
|
|
void
|
|
|
|
sim_size (power)
|
|
|
|
int power;
|
|
|
|
|
|
|
|
{
|
|
|
|
saved_state.asregs.msize = 1 << power;
|
|
|
|
|
1993-06-18 20:53:58 +00:00
|
|
|
sim_memory_size = power;
|
1993-06-18 01:31:54 +00:00
|
|
|
|
|
|
|
|
|
|
|
if (saved_state.asregs.memory)
|
|
|
|
{
|
|
|
|
free (saved_state.asregs.memory);
|
|
|
|
}
|
|
|
|
|
|
|
|
saved_state.asregs.memory =
|
|
|
|
(unsigned char *) calloc (64, saved_state.asregs.msize / 64);
|
|
|
|
|
|
|
|
if (!saved_state.asregs.memory)
|
|
|
|
{
|
|
|
|
fprintf (stderr,
|
|
|
|
"Not enough VM for simuation of %d bytes of RAM\n",
|
|
|
|
saved_state.asregs.msize);
|
|
|
|
|
|
|
|
saved_state.asregs.msize = 1;
|
1993-06-18 20:53:58 +00:00
|
|
|
saved_state.asregs.memory = (unsigned char *) calloc (1, 1);
|
1993-06-18 01:31:54 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
1993-06-18 20:53:58 +00:00
|
|
|
static
|
1993-06-18 01:31:54 +00:00
|
|
|
void
|
|
|
|
init_pointers ()
|
|
|
|
{
|
|
|
|
if (saved_state.asregs.msize != 1 << sim_memory_size)
|
|
|
|
{
|
|
|
|
sim_size (sim_memory_size);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (saved_state.asregs.profile && !profile_file)
|
|
|
|
{
|
1993-06-18 20:53:58 +00:00
|
|
|
profile_file = fopen ("gmon.out", "wb");
|
1993-06-18 01:31:54 +00:00
|
|
|
/* Seek to where to put the call arc data */
|
1993-06-18 20:53:58 +00:00
|
|
|
nsamples = (1 << sim_profile_size);
|
1993-06-18 01:31:54 +00:00
|
|
|
|
1993-06-18 20:53:58 +00:00
|
|
|
fseek (profile_file, nsamples * 2 + 12, 0);
|
|
|
|
|
|
|
|
if (!profile_file)
|
1993-06-18 01:31:54 +00:00
|
|
|
{
|
1993-06-18 20:53:58 +00:00
|
|
|
fprintf (stderr, "Can't open gmon.out\n");
|
1993-06-18 01:31:54 +00:00
|
|
|
}
|
1993-06-18 20:53:58 +00:00
|
|
|
else
|
1993-06-18 01:31:54 +00:00
|
|
|
{
|
|
|
|
saved_state.asregs.profile_hist =
|
1993-06-18 20:53:58 +00:00
|
|
|
(unsigned short *) calloc (64, (nsamples * sizeof (short) / 64));
|
1993-06-18 01:31:54 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
1993-06-18 20:53:58 +00:00
|
|
|
dump_profile ()
|
1993-06-18 01:31:54 +00:00
|
|
|
{
|
1993-06-18 20:53:58 +00:00
|
|
|
unsigned int minpc;
|
1993-06-18 01:31:54 +00:00
|
|
|
unsigned int maxpc;
|
|
|
|
unsigned short *p;
|
|
|
|
|
|
|
|
int thisshift;
|
1993-06-18 20:53:58 +00:00
|
|
|
|
1993-06-18 01:31:54 +00:00
|
|
|
unsigned short *first;
|
|
|
|
|
|
|
|
int i;
|
|
|
|
p = saved_state.asregs.profile_hist;
|
1993-06-18 20:53:58 +00:00
|
|
|
minpc = 0;
|
|
|
|
maxpc = (1 << sim_profile_size);
|
|
|
|
|
|
|
|
fseek (profile_file, 0L, 0);
|
|
|
|
swapout (minpc << PROFILE_SHIFT);
|
|
|
|
swapout (maxpc << PROFILE_SHIFT);
|
|
|
|
swapout (nsamples * 2 + 12);
|
|
|
|
for (i = 0; i < nsamples; i++)
|
|
|
|
swapout16 (saved_state.asregs.profile_hist[i]);
|
|
|
|
|
1993-06-18 01:31:54 +00:00
|
|
|
}
|
|
|
|
|
1993-06-18 20:53:58 +00:00
|
|
|
static int
|
|
|
|
gotcall (from, to)
|
1993-06-18 01:31:54 +00:00
|
|
|
int from;
|
|
|
|
int to;
|
|
|
|
{
|
1993-06-18 20:53:58 +00:00
|
|
|
swapout (from);
|
|
|
|
swapout (to);
|
|
|
|
swapout (1);
|
1993-06-18 01:31:54 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
#define MMASKB ((saved_state.asregs.msize -1) & ~0)
|
|
|
|
void
|
1993-04-27 01:02:38 +00:00
|
|
|
sim_resume (step)
|
1993-06-18 01:31:54 +00:00
|
|
|
int step;
|
1993-04-27 01:02:38 +00:00
|
|
|
{
|
1993-06-18 20:53:58 +00:00
|
|
|
register unsigned int pc;
|
1993-06-18 01:31:54 +00:00
|
|
|
register int cycles = 0;
|
|
|
|
register int stalls = 0;
|
|
|
|
register int insts = 0;
|
|
|
|
register int prevlock;
|
1993-06-18 20:53:58 +00:00
|
|
|
register int thislock;
|
|
|
|
register unsigned int doprofile;
|
1993-06-18 01:31:54 +00:00
|
|
|
|
1993-04-27 01:02:38 +00:00
|
|
|
int tick_start = get_now ();
|
|
|
|
void (*prev) ();
|
|
|
|
extern unsigned char sh_jump_table0[];
|
|
|
|
|
|
|
|
register unsigned char *jump_table = sh_jump_table0;
|
|
|
|
|
|
|
|
register int *R = &(saved_state.asregs.regs[0]);
|
|
|
|
register int T;
|
|
|
|
register int PR;
|
|
|
|
|
1993-06-18 01:31:54 +00:00
|
|
|
register int maskb = ((saved_state.asregs.msize - 1) & ~0);
|
|
|
|
register int maskw = ((saved_state.asregs.msize - 1) & ~1);
|
|
|
|
register int maskl = ((saved_state.asregs.msize - 1) & ~3);
|
1993-04-27 01:02:38 +00:00
|
|
|
register unsigned char *memory = saved_state.asregs.memory;
|
1993-06-18 01:31:54 +00:00
|
|
|
register unsigned int sbit = (1 << 31);
|
|
|
|
|
1993-04-27 01:02:38 +00:00
|
|
|
prev = signal (SIGINT, control_c);
|
|
|
|
|
1993-06-18 20:53:58 +00:00
|
|
|
init_pointers ();
|
|
|
|
|
1993-04-27 01:02:38 +00:00
|
|
|
if (step)
|
|
|
|
{
|
|
|
|
saved_state.asregs.exception = SIGTRAP;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
saved_state.asregs.exception = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
pc = saved_state.asregs.pc;
|
|
|
|
PR = saved_state.asregs.pr;
|
|
|
|
T = saved_state.asregs.sr.bits.t;
|
1993-06-18 01:31:54 +00:00
|
|
|
prevlock = saved_state.asregs.prevlock;
|
|
|
|
thislock = saved_state.asregs.thislock;
|
|
|
|
doprofile = saved_state.asregs.profile;
|
|
|
|
|
|
|
|
/* If profiling not enabled, disable it by asking for
|
|
|
|
profiles infrequently. */
|
1993-06-18 20:53:58 +00:00
|
|
|
if (doprofile == 0)
|
1993-06-18 01:31:54 +00:00
|
|
|
doprofile = ~0;
|
1993-06-18 20:53:58 +00:00
|
|
|
|
1993-04-27 01:02:38 +00:00
|
|
|
do
|
|
|
|
{
|
1993-06-18 20:53:58 +00:00
|
|
|
register unsigned int iword = RUWAT (pc);
|
|
|
|
register unsigned int ult;
|
1993-04-27 01:02:38 +00:00
|
|
|
|
|
|
|
insts++;
|
|
|
|
top:
|
|
|
|
|
|
|
|
#include "code.c"
|
|
|
|
|
1993-06-18 01:31:54 +00:00
|
|
|
|
1993-04-27 01:02:38 +00:00
|
|
|
pc += 2;
|
1993-06-18 01:31:54 +00:00
|
|
|
prevlock = thislock;
|
|
|
|
thislock = 30;
|
1993-04-27 01:02:38 +00:00
|
|
|
cycles++;
|
1993-06-18 01:31:54 +00:00
|
|
|
|
|
|
|
if (cycles >= doprofile)
|
|
|
|
{
|
|
|
|
saved_state.asregs.cycles += doprofile;
|
|
|
|
cycles -= doprofile;
|
1993-06-18 20:53:58 +00:00
|
|
|
if (saved_state.asregs.profile_hist)
|
1993-06-18 01:31:54 +00:00
|
|
|
{
|
|
|
|
int n = pc >> PROFILE_SHIFT;
|
1993-06-18 20:53:58 +00:00
|
|
|
if (n < nsamples)
|
1993-06-18 01:31:54 +00:00
|
|
|
{
|
|
|
|
int i = saved_state.asregs.profile_hist[n];
|
|
|
|
if (i < 65000)
|
1993-06-18 20:53:58 +00:00
|
|
|
saved_state.asregs.profile_hist[n] = i + 1;
|
1993-06-18 01:31:54 +00:00
|
|
|
}
|
1993-06-18 20:53:58 +00:00
|
|
|
|
1993-06-18 01:31:54 +00:00
|
|
|
}
|
|
|
|
}
|
1993-04-27 01:02:38 +00:00
|
|
|
}
|
|
|
|
while (!saved_state.asregs.exception);
|
|
|
|
|
1993-06-18 01:31:54 +00:00
|
|
|
if (saved_state.asregs.exception == SIGILL)
|
1993-04-27 01:02:38 +00:00
|
|
|
{
|
1993-06-18 01:31:54 +00:00
|
|
|
pc -= 2;
|
1993-04-27 01:02:38 +00:00
|
|
|
}
|
1993-06-18 01:31:54 +00:00
|
|
|
|
1993-04-27 01:02:38 +00:00
|
|
|
saved_state.asregs.ticks += get_now () - tick_start;
|
|
|
|
saved_state.asregs.cycles += cycles;
|
1993-06-18 01:31:54 +00:00
|
|
|
saved_state.asregs.stalls += stalls;
|
1993-04-27 01:02:38 +00:00
|
|
|
saved_state.asregs.insts += insts;
|
|
|
|
saved_state.asregs.pc = pc;
|
|
|
|
saved_state.asregs.sr.bits.t = T;
|
|
|
|
saved_state.asregs.pr = PR;
|
|
|
|
|
1993-06-18 01:31:54 +00:00
|
|
|
saved_state.asregs.prevlock = prevlock;
|
|
|
|
saved_state.asregs.thislock = thislock;
|
|
|
|
|
|
|
|
|
|
|
|
if (profile_file)
|
|
|
|
{
|
1993-06-18 20:53:58 +00:00
|
|
|
dump_profile ();
|
1993-06-18 01:31:54 +00:00
|
|
|
}
|
1993-06-18 20:53:58 +00:00
|
|
|
|
1993-04-27 01:02:38 +00:00
|
|
|
signal (SIGINT, prev);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
1993-06-18 01:31:54 +00:00
|
|
|
|
1993-04-27 01:02:38 +00:00
|
|
|
void
|
|
|
|
sim_write (addr, buffer, size)
|
|
|
|
long int addr;
|
|
|
|
unsigned char *buffer;
|
|
|
|
int size;
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
init_pointers ();
|
|
|
|
|
|
|
|
for (i = 0; i < size; i++)
|
|
|
|
{
|
|
|
|
saved_state.asregs.memory[MMASKB & (addr + i)] = buffer[i];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
sim_read (addr, buffer, size)
|
|
|
|
long int addr;
|
|
|
|
char *buffer;
|
|
|
|
int size;
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
init_pointers ();
|
|
|
|
|
|
|
|
for (i = 0; i < size; i++)
|
|
|
|
{
|
|
|
|
buffer[i] = saved_state.asregs.memory[MMASKB & (addr + i)];
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
1993-06-18 01:31:54 +00:00
|
|
|
void
|
1993-04-27 01:02:38 +00:00
|
|
|
sim_store_register (rn, value)
|
|
|
|
int rn;
|
|
|
|
int value;
|
|
|
|
{
|
|
|
|
saved_state.asregs.regs[rn] = value;
|
|
|
|
}
|
|
|
|
|
1993-06-18 01:31:54 +00:00
|
|
|
void
|
1993-04-27 01:02:38 +00:00
|
|
|
sim_fetch_register (rn, buf)
|
|
|
|
int rn;
|
|
|
|
char *buf;
|
|
|
|
{
|
|
|
|
int value = ((int *) (&saved_state))[rn];
|
|
|
|
|
1993-06-18 20:53:58 +00:00
|
|
|
swap (buf, value);
|
1993-04-27 01:02:38 +00:00
|
|
|
}
|
|
|
|
|
1993-06-18 01:31:54 +00:00
|
|
|
|
1993-04-27 01:02:38 +00:00
|
|
|
int
|
|
|
|
sim_trace ()
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
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1993-06-18 01:31:54 +00:00
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int
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1993-04-27 01:02:38 +00:00
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sim_stop_signal ()
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{
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return saved_state.asregs.exception;
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}
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1993-06-18 01:31:54 +00:00
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void
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1993-04-27 01:02:38 +00:00
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sim_set_pc (x)
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1993-06-18 01:31:54 +00:00
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int x;
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1993-04-27 01:02:38 +00:00
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{
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saved_state.asregs.pc = x;
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}
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1993-06-18 01:31:54 +00:00
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void
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1993-04-27 01:02:38 +00:00
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sim_info ()
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{
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double timetaken = (double) saved_state.asregs.ticks / (double) now_persec ();
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1993-06-18 01:31:54 +00:00
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double virttime = saved_state.asregs.cycles / 36.0e6;
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printf ("\n\n# instructions executed %10d\n", saved_state.asregs.insts);
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1993-06-18 20:53:58 +00:00
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printf ("# cycles %10d\n", saved_state.asregs.cycles);
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1993-06-18 01:31:54 +00:00
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printf ("# pipeline stalls %10d\n", saved_state.asregs.stalls);
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printf ("# real time taken %10.4f\n", timetaken);
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printf ("# virtual time taked %10.4f\n", virttime);
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printf ("# profiling size %10d\n", sim_profile_size);
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1993-06-18 20:53:58 +00:00
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printf ("# profiling frequency %10d\n", saved_state.asregs.profile);
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printf ("# profile maxpc %10x\n", (1 << sim_profile_size) << PROFILE_SHIFT);
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if (timetaken != 0)
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1993-06-18 01:31:54 +00:00
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{
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printf ("# cycles/second %10d\n", (int) (saved_state.asregs.cycles / timetaken));
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printf ("# simulation ratio %10.4f\n", virttime / timetaken);
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}
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1993-04-27 01:02:38 +00:00
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}
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1993-06-18 01:31:54 +00:00
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void
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1993-06-18 20:53:58 +00:00
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sim_set_profile (n)
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1993-04-27 01:02:38 +00:00
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{
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1993-06-18 01:31:54 +00:00
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saved_state.asregs.profile = n;
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}
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void
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1993-06-18 20:53:58 +00:00
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sim_set_profile_size (n)
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1993-06-18 01:31:54 +00:00
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{
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sim_profile_size = n;
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1993-04-27 01:02:38 +00:00
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}
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