1997-09-16 07:01:57 +00:00
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.macro start
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.text
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.globl _start
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_start:
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.endm
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.macro exit47
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mov 1, r6
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addi 47, r0, r7
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trap 31
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.endm
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.macro exit0
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mov 1, r6
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mov 0, r7
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trap 31
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.endm
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1997-09-17 03:31:09 +00:00
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.macro load reg val
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1997-09-16 07:01:57 +00:00
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jr 1f
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.align 2
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1: jarl 2f, \reg
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.long \val
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2: ld.w 0[\reg], \reg
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.endm
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1997-09-17 03:31:09 +00:00
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.macro check1 reg val
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jr 1f
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.align 2
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1: jarl 2f, r1
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.long \val
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2: ld.w 0[r1], r1
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cmp r1, \reg
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be 1f
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exit47
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1:
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.endm
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1997-09-19 06:40:11 +00:00
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.macro check1x sts reg val
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jr 1f
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.align 2
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1: jarl 2f, r1
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.long \val
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2: ld.w 0[r1], r1
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cmp r1, \reg
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be 1f
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mov 1, r6
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addi \sts, r0, r7
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trap 31
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1:
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.endm
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# definitions of various PSW bits
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PSW_US = 0x100
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PSW_NP = 0x80
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PSW_EP = 0x40
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PSW_ID = 0x20
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PSW_SAT = 0x10
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PSW_CY = 0x8
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PSW_OV = 0x4
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PSW_S = 0x2
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PSW_Z = 0x1
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1997-09-23 08:40:55 +00:00
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# definitions of various interrupt addresses
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INT_RESET = 0x0
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INT_NMI = 0x10
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