old-cross-binutils/sim/arm/armvirt.c

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/* armvirt.c -- ARMulator virtual memory interace: ARM6 Instruction Emulator.
Copyright (C) 1994 Advanced RISC Machines Ltd.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
/* This file contains a complete ARMulator memory model, modelling a
"virtual memory" system. A much simpler model can be found in armfast.c,
and that model goes faster too, but has a fixed amount of memory. This
model's memory has 64K pages, allocated on demand from a 64K entry page
table. The routines PutWord and GetWord implement this. Pages are never
freed as they might be needed again. A single area of memory may be
defined to generate aborts. */
#include "armopts.h"
#include "armos.h"
#include "armdefs.h"
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#include "ansidecl.h"
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#ifdef VALIDATE /* for running the validate suite */
#define TUBE 48 * 1024 * 1024 /* write a char on the screen */
#define ABORTS 1
#endif
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/* #define ABORTS */
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#ifdef ABORTS /* the memory system will abort */
/* For the old test suite Abort between 32 Kbytes and 32 Mbytes
For the new test suite Abort between 8 Mbytes and 26 Mbytes */
/* #define LOWABORT 32 * 1024
#define HIGHABORT 32 * 1024 * 1024 */
#define LOWABORT 8 * 1024 * 1024
#define HIGHABORT 26 * 1024 * 1024
#endif
#define NUMPAGES 64 * 1024
#define PAGESIZE 64 * 1024
#define PAGEBITS 16
#define OFFSETBITS 0xffff
int SWI_vector_installed = FALSE;
/***************************************************************************\
* Get a Word from Virtual Memory, maybe allocating the page *
\***************************************************************************/
static ARMword
GetWord (ARMul_State * state, ARMword address, int check)
{
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ARMword page;
ARMword offset;
ARMword **pagetable;
ARMword *pageptr;
if (check && state->is_XScale)
XScale_check_memacc (state, &address, 0);
* XScale coprocessor support. 2001-04-18 matthew green <mrg@redhat.com> * armcopro.c (write_cp15_reg): Set CHANGEMODE if endianness changes. (read_cp15_reg): Make non-static. (XScale_cp15_LDC): Update for write_cp15_reg() change. (XScale_cp15_MCR): Likewise. (XScale_cp15_write_reg): Likewise. (XScale_check_memacc): New function. Check for breakpoints being activated by memory accesses. Does not support the Branch Target Buffer. (XScale_set_fsr_far): New function. Set FSR and FAR for XScale. (XScale_debug_moe): New function. Set the debug Method Of Entry, if configured. (write_cp14_reg): Reset count counter if requested. * armdefs.h (struct ARMul_State): New members `LastTime' and `CP14R0_CCD' used for the timer/counters. (ARMul_CP13_R0_FIQ, ARMul_CP13_R0_IRQ, ARMul_CP13_R8_PMUS, ARMul_CP14_R0_ENABLE, ARMul_CP14_R0_CLKRST, ARMul_CP14_R0_CCD, ARMul_CP14_R0_INTEN0, ARMul_CP14_R0_INTEN1, ARMul_CP14_R0_INTEN2, ARMul_CP14_R0_FLAG0, ARMul_CP14_R0_FLAG1, ARMul_CP14_R0_FLAG2, ARMul_CP14_R10_MOE_IB, ARMul_CP14_R10_MOE_DB, ARMul_CP14_R10_MOE_BT, ARMul_CP15_R1_ENDIAN, ARMul_CP15_R1_ALIGN, ARMul_CP15_R5_X, ARMul_CP15_R5_ST_ALIGN, ARMul_CP15_R5_IMPRE, ARMul_CP15_R5_MMU_EXCPT, ARMul_CP15_DBCON_M, ARMul_CP15_DBCON_E1, ARMul_CP15_DBCON_E0): New defines for XScale registers. (XScale_check_memacc, XScale_set_fsr_far, XScale_debug_moe): Prototype. (ARMul_Emulate32, ARMul_Emulate26): Clean up function definition. (ARMul_Emulate32): Handle the clock counter and hardware instruction breakpoints. Call XScale_set_fsr_far() for software breakpoints and software interrupts. (LoadMult): Call XScale_set_fsr_far() for data aborts. (LoadSMult): Likewise. (StoreMult): Likewise. (StoreSMult): Likewise. * armemu.h (write_cp15_reg): Update prototype. * arminit.c (ARMul_NewState): Initialise CP14R0_CCD and LastTime. (ARMul_Abort): If XScale, check for FIQ and IRQ being enabled in CP13 register 0. * armvirt.c (GetWord): Call XScale_check_memacc(). (PutWord): Likewise.
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page = address >> PAGEBITS;
offset = (address & OFFSETBITS) >> 2;
pagetable = (ARMword **) state->MemDataPtr;
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pageptr = *(pagetable + page);
if (pageptr == NULL)
{
pageptr = (ARMword *) malloc (PAGESIZE);
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if (pageptr == NULL)
{
perror ("ARMulator can't allocate VM page");
exit (12);
}
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*(pagetable + page) = pageptr;
}
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return *(pageptr + offset);
}
/***************************************************************************\
* Put a Word into Virtual Memory, maybe allocating the page *
\***************************************************************************/
static void
PutWord (ARMul_State * state, ARMword address, ARMword data, int check)
{
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ARMword page;
ARMword offset;
ARMword **pagetable;
ARMword *pageptr;
if (check && state->is_XScale)
XScale_check_memacc (state, &address, 1);
* XScale coprocessor support. 2001-04-18 matthew green <mrg@redhat.com> * armcopro.c (write_cp15_reg): Set CHANGEMODE if endianness changes. (read_cp15_reg): Make non-static. (XScale_cp15_LDC): Update for write_cp15_reg() change. (XScale_cp15_MCR): Likewise. (XScale_cp15_write_reg): Likewise. (XScale_check_memacc): New function. Check for breakpoints being activated by memory accesses. Does not support the Branch Target Buffer. (XScale_set_fsr_far): New function. Set FSR and FAR for XScale. (XScale_debug_moe): New function. Set the debug Method Of Entry, if configured. (write_cp14_reg): Reset count counter if requested. * armdefs.h (struct ARMul_State): New members `LastTime' and `CP14R0_CCD' used for the timer/counters. (ARMul_CP13_R0_FIQ, ARMul_CP13_R0_IRQ, ARMul_CP13_R8_PMUS, ARMul_CP14_R0_ENABLE, ARMul_CP14_R0_CLKRST, ARMul_CP14_R0_CCD, ARMul_CP14_R0_INTEN0, ARMul_CP14_R0_INTEN1, ARMul_CP14_R0_INTEN2, ARMul_CP14_R0_FLAG0, ARMul_CP14_R0_FLAG1, ARMul_CP14_R0_FLAG2, ARMul_CP14_R10_MOE_IB, ARMul_CP14_R10_MOE_DB, ARMul_CP14_R10_MOE_BT, ARMul_CP15_R1_ENDIAN, ARMul_CP15_R1_ALIGN, ARMul_CP15_R5_X, ARMul_CP15_R5_ST_ALIGN, ARMul_CP15_R5_IMPRE, ARMul_CP15_R5_MMU_EXCPT, ARMul_CP15_DBCON_M, ARMul_CP15_DBCON_E1, ARMul_CP15_DBCON_E0): New defines for XScale registers. (XScale_check_memacc, XScale_set_fsr_far, XScale_debug_moe): Prototype. (ARMul_Emulate32, ARMul_Emulate26): Clean up function definition. (ARMul_Emulate32): Handle the clock counter and hardware instruction breakpoints. Call XScale_set_fsr_far() for software breakpoints and software interrupts. (LoadMult): Call XScale_set_fsr_far() for data aborts. (LoadSMult): Likewise. (StoreMult): Likewise. (StoreSMult): Likewise. * armemu.h (write_cp15_reg): Update prototype. * arminit.c (ARMul_NewState): Initialise CP14R0_CCD and LastTime. (ARMul_Abort): If XScale, check for FIQ and IRQ being enabled in CP13 register 0. * armvirt.c (GetWord): Call XScale_check_memacc(). (PutWord): Likewise.
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page = address >> PAGEBITS;
offset = (address & OFFSETBITS) >> 2;
pagetable = (ARMword **) state->MemDataPtr;
pageptr = *(pagetable + page);
if (pageptr == NULL)
{
pageptr = (ARMword *) malloc (PAGESIZE);
if (pageptr == NULL)
{
perror ("ARMulator can't allocate VM page");
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exit (13);
}
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*(pagetable + page) = pageptr;
}
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if (address == 0x8)
SWI_vector_installed = TRUE;
*(pageptr + offset) = data;
}
/***************************************************************************\
* Initialise the memory interface *
\***************************************************************************/
unsigned
ARMul_MemoryInit (ARMul_State * state, unsigned long initmemsize)
{
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ARMword **pagetable;
unsigned page;
if (initmemsize)
state->MemSize = initmemsize;
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pagetable = (ARMword **) malloc (sizeof (ARMword *) * NUMPAGES);
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if (pagetable == NULL)
return FALSE;
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for (page = 0; page < NUMPAGES; page++)
*(pagetable + page) = NULL;
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state->MemDataPtr = (unsigned char *) pagetable;
ARMul_ConsolePrint (state, ", 4 Gb memory");
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return TRUE;
}
/***************************************************************************\
* Remove the memory interface *
\***************************************************************************/
void
ARMul_MemoryExit (ARMul_State * state)
{
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ARMword page;
ARMword **pagetable;
ARMword *pageptr;
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pagetable = (ARMword **) state->MemDataPtr;
for (page = 0; page < NUMPAGES; page++)
{
pageptr = *(pagetable + page);
if (pageptr != NULL)
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free ((char *) pageptr);
}
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free ((char *) pagetable);
return;
}
/***************************************************************************\
* ReLoad Instruction *
\***************************************************************************/
ARMword
ARMul_ReLoadInstr (ARMul_State * state, ARMword address, ARMword isize)
{
#ifdef ABORTS
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if (address >= LOWABORT && address < HIGHABORT)
{
ARMul_PREFETCHABORT (address);
return ARMul_ABORTWORD;
}
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else
{
ARMul_CLEARABORT;
}
#endif
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if ((isize == 2) && (address & 0x2))
{
/* We return the next two halfwords: */
ARMword lo = GetWord (state, address, FALSE);
ARMword hi = GetWord (state, address + 4, FALSE);
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if (state->bigendSig == HIGH)
return (lo << 16) | (hi >> 16);
else
return ((hi & 0xFFFF) << 16) | (lo >> 16);
}
return GetWord (state, address, TRUE);
}
/***************************************************************************\
* Load Instruction, Sequential Cycle *
\***************************************************************************/
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ARMword ARMul_LoadInstrS (ARMul_State * state, ARMword address, ARMword isize)
{
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state->NumScycles++;
#ifdef HOURGLASS
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if ((state->NumScycles & HOURGLASS_RATE) == 0)
{
HOURGLASS;
}
#endif
return ARMul_ReLoadInstr (state, address, isize);
}
/***************************************************************************\
* Load Instruction, Non Sequential Cycle *
\***************************************************************************/
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ARMword ARMul_LoadInstrN (ARMul_State * state, ARMword address, ARMword isize)
{
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state->NumNcycles++;
return ARMul_ReLoadInstr (state, address, isize);
}
/***************************************************************************\
* Read Word (but don't tell anyone!) *
\***************************************************************************/
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ARMword ARMul_ReadWord (ARMul_State * state, ARMword address)
{
#ifdef ABORTS
if (address >= LOWABORT && address < HIGHABORT)
{
ARMul_DATAABORT (address);
return ARMul_ABORTWORD;
}
else
{
ARMul_CLEARABORT;
}
#endif
return GetWord (state, address, TRUE);
}
/***************************************************************************\
* Load Word, Sequential Cycle *
\***************************************************************************/
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ARMword ARMul_LoadWordS (ARMul_State * state, ARMword address)
{
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state->NumScycles++;
return ARMul_ReadWord (state, address);
}
/***************************************************************************\
* Load Word, Non Sequential Cycle *
\***************************************************************************/
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ARMword ARMul_LoadWordN (ARMul_State * state, ARMword address)
{
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state->NumNcycles++;
return ARMul_ReadWord (state, address);
}
/***************************************************************************\
* Load Halfword, (Non Sequential Cycle) *
\***************************************************************************/
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ARMword ARMul_LoadHalfWord (ARMul_State * state, ARMword address)
{
ARMword temp, offset;
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state->NumNcycles++;
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temp = ARMul_ReadWord (state, address);
offset = (((ARMword) state->bigendSig * 2) ^ (address & 2)) << 3; /* bit offset into the word */
return (temp >> offset) & 0xffff;
}
/***************************************************************************\
* Read Byte (but don't tell anyone!) *
\***************************************************************************/
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ARMword ARMul_ReadByte (ARMul_State * state, ARMword address)
{
ARMword temp, offset;
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temp = ARMul_ReadWord (state, address);
offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3; /* bit offset into the word */
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return (temp >> offset & 0xffL);
}
/***************************************************************************\
* Load Byte, (Non Sequential Cycle) *
\***************************************************************************/
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ARMword ARMul_LoadByte (ARMul_State * state, ARMword address)
{
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state->NumNcycles++;
return ARMul_ReadByte (state, address);
}
/***************************************************************************\
* Write Word (but don't tell anyone!) *
\***************************************************************************/
void
ARMul_WriteWord (ARMul_State * state, ARMword address, ARMword data)
{
#ifdef ABORTS
if (address >= LOWABORT && address < HIGHABORT)
{
ARMul_DATAABORT (address);
return;
}
else
{
ARMul_CLEARABORT;
}
#endif
PutWord (state, address, data, TRUE);
}
/***************************************************************************\
* Store Word, Sequential Cycle *
\***************************************************************************/
void
ARMul_StoreWordS (ARMul_State * state, ARMword address, ARMword data)
{
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state->NumScycles++;
ARMul_WriteWord (state, address, data);
}
/***************************************************************************\
* Store Word, Non Sequential Cycle *
\***************************************************************************/
void
ARMul_StoreWordN (ARMul_State * state, ARMword address, ARMword data)
{
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state->NumNcycles++;
ARMul_WriteWord (state, address, data);
}
/***************************************************************************\
* Store HalfWord, (Non Sequential Cycle) *
\***************************************************************************/
void
ARMul_StoreHalfWord (ARMul_State * state, ARMword address, ARMword data)
{
ARMword temp, offset;
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state->NumNcycles++;
#ifdef VALIDATE
if (address == TUBE)
{
if (data == 4)
state->Emulate = FALSE;
else
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(void) putc ((char) data, stderr); /* Write Char */
return;
}
#endif
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temp = ARMul_ReadWord (state, address);
offset = (((ARMword) state->bigendSig * 2) ^ (address & 2)) << 3; /* bit offset into the word */
PutWord (state, address,
(temp & ~(0xffffL << offset)) | ((data & 0xffffL) << offset),
TRUE);
}
/***************************************************************************\
* Write Byte (but don't tell anyone!) *
\***************************************************************************/
void
ARMul_WriteByte (ARMul_State * state, ARMword address, ARMword data)
{
ARMword temp, offset;
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temp = ARMul_ReadWord (state, address);
offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3; /* bit offset into the word */
PutWord (state, address,
(temp & ~(0xffL << offset)) | ((data & 0xffL) << offset),
TRUE);
}
/***************************************************************************\
* Store Byte, (Non Sequential Cycle) *
\***************************************************************************/
void
ARMul_StoreByte (ARMul_State * state, ARMword address, ARMword data)
{
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state->NumNcycles++;
#ifdef VALIDATE
if (address == TUBE)
{
if (data == 4)
state->Emulate = FALSE;
else
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(void) putc ((char) data, stderr); /* Write Char */
return;
}
#endif
ARMul_WriteByte (state, address, data);
}
/***************************************************************************\
* Swap Word, (Two Non Sequential Cycles) *
\***************************************************************************/
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ARMword ARMul_SwapWord (ARMul_State * state, ARMword address, ARMword data)
{
ARMword temp;
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state->NumNcycles++;
temp = ARMul_ReadWord (state, address);
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state->NumNcycles++;
PutWord (state, address, data, TRUE);
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return temp;
}
/***************************************************************************\
* Swap Byte, (Two Non Sequential Cycles) *
\***************************************************************************/
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ARMword ARMul_SwapByte (ARMul_State * state, ARMword address, ARMword data)
{
ARMword temp;
temp = ARMul_LoadByte (state, address);
ARMul_StoreByte (state, address, data);
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return temp;
}
/***************************************************************************\
* Count I Cycles *
\***************************************************************************/
void
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ARMul_Icycles (ARMul_State * state, unsigned number, ARMword address ATTRIBUTE_UNUSED)
{
state->NumIcycles += number;
ARMul_CLEARABORT;
}
/***************************************************************************\
* Count C Cycles *
\***************************************************************************/
void
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ARMul_Ccycles (ARMul_State * state, unsigned number, ARMword address ATTRIBUTE_UNUSED)
{
state->NumCcycles += number;
ARMul_CLEARABORT;
}
/* Read a byte. Do not check for alignment or access errors. */
ARMword
ARMul_SafeReadByte (ARMul_State * state, ARMword address)
{
ARMword temp, offset;
temp = GetWord (state, address, FALSE);
offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3;
return (temp >> offset & 0xffL);
}
void
ARMul_SafeWriteByte (ARMul_State * state, ARMword address, ARMword data)
{
ARMword temp, offset;
temp = GetWord (state, address, FALSE);
offset = (((ARMword) state->bigendSig * 3) ^ (address & 3)) << 3;
PutWord (state, address,
(temp & ~(0xffL << offset)) | ((data & 0xffL) << offset),
FALSE);
}