1999-05-03 07:29:11 +00:00
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/* mips16-opc.c. Mips16 opcode table.
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2012-05-17 15:13:28 +00:00
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Copyright 1996, 1997, 1998, 2000, 2005, 2006, 2007, 2012
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2009-09-02 07:25:43 +00:00
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Free Software Foundation, Inc.
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1999-05-03 07:29:11 +00:00
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Contributed by Ian Lance Taylor, Cygnus Support
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2007-07-05 09:49:03 +00:00
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This file is part of the GNU opcodes library.
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1999-05-03 07:29:11 +00:00
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2007-07-05 09:49:03 +00:00
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This library is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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1999-05-03 07:29:11 +00:00
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2007-07-05 09:49:03 +00:00
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It is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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License for more details.
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1999-05-03 07:29:11 +00:00
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2007-07-05 09:49:03 +00:00
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the
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Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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1999-05-03 07:29:11 +00:00
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2000-04-14 04:16:58 +00:00
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#include "sysdep.h"
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2012-05-17 15:13:28 +00:00
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#include <stdio.h>
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1999-05-03 07:29:11 +00:00
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#include "opcode/mips.h"
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/* This is the opcodes table for the mips16 processor. The format of
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this table is intentionally identical to the one in mips-opc.c.
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However, the special letters that appear in the argument string are
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different, and the table uses some different flags. */
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/* Use some short hand macros to keep down the length of the lines in
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the opcodes table. */
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#define UBD INSN_UNCOND_BRANCH_DELAY
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2010-07-06 00:02:46 +00:00
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#define UBR MIPS16_INSN_UNCOND_BRANCH
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#define CBR MIPS16_INSN_COND_BRANCH
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1999-05-03 07:29:11 +00:00
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#define WR_x MIPS16_INSN_WRITE_X
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#define WR_y MIPS16_INSN_WRITE_Y
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#define WR_z MIPS16_INSN_WRITE_Z
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#define WR_T MIPS16_INSN_WRITE_T
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#define WR_SP MIPS16_INSN_WRITE_SP
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#define WR_31 MIPS16_INSN_WRITE_31
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#define WR_Y MIPS16_INSN_WRITE_GPR_Y
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#define RD_x MIPS16_INSN_READ_X
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#define RD_y MIPS16_INSN_READ_Y
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#define RD_Z MIPS16_INSN_READ_Z
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#define RD_T MIPS16_INSN_READ_T
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#define RD_SP MIPS16_INSN_READ_SP
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#define RD_31 MIPS16_INSN_READ_31
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#define RD_PC MIPS16_INSN_READ_PC
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#define RD_X MIPS16_INSN_READ_GPR_X
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#define WR_HI INSN_WRITE_HI
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#define WR_LO INSN_WRITE_LO
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#define RD_HI INSN_READ_HI
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#define RD_LO INSN_READ_LO
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2011-07-24 14:04:51 +00:00
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#define NODS INSN_NO_DELAY_SLOT
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#define TRAP INSN_NO_DELAY_SLOT
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1999-05-03 07:29:11 +00:00
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2006-05-14 15:35:22 +00:00
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#define I1 INSN_ISA1
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1999-05-03 07:29:11 +00:00
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#define I3 INSN_ISA3
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2006-05-14 15:35:22 +00:00
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#define I32 INSN_ISA32
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#define I64 INSN_ISA64
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#define T3 INSN_3900
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1999-05-03 07:29:11 +00:00
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2000-12-01 20:06:36 +00:00
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const struct mips_opcode mips16_opcodes[] =
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{
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[ gas/testsuite/ChangeLog ]
2006-05-04 Thiemo Seufer <ths@mips.com>
Nigel Stephens <nigel@mips.com>
* gas/mips/mips.exp: Run mips32-dsp tests only for mips32r2.
* gas/mips/set-arch.d: Adjust according to opcode table changes.
[ include/opcode/ChangeLog ]
2006-05-04 Thiemo Seufer <ths@mips.com>
Nigel Stephens <nigel@mips.com>
David Ung <davidu@mips.com>
* mips.h: Add INSN_SMARTMIPS define.
[ opcodes/ChangeLog ]
2006-05-04 Thiemo Seufer <ths@mips.com>
Nigel Stephens <nigel@mips.com>
David Ung <davidu@mips.com>
* mips-dis.c (mips_arch_choices): Add smartmips instruction
decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release
2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to
MIPS64R2.
* mips-opc.c: fix random typos in comments.
(INSN_SMARTMIPS): New defines.
(mips_builtin_opcodes): Add paired single support for MIPS32R2.
Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd,
flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the
FP_S and FP_D flags to denote single and double register
accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards.
Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1
for MIPS32R2. Add SmartMIPS instructions. Add two-argument
variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to
release 2 ISAs.
* mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
2006-05-04 10:47:05 +00:00
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/* name, args, match, mask, pinfo, pinfo2, membership */
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2006-05-14 15:35:22 +00:00
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{"nop", "", 0x6500, 0xffff, RD_Z, 0, I1 }, /* move $0,$Z */
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{"la", "x,A", 0x0800, 0xf800, WR_x|RD_PC, 0, I1 },
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{"abs", "x,w", 0, (int) M_ABS, INSN_MACRO, 0, I1 },
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{"addiu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0, I1 },
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{"addiu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0, I1 },
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{"addiu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, I1 },
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{"addiu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, I1 },
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{"addiu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0, I1 },
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{"addiu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0, I1 },
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{"addu", "z,v,y", 0xe001, 0xf803, WR_z|RD_x|RD_y, 0, I1 },
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{"addu", "y,x,4", 0x4000, 0xf810, WR_y|RD_x, 0, I1 },
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{"addu", "x,k", 0x4800, 0xf800, WR_x|RD_x, 0, I1 },
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{"addu", "S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, I1 },
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{"addu", "S,S,K", 0x6300, 0xff00, WR_SP|RD_SP, 0, I1 },
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{"addu", "x,P,V", 0x0800, 0xf800, WR_x|RD_PC, 0, I1 },
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{"addu", "x,S,V", 0x0000, 0xf800, WR_x|RD_SP, 0, I1 },
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{"and", "x,y", 0xe80c, 0xf81f, WR_x|RD_x|RD_y, 0, I1 },
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2010-07-06 00:02:46 +00:00
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{"b", "q", 0x1000, 0xf800, UBR, 0, I1 },
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2006-05-14 15:35:22 +00:00
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{"beq", "x,y,p", 0, (int) M_BEQ, INSN_MACRO, 0, I1 },
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{"beq", "x,U,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1 },
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2010-07-06 00:02:46 +00:00
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{"beqz", "x,p", 0x2000, 0xf800, CBR|RD_x, 0, I1 },
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2006-05-14 15:35:22 +00:00
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{"bge", "x,y,p", 0, (int) M_BGE, INSN_MACRO, 0, I1 },
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{"bge", "x,8,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1 },
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{"bgeu", "x,y,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1 },
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{"bgeu", "x,8,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1 },
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{"bgt", "x,y,p", 0, (int) M_BGT, INSN_MACRO, 0, I1 },
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{"bgt", "x,8,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1 },
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{"bgtu", "x,y,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1 },
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{"bgtu", "x,8,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1 },
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{"ble", "x,y,p", 0, (int) M_BLE, INSN_MACRO, 0, I1 },
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{"ble", "x,8,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1 },
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{"bleu", "x,y,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1 },
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{"bleu", "x,8,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1 },
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{"blt", "x,y,p", 0, (int) M_BLT, INSN_MACRO, 0, I1 },
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{"blt", "x,8,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1 },
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{"bltu", "x,y,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1 },
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{"bltu", "x,8,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1 },
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{"bne", "x,y,p", 0, (int) M_BNE, INSN_MACRO, 0, I1 },
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{"bne", "x,U,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1 },
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2010-07-06 00:02:46 +00:00
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{"bnez", "x,p", 0x2800, 0xf800, CBR|RD_x, 0, I1 },
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2006-05-14 15:35:22 +00:00
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{"break", "6", 0xe805, 0xf81f, TRAP, 0, I1 },
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2010-07-06 00:02:46 +00:00
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{"bteqz", "p", 0x6000, 0xff00, CBR|RD_T, 0, I1 },
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{"btnez", "p", 0x6100, 0xff00, CBR|RD_T, 0, I1 },
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2006-05-14 15:35:22 +00:00
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{"cmpi", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0, I1 },
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{"cmp", "x,y", 0xe80a, 0xf81f, WR_T|RD_x|RD_y, 0, I1 },
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{"cmp", "x,U", 0x7000, 0xf800, WR_T|RD_x, 0, I1 },
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2005-01-19 23:31:15 +00:00
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{"dla", "y,E", 0xfe00, 0xff00, WR_y|RD_PC, 0, I3 },
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{"daddiu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, 0, I3 },
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{"daddiu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, 0, I3 },
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{"daddiu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3 },
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{"daddiu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3 },
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{"daddiu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, 0, I3 },
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{"daddiu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, 0, I3 },
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{"daddu", "z,v,y", 0xe000, 0xf803, WR_z|RD_x|RD_y, 0, I3 },
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{"daddu", "y,x,4", 0x4010, 0xf810, WR_y|RD_x, 0, I3 },
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{"daddu", "y,j", 0xfd00, 0xff00, WR_y|RD_y, 0, I3 },
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{"daddu", "S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3 },
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{"daddu", "S,S,K", 0xfb00, 0xff00, WR_SP|RD_SP, 0, I3 },
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{"daddu", "y,P,W", 0xfe00, 0xff00, WR_y|RD_PC, 0, I3 },
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{"daddu", "y,S,W", 0xff00, 0xff00, WR_y|RD_SP, 0, I3 },
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{"ddiv", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 },
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2006-05-14 15:35:22 +00:00
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{"ddiv", "z,v,y", 0, (int) M_DDIV_3, INSN_MACRO, 0, I1 },
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2005-01-19 23:31:15 +00:00
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{"ddivu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 },
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2006-05-14 15:35:22 +00:00
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{"ddivu", "z,v,y", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I1 },
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{"div", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1 },
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{"div", "z,v,y", 0, (int) M_DIV_3, INSN_MACRO, 0, I1 },
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{"divu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1 },
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{"divu", "z,v,y", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1 },
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2005-01-19 23:31:15 +00:00
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{"dmul", "z,v,y", 0, (int) M_DMUL, INSN_MACRO, 0, I3 },
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{"dmult", "x,y", 0xe81c, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 },
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{"dmultu", "x,y", 0xe81d, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 },
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{"drem", "0,x,y", 0xe81e, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 },
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2006-05-14 15:35:22 +00:00
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{"drem", "z,v,y", 0, (int) M_DREM_3, INSN_MACRO, 0, I1 },
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2005-01-19 23:31:15 +00:00
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{"dremu", "0,x,y", 0xe81f, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I3 },
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2006-05-14 15:35:22 +00:00
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{"dremu", "z,v,y", 0, (int) M_DREMU_3, INSN_MACRO, 0, I1 },
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2005-01-19 23:31:15 +00:00
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{"dsllv", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
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{"dsll", "x,w,[", 0x3001, 0xf803, WR_x|RD_y, 0, I3 },
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{"dsll", "y,x", 0xe814, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
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{"dsrav", "y,x", 0xe817, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
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{"dsra", "y,]", 0xe813, 0xf81f, WR_y|RD_y, 0, I3 },
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{"dsra", "y,x", 0xe817, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
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{"dsrlv", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
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{"dsrl", "y,]", 0xe808, 0xf81f, WR_y|RD_y, 0, I3 },
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{"dsrl", "y,x", 0xe816, 0xf81f, WR_y|RD_y|RD_x, 0, I3 },
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{"dsubu", "z,v,y", 0xe002, 0xf803, WR_z|RD_x|RD_y, 0, I3 },
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2006-05-14 15:35:22 +00:00
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{"dsubu", "y,x,4", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I1 },
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{"dsubu", "y,j", 0, (int) M_DSUBU_I_2, INSN_MACRO, 0, I1 },
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{"exit", "L", 0xed09, 0xff1f, TRAP, 0, I1 },
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{"exit", "L", 0xee09, 0xff1f, TRAP, 0, I1 },
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{"exit", "L", 0xef09, 0xff1f, TRAP, 0, I1 },
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{"entry", "l", 0xe809, 0xf81f, TRAP, 0, I1 },
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{"extend", "e", 0xf000, 0xf800, 0, 0, I1 },
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{"jalr", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, I1 },
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{"jalr", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, I1 },
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{"jal", "x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, I1 },
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{"jal", "R,x", 0xe840, 0xf8ff, UBD|WR_31|RD_x, 0, I1 },
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{"jal", "a", 0x1800, 0xfc00, UBD|WR_31, 0, I1 },
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{"jalx", "a", 0x1c00, 0xfc00, UBD|WR_31, 0, I1 },
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{"jr", "x", 0xe800, 0xf8ff, UBD|RD_x, 0, I1 },
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{"jr", "R", 0xe820, 0xffff, UBD|RD_31, 0, I1 },
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{"j", "x", 0xe800, 0xf8ff, UBD|RD_x, 0, I1 },
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{"j", "R", 0xe820, 0xffff, UBD|RD_31, 0, I1 },
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2011-06-29 20:42:48 +00:00
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/* MIPS16e compact branches. We keep them near the ordinary branches
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so that we easily find them when converting a normal branch to a
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compact one. */
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2011-07-24 14:04:51 +00:00
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{"jalrc", "x", 0xe8c0, 0xf8ff, UBR|WR_31|RD_x|NODS, 0, I32 },
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{"jalrc", "R,x", 0xe8c0, 0xf8ff, UBR|WR_31|RD_x|NODS, 0, I32 },
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{"jrc", "x", 0xe880, 0xf8ff, UBR|RD_x|NODS, 0, I32 },
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{"jrc", "R", 0xe8a0, 0xffff, UBR|RD_31|NODS, 0, I32 },
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2006-05-14 15:35:22 +00:00
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{"lb", "y,5(x)", 0x8000, 0xf800, WR_y|RD_x, 0, I1 },
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{"lbu", "y,5(x)", 0xa000, 0xf800, WR_y|RD_x, 0, I1 },
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2005-01-19 23:31:15 +00:00
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{"ld", "y,D(x)", 0x3800, 0xf800, WR_y|RD_x, 0, I3 },
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{"ld", "y,B", 0xfc00, 0xff00, WR_y|RD_PC, 0, I3 },
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{"ld", "y,D(P)", 0xfc00, 0xff00, WR_y|RD_PC, 0, I3 },
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{"ld", "y,D(S)", 0xf800, 0xff00, WR_y|RD_SP, 0, I3 },
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2006-05-14 15:35:22 +00:00
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{"lh", "y,H(x)", 0x8800, 0xf800, WR_y|RD_x, 0, I1 },
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{"lhu", "y,H(x)", 0xa800, 0xf800, WR_y|RD_x, 0, I1 },
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{"li", "x,U", 0x6800, 0xf800, WR_x, 0, I1 },
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{"lw", "y,W(x)", 0x9800, 0xf800, WR_y|RD_x, 0, I1 },
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{"lw", "x,A", 0xb000, 0xf800, WR_x|RD_PC, 0, I1 },
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{"lw", "x,V(P)", 0xb000, 0xf800, WR_x|RD_PC, 0, I1 },
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{"lw", "x,V(S)", 0x9000, 0xf800, WR_x|RD_SP, 0, I1 },
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2005-01-19 23:31:15 +00:00
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{"lwu", "y,W(x)", 0xb800, 0xf800, WR_y|RD_x, 0, I3 },
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2006-05-14 15:35:22 +00:00
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{"mfhi", "x", 0xe810, 0xf8ff, WR_x|RD_HI, 0, I1 },
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{"mflo", "x", 0xe812, 0xf8ff, WR_x|RD_LO, 0, I1 },
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{"move", "y,X", 0x6700, 0xff00, WR_y|RD_X, 0, I1 },
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{"move", "Y,Z", 0x6500, 0xff00, WR_Y|RD_Z, 0, I1 },
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{"mul", "z,v,y", 0, (int) M_MUL, INSN_MACRO, 0, I1 },
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{"mult", "x,y", 0xe818, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1 },
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{"multu", "x,y", 0xe819, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1 },
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{"neg", "x,w", 0xe80b, 0xf81f, WR_x|RD_y, 0, I1 },
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{"not", "x,w", 0xe80f, 0xf81f, WR_x|RD_y, 0, I1 },
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{"or", "x,y", 0xe80d, 0xf81f, WR_x|RD_x|RD_y, 0, I1 },
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{"rem", "0,x,y", 0xe81a, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1 },
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{"rem", "z,v,y", 0, (int) M_REM_3, INSN_MACRO, 0, I1 },
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{"remu", "0,x,y", 0xe81b, 0xf81f, RD_x|RD_y|WR_HI|WR_LO, 0, I1 },
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{"remu", "z,v,y", 0, (int) M_REMU_3, INSN_MACRO, 0, I1 },
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{"sb", "y,5(x)", 0xc000, 0xf800, RD_y|RD_x, 0, I1 },
|
2005-01-19 23:31:15 +00:00
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{"sd", "y,D(x)", 0x7800, 0xf800, RD_y|RD_x, 0, I3 },
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{"sd", "y,D(S)", 0xf900, 0xff00, RD_y|RD_PC, 0, I3 },
|
2006-05-14 15:35:22 +00:00
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{"sd", "R,C(S)", 0xfa00, 0xff00, RD_31|RD_PC, 0, I1 },
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{"sh", "y,H(x)", 0xc800, 0xf800, RD_y|RD_x, 0, I1 },
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{"sllv", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0, I1 },
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{"sll", "x,w,<", 0x3000, 0xf803, WR_x|RD_y, 0, I1 },
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{"sll", "y,x", 0xe804, 0xf81f, WR_y|RD_y|RD_x, 0, I1 },
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{"slti", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0, I1 },
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{"slt", "x,y", 0xe802, 0xf81f, WR_T|RD_x|RD_y, 0, I1 },
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{"slt", "x,8", 0x5000, 0xf800, WR_T|RD_x, 0, I1 },
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{"sltiu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0, I1 },
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{"sltu", "x,y", 0xe803, 0xf81f, WR_T|RD_x|RD_y, 0, I1 },
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{"sltu", "x,8", 0x5800, 0xf800, WR_T|RD_x, 0, I1 },
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{"srav", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0, I1 },
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{"sra", "x,w,<", 0x3003, 0xf803, WR_x|RD_y, 0, I1 },
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{"sra", "y,x", 0xe807, 0xf81f, WR_y|RD_y|RD_x, 0, I1 },
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{"srlv", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0, I1 },
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|
{"srl", "x,w,<", 0x3002, 0xf803, WR_x|RD_y, 0, I1 },
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|
{"srl", "y,x", 0xe806, 0xf81f, WR_y|RD_y|RD_x, 0, I1 },
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|
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|
{"subu", "z,v,y", 0xe003, 0xf803, WR_z|RD_x|RD_y, 0, I1 },
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|
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|
{"subu", "y,x,4", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 },
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|
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|
|
{"subu", "x,k", 0, (int) M_SUBU_I_2, INSN_MACRO,0, I1 },
|
|
|
|
|
{"sw", "y,W(x)", 0xd800, 0xf800, RD_y|RD_x, 0, I1 },
|
|
|
|
|
{"sw", "x,V(S)", 0xd000, 0xf800, RD_x|RD_SP, 0, I1 },
|
|
|
|
|
{"sw", "R,V(S)", 0x6200, 0xff00, RD_31|RD_SP, 0, I1 },
|
|
|
|
|
{"xor", "x,y", 0xe80e, 0xf81f, WR_x|RD_x|RD_y, 0, I1 },
|
2005-06-16 17:01:12 +00:00
|
|
|
/* MIPS16e additions */
|
2011-07-24 14:04:51 +00:00
|
|
|
{"restore", "M", 0x6400, 0xff80, WR_31|RD_SP|WR_SP|NODS, 0, I32 },
|
|
|
|
|
{"save", "m", 0x6480, 0xff80, RD_31|RD_SP|WR_SP|NODS, 0, I32 },
|
2006-05-14 15:35:22 +00:00
|
|
|
{"sdbbp", "6", 0xe801, 0xf81f, TRAP, 0, I32 },
|
|
|
|
|
{"seb", "x", 0xe891, 0xf8ff, WR_x|RD_x, 0, I32 },
|
|
|
|
|
{"seh", "x", 0xe8b1, 0xf8ff, WR_x|RD_x, 0, I32 },
|
|
|
|
|
{"sew", "x", 0xe8d1, 0xf8ff, WR_x|RD_x, 0, I64 },
|
|
|
|
|
{"zeb", "x", 0xe811, 0xf8ff, WR_x|RD_x, 0, I32 },
|
|
|
|
|
{"zeh", "x", 0xe831, 0xf8ff, WR_x|RD_x, 0, I32 },
|
|
|
|
|
{"zew", "x", 0xe851, 0xf8ff, WR_x|RD_x, 0, I64 },
|
1999-05-03 07:29:11 +00:00
|
|
|
};
|
|
|
|
|
|
|
|
|
|
const int bfd_mips16_num_opcodes =
|
|
|
|
|
((sizeof mips16_opcodes) / (sizeof (mips16_opcodes[0])));
|
