280 lines
9.9 KiB
C
280 lines
9.9 KiB
C
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/* tc-i960.h - Basic 80960 instruction formats.
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Copyright (C) 1989, 1990, 1991 Free Software Foundation, Inc.
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This file is part of GAS, the GNU Assembler.
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GAS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 1,
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or (at your option) any later version.
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GAS is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public
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License along with GAS; see the file COPYING. If not, write
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to the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* $Id$ */
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/*
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* The 'COJ' instructions are actually COBR instructions with the 'b' in
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* the mnemonic replaced by a 'j'; they are ALWAYS "de-optimized" if necessary:
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* if the displacement will not fit in 13 bits, the assembler will replace them
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* with the corresponding compare and branch instructions.
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*
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* All of the 'MEMn' instructions are the same format; the 'n' in the name
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* indicates the default index scale factor (the size of the datum operated on).
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*
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* The FBRA formats are not actually an instruction format. They are the
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* "convenience directives" for branching on floating-point comparisons,
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* each of which generates 2 instructions (a 'bno' and one other branch).
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*
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* The CALLJ format is not actually an instruction format. It indicates that
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* the instruction generated (a CTRL-format 'call') should have its relocation
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* specially flagged for link-time replacement with a 'bal' or 'calls' if
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* appropriate.
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*/
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#define TC_I960 1
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/* tailor gas */
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#define SYMBOLS_NEED_BACKPOINTERS
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#define LOCAL_LABELS_FB
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#define WANT_BITFIELDS
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/* tailor the coff format */
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#define OBJ_COFF_SECTION_HEADER_HAS_ALIGNMENT
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#define OBJ_COFF_MAX_AUXENTRIES (2)
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/* other */
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#define CTRL 0
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#define COBR 1
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#define COJ 2
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#define REG 3
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#define MEM1 4
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#define MEM2 5
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#define MEM4 6
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#define MEM8 7
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#define MEM12 8
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#define MEM16 9
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#define FBRA 10
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#define CALLJ 11
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/* Masks for the mode bits in REG format instructions */
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#define M1 0x0800
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#define M2 0x1000
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#define M3 0x2000
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/* Generate the 12-bit opcode for a REG format instruction by placing the
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* high 8 bits in instruction bits 24-31, the low 4 bits in instruction bits
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* 7-10.
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*/
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#define REG_OPC(opc) ((opc & 0xff0) << 20) | ((opc & 0xf) << 7)
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/* Generate a template for a REG format instruction: place the opcode bits
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* in the appropriate fields and OR in mode bits for the operands that will not
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* be used. I.e.,
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* set m1=1, if src1 will not be used
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* set m2=1, if src2 will not be used
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* set m3=1, if dst will not be used
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*
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* Setting the "unused" mode bits to 1 speeds up instruction execution(!).
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* The information is also useful to us because some 1-operand REG instructions
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* use the src1 field, others the dst field; and some 2-operand REG instructions
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* use src1/src2, others src1/dst. The set mode bits enable us to distinguish.
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*/
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#define R_0(opc) ( REG_OPC(opc) | M1 | M2 | M3 ) /* No operands */
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#define R_1(opc) ( REG_OPC(opc) | M2 | M3 ) /* 1 operand: src1 */
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#define R_1D(opc) ( REG_OPC(opc) | M1 | M2 ) /* 1 operand: dst */
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#define R_2(opc) ( REG_OPC(opc) | M3 ) /* 2 ops: src1/src2 */
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#define R_2D(opc) ( REG_OPC(opc) | M2 ) /* 2 ops: src1/dst */
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#define R_3(opc) ( REG_OPC(opc) ) /* 3 operands */
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/* DESCRIPTOR BYTES FOR REGISTER OPERANDS
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*
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* Interpret names as follows:
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* R: global or local register only
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* RS: global, local, or (if target allows) special-function register only
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* RL: global or local register, or integer literal
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* RSL: global, local, or (if target allows) special-function register;
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* or integer literal
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* F: global, local, or floating-point register
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* FL: global, local, or floating-point register; or literal (including
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* floating point)
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*
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* A number appended to a name indicates that registers must be aligned,
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* as follows:
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* 2: register number must be multiple of 2
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* 4: register number must be multiple of 4
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*/
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#define SFR 0x10 /* Mask for the "sfr-OK" bit */
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#define LIT 0x08 /* Mask for the "literal-OK" bit */
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#define FP 0x04 /* Mask for "floating-point-OK" bit */
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/* This macro ors the bits together. Note that 'align' is a mask
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* for the low 0, 1, or 2 bits of the register number, as appropriate.
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*/
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#define OP(align,lit,fp,sfr) ( align | lit | fp | sfr )
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#define R OP( 0, 0, 0, 0 )
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#define RS OP( 0, 0, 0, SFR )
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#define RL OP( 0, LIT, 0, 0 )
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#define RSL OP( 0, LIT, 0, SFR )
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#define F OP( 0, 0, FP, 0 )
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#define FL OP( 0, LIT, FP, 0 )
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#define R2 OP( 1, 0, 0, 0 )
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#define RL2 OP( 1, LIT, 0, 0 )
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#define F2 OP( 1, 0, FP, 0 )
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#define FL2 OP( 1, LIT, FP, 0 )
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#define R4 OP( 3, 0, 0, 0 )
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#define RL4 OP( 3, LIT, 0, 0 )
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#define F4 OP( 3, 0, FP, 0 )
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#define FL4 OP( 3, LIT, FP, 0 )
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#define M 0x7f /* Memory operand (MEMA & MEMB format instructions) */
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/* Macros to extract info from the register operand descriptor byte 'od'.
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*/
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#define SFR_OK(od) (od & SFR) /* TRUE if sfr operand allowed */
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#define LIT_OK(od) (od & LIT) /* TRUE if literal operand allowed */
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#define FP_OK(od) (od & FP) /* TRUE if floating-point op allowed */
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#define REG_ALIGN(od,n) ((od & 0x3 & n) == 0)
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/* TRUE if reg #n is properly aligned */
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#define MEMOP(od) (od == M) /* TRUE if operand is a memory operand*/
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/* Classes of 960 intructions:
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* - each instruction falls into one class.
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* - each target architecture supports one or more classes.
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*
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* EACH CONSTANT MUST CONTAIN 1 AND ONLY 1 SET BIT!: see targ_has_iclass().
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*/
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#define I_BASE 0x01 /* 80960 base instruction set */
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#define I_CX 0x02 /* 80960Cx instruction */
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#define I_DEC 0x04 /* Decimal instruction */
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#define I_FP 0x08 /* Floating point instruction */
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#define I_KX 0x10 /* 80960Kx instruction */
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#define I_MIL 0x20 /* Military instruction */
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/* MEANING OF 'n_other' in the symbol record.
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*
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* If non-zero, the 'n_other' fields indicates either a leaf procedure or
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* a system procedure, as follows:
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*
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* 1 <= n_other <= 32 :
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* The symbol is the entry point to a system procedure.
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* 'n_value' is the address of the entry, as for any other
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* procedure. The system procedure number (which can be used in
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* a 'calls' instruction) is (n_other-1). These entries come from
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* '.sysproc' directives.
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*
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* n_other == N_CALLNAME
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* the symbol is the 'call' entry point to a leaf procedure.
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* The *next* symbol in the symbol table must be the corresponding
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* 'bal' entry point to the procedure (see following). These
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* entries come from '.leafproc' directives in which two different
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* symbols are specified (the first one is represented here).
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*
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*
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* n_other == N_BALNAME
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* the symbol is the 'bal' entry point to a leaf procedure.
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* These entries result from '.leafproc' directives in which only
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* one symbol is specified, or in which the same symbol is
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* specified twice.
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*
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* Note that an N_CALLNAME entry *must* have a corresponding N_BALNAME entry,
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* but not every N_BALNAME entry must have an N_CALLNAME entry.
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*/
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#define N_CALLNAME (-1)
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#define N_BALNAME (-2)
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/* i960 uses a custom relocation record. */
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/* let obj-aout.h know */
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#define CUSTOM_RELOC_FORMAT 1
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/* let a.out.gnu.h know */
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#define N_RELOCATION_INFO_DECLARED 1
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struct relocation_info {
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int r_address; /* File address of item to be relocated */
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unsigned
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r_index:24,/* Index of symbol on which relocation is based*/
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r_pcrel:1, /* 1 => relocate PC-relative; else absolute
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* On i960, pc-relative implies 24-bit
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* address, absolute implies 32-bit.
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*/
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r_length:2, /* Number of bytes to relocate:
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* 0 => 1 byte
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* 1 => 2 bytes
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* 2 => 4 bytes -- only value used for i960
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*/
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r_extern:1,
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r_bsr:1, /* Something for the GNU NS32K assembler */
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r_disp:1, /* Something for the GNU NS32K assembler */
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r_callj:1, /* 1 if relocation target is an i960 'callj' */
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nuthin:1; /* Unused */
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};
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/* hacks for tracking callj's */
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#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
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#define TC_S_IS_SYSPROC(s) ((1<=S_GET_OTHER(s)) && (S_GET_OTHER(s)<=32))
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#define TC_S_IS_BALNAME(s) (S_GET_OTHER(s) == N_BALNAME)
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#define TC_S_IS_CALLNAME(s) (S_GET_OTHER(s) == N_CALLNAME)
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#define TC_S_IS_BADPROC(s) ((S_GET_OTHER(s) != 0) && !TC_S_IS_CALLNAME(s) && !TC_S_IS_BALNAME(s) && !TC_S_IS_SYSPROC(s))
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#define TC_S_SET_SYSPROC(s, p) (S_SET_OTHER((s), (p)+1))
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#define TC_S_GET_SYSPROC(s) (S_GET_OTHER(s)-1)
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#define TC_S_FORCE_TO_BALNAME(s) (S_SET_OTHER((s), N_BALNAME))
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#define TC_S_FORCE_TO_CALLNAME(s) (S_SET_OTHER((s), N_CALLNAME))
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#define TC_S_FORCE_TO_SYSPROC(s) {;}
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#elif defined(OBJ_COFF)
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#define TC_S_IS_SYSPROC(s) (S_GET_STORAGE_CLASS(s) == C_SCALL)
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#define TC_S_IS_BALNAME(s) (SF_GET_BALNAME(s))
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#define TC_S_IS_CALLNAME(s) (SF_GET_CALLNAME(s))
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#define TC_S_IS_BADPROC(s) (TC_S_IS_SYSPROC(s) && TC_S_GET_SYSPROC(s) < 0 && 31 < TC_S_GET_SYSPROC(s))
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#define TC_S_SET_SYSPROC(s, p) ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx = (p))
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#define TC_S_GET_SYSPROC(s) ((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx)
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#define TC_S_FORCE_TO_BALNAME(s) (SF_SET_BALNAME(s))
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#define TC_S_FORCE_TO_CALLNAME(s) (SF_SET_CALLNAME(s))
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#define TC_S_FORCE_TO_SYSPROC(s) (S_SET_STORAGE_CLASS((s), C_SCALL))
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#else /* switch on OBJ */
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you lose
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#endif /* witch on OBJ */
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#ifdef __STDC__
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void brtab_emit(void);
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void reloc_callj(); /* this is really reloc_callj(fixS *fixP) but I don't want to change header inclusion order. */
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void tc_set_bal_of_call(); /* this is really tc_set_bal_of_call(symbolS *callP, symbolS *balP) */
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#else /* __STDC__ */
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void brtab_emit();
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void reloc_callj();
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void tc_set_bal_of_call();
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#endif /* __STDC__ */
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char *_tc_get_bal_of_call(); /* this is really symbolS *tc_get_bal_of_call(symbolS *callP). */
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#define tc_get_bal_of_call(c) ((symbolS *) _tc_get_bal_of_call(c))
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/*
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* Local Variables:
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* comment-column: 0
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* fill-column: 131
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* End:
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*/
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/* end of tp-i960.h */
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