1999-05-03 07:29:11 +00:00
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/* Select disassembly routine for specified architecture.
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2005-03-03 11:52:12 +00:00
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Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
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2004, 2005 Free Software Foundation, Inc.
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1999-05-03 07:29:11 +00:00
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2004-11-08 13:17:43 +00:00
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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1999-05-03 07:29:11 +00:00
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2004-11-08 13:17:43 +00:00
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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1999-05-03 07:29:11 +00:00
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2004-11-08 13:17:43 +00:00
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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1999-05-03 07:29:11 +00:00
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2000-04-14 04:16:58 +00:00
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#include "sysdep.h"
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1999-05-03 07:29:11 +00:00
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#include "dis-asm.h"
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#ifdef ARCH_all
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#define ARCH_a29k
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#define ARCH_alpha
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#define ARCH_arc
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#define ARCH_arm
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2000-03-27 08:39:14 +00:00
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#define ARCH_avr
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2000-07-20 16:46:28 +00:00
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#define ARCH_cris
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2004-07-07 17:28:53 +00:00
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#define ARCH_crx
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1999-05-03 07:29:11 +00:00
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#define ARCH_d10v
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#define ARCH_d30v
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2002-05-28 14:08:47 +00:00
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#define ARCH_dlx
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1999-05-03 07:29:11 +00:00
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#define ARCH_h8300
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#define ARCH_h8500
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#define ARCH_hppa
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2000-02-23 13:52:23 +00:00
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#define ARCH_i370
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1999-05-03 07:29:11 +00:00
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#define ARCH_i386
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2000-07-22 Jason Eckhardt <jle@cygnus.com>
* include/opcode/i860.h (btne, bte, bla): Changed these opcodes
to use sbroff ('r') instead of split16 ('s').
(J, K, L, M): New operand types for 16-bit aligned fields.
(ld.x, {p}fld.x, fst.x, pst.d): Changed these opcodes to
use I, J, K, L, M instead of just I.
(T, U): New operand types for split 16-bit aligned fields.
(st.x): Changed these opcodes to use S, T, U instead of just S.
(andh, andnoth, orh, xorh): Deleted 3-register forms as they do not
exist on the i860.
(pfgt.sd, pfle.sd): Deleted these as they do not exist on the i860.
(pfeq.ss, pfeq.dd): New opcodes.
(st.s): Fixed incorrect mask bits.
(fmlow): Fixed incorrect mask bits.
(fzchkl, pfzchkl): Fixed incorrect mask bits.
(faddz, pfaddz): Fixed incorrect mask bits.
(form, pform): Fixed incorrect mask bits.
(pfld.l): Fixed incorrect mask bits.
(fst.q): Fixed incorrect mask bits.
(all floating point opcodes): Fixed incorrect mask bits for
handling of dual bit.
* include/elf/i860.h: New file.
(elf_i860_reloc_type): Defined ELF32 i860 relocations.
* bfd/cpu-i860.c: Added comments.
* bfd/elf32-i860.c (TARGET_LITTLE_SYM): Defined to
bfd_elf32_i860_little_vec.
(TARGET_LITTLE_NAME): Defined to "elf32-i860-little".
(ELF_MAXPAGESIZE): Changed to 4096.
* bfd/targets.c (bfd_elf32_i860_little_vec): Declaration of
new target.
(bfd_target_vector): Added bfd_elf32_i860_little_vec.
* bfd/config.bfd (i860-stardent-sysv4*, i860-stardent-elf*): Added
config for little endian elf32 i860.
(targ_defvec): Define for the new config above
as "bfd_elf32_i860_little_vec".
(targ_selvecs): Define for the new config above
as "bfd_elf32_i860_vec bfd_elf32_i860_little_vec"
* bfd/configure.in (bfd_elf32_i860_little_vec): Added recognition
of new target vec.
* bfd/configure: Regenerated.
* opcodes/i860-dis.c: New file.
(print_insn_i860): New function.
(print_br_address): New function.
(sign_extend): New function.
(BITWISE_OP): New macro.
(I860_REG_PREFIX): New macro.
(grnames, frnames, crnames): New structures.
* opcodes/disassemble.c (ARCH_i860): Define.
(disassembler): Add check for bfd_arch_i860 to set disassemble
function to print_insn_i860.
* include/dis-asm.h (print_insn_i860): Add prototype.
* opcodes/Makefile.in (CFILES): Added i860-dis.c.
(ALL_MACHINES): Added i860-dis.lo.
(i860-dis.lo): New dependences.
* opcodes/configure.in: New bits for bfd_i860_arch.
* opcodes/configure: Regenerated.
2000-07-28 21:10:20 +00:00
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#define ARCH_i860
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1999-05-03 07:29:11 +00:00
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#define ARCH_i960
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2002-07-19 07:52:40 +00:00
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#define ARCH_ip2k
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2000-04-21 20:22:24 +00:00
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#define ARCH_ia64
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1999-05-03 07:29:11 +00:00
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#define ARCH_fr30
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#define ARCH_m32r
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#define ARCH_m68k
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2000-06-19 01:22:44 +00:00
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#define ARCH_m68hc11
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#define ARCH_m68hc12
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1999-05-03 07:29:11 +00:00
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#define ARCH_m88k
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2004-11-08 13:17:43 +00:00
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#define ARCH_maxq
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1999-05-03 07:29:11 +00:00
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#define ARCH_mcore
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#define ARCH_mips
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2001-10-30 15:20:14 +00:00
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#define ARCH_mmix
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1999-05-03 07:29:11 +00:00
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#define ARCH_mn10200
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#define ARCH_mn10300
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2002-12-30 19:25:13 +00:00
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#define ARCH_msp430
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1999-05-03 07:29:11 +00:00
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#define ARCH_ns32k
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2001-04-27 13:34:20 +00:00
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#define ARCH_openrisc
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2002-01-31 17:33:08 +00:00
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#define ARCH_or32
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2001-02-18 23:33:11 +00:00
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#define ARCH_pdp11
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1999-09-04 17:14:37 +00:00
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#define ARCH_pj
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1999-05-03 07:29:11 +00:00
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#define ARCH_powerpc
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#define ARCH_rs6000
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2001-02-10 00:58:38 +00:00
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#define ARCH_s390
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1999-05-03 07:29:11 +00:00
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#define ARCH_sh
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#define ARCH_sparc
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#define ARCH_tic30
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2002-08-28 10:38:51 +00:00
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#define ARCH_tic4x
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2000-05-06 17:14:34 +00:00
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#define ARCH_tic54x
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1999-05-03 07:29:11 +00:00
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#define ARCH_tic80
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#define ARCH_v850
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#define ARCH_vax
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#define ARCH_w65
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2001-12-08 03:46:03 +00:00
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#define ARCH_xstormy16
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2003-04-01 15:50:31 +00:00
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#define ARCH_xtensa
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1999-05-03 07:29:11 +00:00
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#define ARCH_z8k
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2002-06-18 21:21:05 +00:00
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#define ARCH_frv
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2003-01-03 19:52:23 +00:00
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#define ARCH_iq2000
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Contribute sh64-elf.
2001-10-08 Nick Clifton <nickc@cambridge.redhat.com>
* sh64-opc.c: Regenerate.
2001-03-13 DJ Delorie <dj@redhat.com>
* sh64-opc.h: Rename A_RESV_Fx to A_REUSE_PREV so that its
purpose is more obvious.
* sh64-opc.c (shmedia_table): Ditto.
* sh64-dis.c (initialize_shmedia_opcode_mask_table): Ditto.
(print_insn_shmedia): Ditto.
2001-03-12 DJ Delorie <dj@redhat.com>
* sh64-opc.c: Adjust comments to reflect reality: replace bits
3:0 with zeros (not "reserved"), replace "rrrrrr" with
"gggggg" for two-operand floating point opcodes. Remove
"fsina".
2001-01-08 Hans-Peter Nilsson <hpn@cygnus.com>
* sh64-dis.c (print_insn_shmedia) <failing read_memory_func>:
Correct printing of .byte:s. Return number of printed bytes or
-1; never 0.
(print_insn_sh64x) <not CRT_SH5_ISA16>: Ditto. Print as .byte:s
to next four-byte-alignment if insn or data is not aligned.
2001-01-06 Hans-Peter Nilsson <hpn@cygnus.com>
* sh64-dis.c: Update comments and fix comment formatting.
(initialize_shmedia_opcode_mask_table) <case A_IMMM>:
Abort instead of setting length to 0.
(crange_qsort_cmpb, crange_qsort_cmpl, crange_bsearch_cmpb,
crange_bsearch_cmpl, sh64_get_contents_type,
sh64_address_in_cranges): Move to bfd/elf32-sh64.c.
2001-01-05 Hans-Peter Nilsson <hpn@cygnus.com>
* sh64-opc.c: Remove #if 0:d entries for instructions not found in
SH-5/ST50-023-04: fcosa.s, fsrra.s and prefo.
2000-12-30 Hans-Peter Nilsson <hpn@cygnus.com>
* sh64-dis.c (print_insn_shmedia): Display MOVI/SHORI-formed
address with same prefix as SHcompact.
In the disassembler, use a .cranges section for linked executables.
* sh64-dis.c (SAVED_MOVI_R, SAVED_MOVI_IMM): Move to head of file
and update for using structure in info->private_data.
(struct sh64_disassemble_info): New.
(is_shmedia_p): Delete.
(crange_qsort_cmpb): New function.
(crange_qsort_cmpl, crange_bsearch_cmpb): New functions.
(crange_bsearch_cmpl, sh64_address_in_cranges): New functions.
(init_sh64_disasm_info, sh64_get_contents_type_disasm): New functions.
(sh64_get_contents_type, sh64_address_is_shmedia): New functions.
(print_insn_shmedia): Correct displaying of address after MOVI/SHORI
pair. Display addresses for linked executables only.
(print_insn_sh64x_media): Initialize info->private_data by calling
init_sh64_disasm_info.
(print_insn_sh64x): Ditto. Find out type of contents by calling
sh64_contents_type_disasm. Display data regions using ".long" and
".byte" similar to unrecognized opcodes.
2000-12-19 Hans-Peter Nilsson <hpn@cygnus.com>
* sh64-dis.c (is_shmedia_p): Check info->section and look for ISA
information in section flags before considering symbols. Don't
assume an info->mach setting of bfd_mach_sh5 means SHmedia code.
* configure.in (bfd_sh_arch): Check presence of sh64 insns by
matching $target $canon_targets instead of looking at the
now-removed -DINCLUDE_SHMEDIA in $targ_cflags.
* configure: Regenerate.
2000-11-25 Hans-Peter Nilsson <hpn@cygnus.com>
* sh64-opc.c (shmedia_creg_table): New.
* sh64-opc.h (shmedia_creg_info): New type.
(shmedia_creg_table): Declare.
* sh64-dis.c (creg_name): New function.
(print_insn_shmedia): Use it.
* disassemble.c (disassembler) [ARCH_sh, INCLUDE_SHMEDIA]: Map
bfd_mach_sh5 to print_insn_sh64 if big-endian and to
print_insn_sh64l if little-endian.
* sh64-dis.c (print_insn_shmedia): Make r unsigned.
(print_insn_sh64l): New.
(print_insn_sh64x): New.
(print_insn_sh64x_media): New.
(print_insn_sh64): Break out code to print_insn_sh64x and
print_insn_sh64x_media.
2000-11-24 Hans-Peter Nilsson <hpn@cygnus.com>
* sh64-opc.h: New file
* sh64-opc.c: New file
* sh64-dis.c: New file
* Makefile.am: Add sh64 targets.
(HFILES): Add sh64-opc.h.
(CFILES): Add sh64-opc.c and sh64-dis.c.
(ALL_MACHINES): Add sh64 files.
* Makefile.in: Regenerate.
* configure.in: Add support for sh64 to bfd_sh_arch.
* configure: Regenerate.
* disassemble.c [ARCH_all] (INCLUDE_SHMEDIA): Define.
(disassembler) [ARCH_sh, INCLUDE_SHMEDIA]: Map bfd_mach_sh5 to
print_insn_sh64.
* sh-dis.c (print_insn_shx): Handle bfd_mach_sh5 as arch_sh4.
* po/POTFILES.in: Regenerate.
* po/opcodes.pot: Regenerate.
2002-02-08 05:51:04 +00:00
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#define INCLUDE_SHMEDIA
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1999-05-03 07:29:11 +00:00
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#endif
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disassembler_ftype
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disassembler (abfd)
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bfd *abfd;
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{
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enum bfd_architecture a = bfd_get_arch (abfd);
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disassembler_ftype disassemble;
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switch (a)
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{
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/* If you add a case to this table, also add it to the
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ARCH_all definition right above this function. */
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#ifdef ARCH_a29k
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case bfd_arch_a29k:
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/* As far as I know we only handle big-endian 29k objects. */
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disassemble = print_insn_big_a29k;
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break;
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#endif
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#ifdef ARCH_alpha
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case bfd_arch_alpha:
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disassemble = print_insn_alpha;
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break;
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#endif
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#ifdef ARCH_arc
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case bfd_arch_arc:
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{
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2001-01-11 21:20:20 +00:00
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disassemble = arc_get_disassembler (abfd);
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1999-05-03 07:29:11 +00:00
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break;
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}
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#endif
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#ifdef ARCH_arm
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case bfd_arch_arm:
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if (bfd_big_endian (abfd))
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disassemble = print_insn_big_arm;
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else
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disassemble = print_insn_little_arm;
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break;
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#endif
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2000-03-27 08:39:14 +00:00
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#ifdef ARCH_avr
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case bfd_arch_avr:
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disassemble = print_insn_avr;
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break;
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#endif
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2000-07-20 16:46:28 +00:00
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#ifdef ARCH_cris
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case bfd_arch_cris:
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2000-09-29 18:17:25 +00:00
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disassemble = cris_get_disassembler (abfd);
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2000-07-20 16:46:28 +00:00
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break;
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2004-07-07 17:28:53 +00:00
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#endif
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#ifdef ARCH_crx
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case bfd_arch_crx:
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disassemble = print_insn_crx;
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break;
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2000-07-20 16:46:28 +00:00
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#endif
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1999-05-03 07:29:11 +00:00
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#ifdef ARCH_d10v
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case bfd_arch_d10v:
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disassemble = print_insn_d10v;
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break;
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#endif
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#ifdef ARCH_d30v
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case bfd_arch_d30v:
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disassemble = print_insn_d30v;
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break;
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#endif
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2002-05-28 14:08:47 +00:00
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#ifdef ARCH_dlx
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case bfd_arch_dlx:
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/* As far as I know we only handle big-endian DLX objects. */
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disassemble = print_insn_dlx;
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break;
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#endif
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1999-05-03 07:29:11 +00:00
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#ifdef ARCH_h8300
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case bfd_arch_h8300:
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2003-05-12 11:57:32 +00:00
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if (bfd_get_mach (abfd) == bfd_mach_h8300h
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|| bfd_get_mach (abfd) == bfd_mach_h8300hn)
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1999-05-03 07:29:11 +00:00
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disassemble = print_insn_h8300h;
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2003-05-12 11:57:32 +00:00
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else if (bfd_get_mach (abfd) == bfd_mach_h8300s
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2003-10-10 22:13:49 +00:00
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|| bfd_get_mach (abfd) == bfd_mach_h8300sn
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2004-06-27 06:31:22 +00:00
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|| bfd_get_mach (abfd) == bfd_mach_h8300sx
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|| bfd_get_mach (abfd) == bfd_mach_h8300sxn)
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1999-05-03 07:29:11 +00:00
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disassemble = print_insn_h8300s;
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2001-01-13 19:45:52 +00:00
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else
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1999-05-03 07:29:11 +00:00
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disassemble = print_insn_h8300;
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break;
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#endif
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#ifdef ARCH_h8500
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case bfd_arch_h8500:
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disassemble = print_insn_h8500;
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break;
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#endif
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#ifdef ARCH_hppa
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case bfd_arch_hppa:
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disassemble = print_insn_hppa;
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break;
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#endif
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2000-02-23 13:52:23 +00:00
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#ifdef ARCH_i370
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case bfd_arch_i370:
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disassemble = print_insn_i370;
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break;
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#endif
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1999-05-03 07:29:11 +00:00
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#ifdef ARCH_i386
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case bfd_arch_i386:
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2001-11-14 03:15:28 +00:00
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disassemble = print_insn_i386;
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1999-05-03 07:29:11 +00:00
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break;
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#endif
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2000-07-22 Jason Eckhardt <jle@cygnus.com>
* include/opcode/i860.h (btne, bte, bla): Changed these opcodes
to use sbroff ('r') instead of split16 ('s').
(J, K, L, M): New operand types for 16-bit aligned fields.
(ld.x, {p}fld.x, fst.x, pst.d): Changed these opcodes to
use I, J, K, L, M instead of just I.
(T, U): New operand types for split 16-bit aligned fields.
(st.x): Changed these opcodes to use S, T, U instead of just S.
(andh, andnoth, orh, xorh): Deleted 3-register forms as they do not
exist on the i860.
(pfgt.sd, pfle.sd): Deleted these as they do not exist on the i860.
(pfeq.ss, pfeq.dd): New opcodes.
(st.s): Fixed incorrect mask bits.
(fmlow): Fixed incorrect mask bits.
(fzchkl, pfzchkl): Fixed incorrect mask bits.
(faddz, pfaddz): Fixed incorrect mask bits.
(form, pform): Fixed incorrect mask bits.
(pfld.l): Fixed incorrect mask bits.
(fst.q): Fixed incorrect mask bits.
(all floating point opcodes): Fixed incorrect mask bits for
handling of dual bit.
* include/elf/i860.h: New file.
(elf_i860_reloc_type): Defined ELF32 i860 relocations.
* bfd/cpu-i860.c: Added comments.
* bfd/elf32-i860.c (TARGET_LITTLE_SYM): Defined to
bfd_elf32_i860_little_vec.
(TARGET_LITTLE_NAME): Defined to "elf32-i860-little".
(ELF_MAXPAGESIZE): Changed to 4096.
* bfd/targets.c (bfd_elf32_i860_little_vec): Declaration of
new target.
(bfd_target_vector): Added bfd_elf32_i860_little_vec.
* bfd/config.bfd (i860-stardent-sysv4*, i860-stardent-elf*): Added
config for little endian elf32 i860.
(targ_defvec): Define for the new config above
as "bfd_elf32_i860_little_vec".
(targ_selvecs): Define for the new config above
as "bfd_elf32_i860_vec bfd_elf32_i860_little_vec"
* bfd/configure.in (bfd_elf32_i860_little_vec): Added recognition
of new target vec.
* bfd/configure: Regenerated.
* opcodes/i860-dis.c: New file.
(print_insn_i860): New function.
(print_br_address): New function.
(sign_extend): New function.
(BITWISE_OP): New macro.
(I860_REG_PREFIX): New macro.
(grnames, frnames, crnames): New structures.
* opcodes/disassemble.c (ARCH_i860): Define.
(disassembler): Add check for bfd_arch_i860 to set disassemble
function to print_insn_i860.
* include/dis-asm.h (print_insn_i860): Add prototype.
* opcodes/Makefile.in (CFILES): Added i860-dis.c.
(ALL_MACHINES): Added i860-dis.lo.
(i860-dis.lo): New dependences.
* opcodes/configure.in: New bits for bfd_i860_arch.
* opcodes/configure: Regenerated.
2000-07-28 21:10:20 +00:00
|
|
|
#ifdef ARCH_i860
|
|
|
|
|
case bfd_arch_i860:
|
|
|
|
|
disassemble = print_insn_i860;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
1999-05-03 07:29:11 +00:00
|
|
|
#ifdef ARCH_i960
|
|
|
|
|
case bfd_arch_i960:
|
|
|
|
|
disassemble = print_insn_i960;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
2000-04-21 20:22:24 +00:00
|
|
|
#ifdef ARCH_ia64
|
|
|
|
|
case bfd_arch_ia64:
|
|
|
|
|
disassemble = print_insn_ia64;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
2002-07-19 07:52:40 +00:00
|
|
|
#ifdef ARCH_ip2k
|
|
|
|
|
case bfd_arch_ip2k:
|
|
|
|
|
disassemble = print_insn_ip2k;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
1999-05-03 07:29:11 +00:00
|
|
|
#ifdef ARCH_fr30
|
|
|
|
|
case bfd_arch_fr30:
|
|
|
|
|
disassemble = print_insn_fr30;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef ARCH_m32r
|
|
|
|
|
case bfd_arch_m32r:
|
|
|
|
|
disassemble = print_insn_m32r;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
2000-06-19 01:22:44 +00:00
|
|
|
#if defined(ARCH_m68hc11) || defined(ARCH_m68hc12)
|
|
|
|
|
case bfd_arch_m68hc11:
|
|
|
|
|
disassemble = print_insn_m68hc11;
|
|
|
|
|
break;
|
|
|
|
|
case bfd_arch_m68hc12:
|
|
|
|
|
disassemble = print_insn_m68hc12;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
1999-05-03 07:29:11 +00:00
|
|
|
#ifdef ARCH_m68k
|
|
|
|
|
case bfd_arch_m68k:
|
|
|
|
|
disassemble = print_insn_m68k;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef ARCH_m88k
|
|
|
|
|
case bfd_arch_m88k:
|
|
|
|
|
disassemble = print_insn_m88k;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
2004-11-08 13:17:43 +00:00
|
|
|
#ifdef ARCH_maxq
|
|
|
|
|
case bfd_arch_maxq:
|
|
|
|
|
disassemble = print_insn_maxq_little;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
2002-12-30 19:25:13 +00:00
|
|
|
#ifdef ARCH_msp430
|
|
|
|
|
case bfd_arch_msp430:
|
|
|
|
|
disassemble = print_insn_msp430;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
1999-05-03 07:29:11 +00:00
|
|
|
#ifdef ARCH_ns32k
|
|
|
|
|
case bfd_arch_ns32k:
|
|
|
|
|
disassemble = print_insn_ns32k;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef ARCH_mcore
|
|
|
|
|
case bfd_arch_mcore:
|
|
|
|
|
disassemble = print_insn_mcore;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef ARCH_mips
|
|
|
|
|
case bfd_arch_mips:
|
|
|
|
|
if (bfd_big_endian (abfd))
|
|
|
|
|
disassemble = print_insn_big_mips;
|
|
|
|
|
else
|
|
|
|
|
disassemble = print_insn_little_mips;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
2001-10-30 15:20:14 +00:00
|
|
|
#ifdef ARCH_mmix
|
|
|
|
|
case bfd_arch_mmix:
|
|
|
|
|
disassemble = print_insn_mmix;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
1999-05-03 07:29:11 +00:00
|
|
|
#ifdef ARCH_mn10200
|
|
|
|
|
case bfd_arch_mn10200:
|
|
|
|
|
disassemble = print_insn_mn10200;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef ARCH_mn10300
|
|
|
|
|
case bfd_arch_mn10300:
|
|
|
|
|
disassemble = print_insn_mn10300;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
2001-04-27 13:34:20 +00:00
|
|
|
#ifdef ARCH_openrisc
|
|
|
|
|
case bfd_arch_openrisc:
|
|
|
|
|
disassemble = print_insn_openrisc;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
2002-01-31 17:33:08 +00:00
|
|
|
#ifdef ARCH_or32
|
|
|
|
|
case bfd_arch_or32:
|
|
|
|
|
if (bfd_big_endian (abfd))
|
|
|
|
|
disassemble = print_insn_big_or32;
|
|
|
|
|
else
|
|
|
|
|
disassemble = print_insn_little_or32;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
2001-02-18 23:33:11 +00:00
|
|
|
#ifdef ARCH_pdp11
|
|
|
|
|
case bfd_arch_pdp11:
|
|
|
|
|
disassemble = print_insn_pdp11;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
1999-09-04 17:14:37 +00:00
|
|
|
#ifdef ARCH_pj
|
|
|
|
|
case bfd_arch_pj:
|
|
|
|
|
disassemble = print_insn_pj;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
1999-05-03 07:29:11 +00:00
|
|
|
#ifdef ARCH_powerpc
|
|
|
|
|
case bfd_arch_powerpc:
|
|
|
|
|
if (bfd_big_endian (abfd))
|
|
|
|
|
disassemble = print_insn_big_powerpc;
|
|
|
|
|
else
|
|
|
|
|
disassemble = print_insn_little_powerpc;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef ARCH_rs6000
|
|
|
|
|
case bfd_arch_rs6000:
|
2000-06-16 20:46:47 +00:00
|
|
|
if (bfd_get_mach (abfd) == bfd_mach_ppc_620)
|
Add XCOFF64 support.
bfd:
* Makefile.am (coff64-rs6000.lo): New rule.
* Makefile.in: Regenerate.
* coff-rs6000.c (xcoff_mkobject, xcoff_copy_private_bfd_data,
xcoff_is_local_label_name, xcoff_rtype2howto,
xcoff_reloc_type_lookup, xcoff_slurp_armap, xcoff_archive_p,
xcoff_read_ar_hdr, xcoff_openr_next_archived_file, xcoff_write_armap,
xcoff_write_archive_contents): No longer static, and prefix with _bfd_.
(NO_COFF_SYMBOLS): Define.
(xcoff64_swap_sym_in, xcoff64_swap_sym_out, xcoff64_swap_aux_in,
xcoff64_swap_aux_out): New functions; handle xcoff symbol tables
internally.
(MINUS_ONE): New macro.
(xcoff_howto_tabl, xcoff_reloc_type_lookup): Add 64 bit POS
relocation.
(coff_SWAP_sym_in, coff_SWAP_sym_out, coff_SWAP_aux_in,
coff_SWAP_aux_out): Map to the new functions.
* coff64-rs6000.c: New file.
* libcoff.h (bfd_coff_backend_data): Add new fields
_bfd_coff_force_symnames_in_strings and
_bfd_coff_debug_string_prefix_length.
(bfd_coff_force_symnames_in_strings,
bfd_coff_debug_string_prefix_length): New macros for above fields.
* coffcode.h (coff_set_arch_mach_hook): Handle XCOFF64 magic.
Set machine to 620 for XCOFF64. Use bfd_coff_swap_sym_in instead
of using coff_swap_sym_in directly.
(FORCE_SYMNAMES_IN_STRINGS): New macro, defined for XCOFF64.
(coff_set_flags) Set magic for XCOFF64.
(coff_compute_section_file_positions): Add symbol name length to
string section length if bfd_coff_debug_string_prefix_length is
true.
(coff_write_object_contents): Don't do reloc overflow for XCOFF64.
(coff_slurp_line_table): Use bfd_coff_swap_lineno_in instead of
using coff_swap_lineno_in directly.
(bfd_coff_backend_data): Add _bfd_coff_force_symnames_in_strings
and _bfd_coff_debug_string_prefix_length fields.
* coffgen.c (coff_fix_symbol_name, coff_write_symbols): Force
symbol names into strings table when
bfd_coff_force_symnames_in_strings is true.
* coffswap.h (MAX_SCNHDR_NRELOC, MAX_SCNHDR_NLNNO, GET_RELOC_VADDR,
SET_RELOC_VADDR): New macros.
(coff_swap_reloc_in, coff_swap_reloc_out): Use above macros.
(coff_swap_aux_in, coff_swap_aux_out): Remove RS6000COFF_C
code.
(coff_swap_aouthdr_in, coff_swap_aouthdr_out): Handle XCOFF64
changes within RS6000COFF_C specific code.
(coff_swap_scnhdr_out): Use PUT_SCNHDR_NLNNO, PUT_SCNHDR_NRELOC,
MAX_SCNHDR_NRELOC, and MAX_SCNHDR_NLNNO.
* reloc.c (bfd_perform_relocation, bfd_install_relocation):
Extend existing hack on target name.
* xcofflink.c (XCOFF_XVECP): Extend existing hack on
target name.
* coff-tic54x.c (ticof): Keep up to date with new fields
in bfd_coff_backend_data.
* config.bfd: Add bfd_powerpc_64_arch to targ_arch and define
targ_selvecs to include rs6000coff64_vec for rs6000.
* configure.in: Add rs6000coff64_vec case.
* cpu-powerpc.c: New bfd_arch_info_type.
gas:
* as.c (parse_args): Allow md_parse_option to override -a listing
option.
* config/obj-coff.c (add_lineno): Change type of offset parameter
from "int" to "bfd_vma."
* config/tc-ppc.c (md_pseudo_table): Add "llong" and "machine."
(ppc_mach, ppc_subseg_align, ppc_target_format): New.
(ppc_change_csect): Align correctly for XCOFF64.
(ppc_machine): New function, which discards "ppc_machine" line.
(ppc_tc): Cons for 8 when code is 64 bit.
(md_apply_fix3): Don't check operand->insert. Handle 64 bit
relocations.
(md_parse_option): Handle -a64 and -a32.
(ppc_xcoff64): New.
* config/tc-ppc.h (TARGET_MACH): Define.
(TARGET_FORMAT): Move to function.
(SUB_SEGMENT_ALIGN): Use ppc_subseg_align.
include:
* include/coff/rs6k64.h: New file.
opcodes:
* configure.in: Add bfd_powerpc_64_arch.
* disassemble.c (disassembler): Use print_insn_big_powerpc for
64 bit code.
2000-04-26 15:09:44 +00:00
|
|
|
disassemble = print_insn_big_powerpc;
|
|
|
|
|
else
|
|
|
|
|
disassemble = print_insn_rs6000;
|
1999-05-03 07:29:11 +00:00
|
|
|
break;
|
|
|
|
|
#endif
|
2001-02-10 00:58:38 +00:00
|
|
|
#ifdef ARCH_s390
|
|
|
|
|
case bfd_arch_s390:
|
|
|
|
|
disassemble = print_insn_s390;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
1999-05-03 07:29:11 +00:00
|
|
|
#ifdef ARCH_sh
|
|
|
|
|
case bfd_arch_sh:
|
2002-05-17 14:36:46 +00:00
|
|
|
disassemble = print_insn_sh;
|
1999-05-03 07:29:11 +00:00
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef ARCH_sparc
|
|
|
|
|
case bfd_arch_sparc:
|
|
|
|
|
disassemble = print_insn_sparc;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef ARCH_tic30
|
|
|
|
|
case bfd_arch_tic30:
|
|
|
|
|
disassemble = print_insn_tic30;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
2002-08-28 10:38:51 +00:00
|
|
|
#ifdef ARCH_tic4x
|
|
|
|
|
case bfd_arch_tic4x:
|
|
|
|
|
disassemble = print_insn_tic4x;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
2000-05-06 17:14:34 +00:00
|
|
|
#ifdef ARCH_tic54x
|
|
|
|
|
case bfd_arch_tic54x:
|
|
|
|
|
disassemble = print_insn_tic54x;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
1999-05-03 07:29:11 +00:00
|
|
|
#ifdef ARCH_tic80
|
|
|
|
|
case bfd_arch_tic80:
|
|
|
|
|
disassemble = print_insn_tic80;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef ARCH_v850
|
|
|
|
|
case bfd_arch_v850:
|
|
|
|
|
disassemble = print_insn_v850;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef ARCH_w65
|
|
|
|
|
case bfd_arch_w65:
|
|
|
|
|
disassemble = print_insn_w65;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
2001-12-08 03:46:03 +00:00
|
|
|
#ifdef ARCH_xstormy16
|
|
|
|
|
case bfd_arch_xstormy16:
|
|
|
|
|
disassemble = print_insn_xstormy16;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
2003-04-01 15:50:31 +00:00
|
|
|
#ifdef ARCH_xtensa
|
|
|
|
|
case bfd_arch_xtensa:
|
|
|
|
|
disassemble = print_insn_xtensa;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
1999-05-03 07:29:11 +00:00
|
|
|
#ifdef ARCH_z8k
|
|
|
|
|
case bfd_arch_z8k:
|
|
|
|
|
if (bfd_get_mach(abfd) == bfd_mach_z8001)
|
|
|
|
|
disassemble = print_insn_z8001;
|
2001-01-13 19:45:52 +00:00
|
|
|
else
|
1999-05-03 07:29:11 +00:00
|
|
|
disassemble = print_insn_z8002;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef ARCH_vax
|
|
|
|
|
case bfd_arch_vax:
|
|
|
|
|
disassemble = print_insn_vax;
|
|
|
|
|
break;
|
2002-06-18 21:21:05 +00:00
|
|
|
#endif
|
|
|
|
|
#ifdef ARCH_frv
|
|
|
|
|
case bfd_arch_frv:
|
|
|
|
|
disassemble = print_insn_frv;
|
|
|
|
|
break;
|
2003-01-03 19:52:23 +00:00
|
|
|
#endif
|
|
|
|
|
#ifdef ARCH_iq2000
|
|
|
|
|
case bfd_arch_iq2000:
|
|
|
|
|
disassemble = print_insn_iq2000;
|
|
|
|
|
break;
|
1999-05-03 07:29:11 +00:00
|
|
|
#endif
|
|
|
|
|
default:
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
return disassemble;
|
|
|
|
|
}
|
2000-01-27 21:44:26 +00:00
|
|
|
|
|
|
|
|
void
|
2000-04-02 06:26:09 +00:00
|
|
|
disassembler_usage (stream)
|
2001-06-23 16:07:06 +00:00
|
|
|
FILE * stream ATTRIBUTE_UNUSED;
|
2000-01-27 21:44:26 +00:00
|
|
|
{
|
2000-01-27 22:17:12 +00:00
|
|
|
#ifdef ARCH_arm
|
|
|
|
|
print_arm_disassembler_options (stream);
|
|
|
|
|
#endif
|
[ binutils/ChangeLog ]
2002-12-27 Chris Demetriou <cgd@broadcom.com>
* doc/binutils.texi (objdump): Document MIPS -M options.
[ gas/testsuite/ChangeLog ]
2002-12-27 Chris Demetriou <cgd@broadcom.com>
* gas/mips/cp0-names-mips32.d: New file.
* gas/mips/cp0-names-mips64.d: New file.
* gas/mips/cp0-names-numeric.d: New file.
* gas/mips/cp0-names-sb1.d: New file.
* gas/mips/cp0-names.s: New file.
* gas/mips/fpr-names-32.d: New file.
* gas/mips/fpr-names-64.d: New file.
* gas/mips/fpr-names-n32.d: New file.
* gas/mips/fpr-names-numeric.d: New file.
* gas/mips/fpr-names.s: New file.
* gas/mips/gpr-names-32.d: New file.
* gas/mips/gpr-names-64.d: New file.
* gas/mips/gpr-names-n32.d: New file.
* gas/mips/gpr-names-numeric.d: New file.
* gas/mips/gpr-names.s: New file.
* gas/mips/mips.exp: Run new tests.
[ include/ChangeLog ]
2002-12-27 Chris Demetriou <cgd@broadcom.com>
* dis-asm.h (print_mips_disassembler_options): Prototype.
[ include/opcode/ChangeLog ]
2002-12-19 Chris Demetriou <cgd@broadcom.com>
* mips.h (OP_OP_COP0, OP_OP_COP1, OP_OP_COP2, OP_OP_COP3)
(OP_OP_LWC1, OP_OP_LWC2, OP_OP_LWC3, OP_OP_LDC1, OP_OP_LDC2)
(OP_OP_LDC3, OP_OP_SWC1, OP_OP_SWC2, OP_OP_SWC3, OP_OP_SDC1)
(OP_OP_SDC2, OP_OP_SDC3): Define.
[ opcodes/ChangeLog ]
2002-12-27 Chris Demetriou <cgd@broadcom.com>
* disassemble.c (disassembler_usage): Add invocation of
print_mips_disassembler_options.
* mips-dis.c (print_mips_disassembler_options)
(set_default_mips_dis_options, parse_mips_dis_option)
(parse_mips_dis_options, choose_abi_by_name, choose_arch_by_name)
(choose_arch_by_number): New functions.
(mips_abi_choice, mips_arch_choice): New structures.
(mips32_reg_names, mips64_reg_names, reg_names): Remove.
(mips_gpr_names_numeric, mips_gpr_names_oldabi)
(mips_gpr_names_newabi, mips_fpr_names_numeric)
(mips_fpr_names_32, mips_fpr_names_n32, mips_fpr_names_64)
(mips_cp0_names_numeric, mips_cp0_names_mips3264)
(mips_cp0_names_sb1, mips_abi_choices, mips_arch_choices)
(mips_processor, mips_isa, mips_gpr_names, mips_fpr_names)
(mips_cp0_names): New variables.
(print_insn_args): Use new variables to print GPR, FPR, and CP0
register names.
(mips_isa_type): Remove.
(print_insn_mips): Remove ISA and CPU setup since it is now done...
(_print_insn_mips): Here. Remove register setup code, and
call set_default_mips_dis_options and parse_mips_dis_options
instead.
(print_mips16_insn_arg): Use mips_gpr_names instead of mips32_names.
2002-12-27 08:00:31 +00:00
|
|
|
#ifdef ARCH_mips
|
|
|
|
|
print_mips_disassembler_options (stream);
|
|
|
|
|
#endif
|
2002-09-04 10:08:08 +00:00
|
|
|
#ifdef ARCH_powerpc
|
|
|
|
|
print_ppc_disassembler_options (stream);
|
|
|
|
|
#endif
|
2001-01-13 19:45:52 +00:00
|
|
|
|
2000-01-27 21:44:26 +00:00
|
|
|
return;
|
|
|
|
|
}
|
2003-11-14 15:12:44 +00:00
|
|
|
|
|
|
|
|
void
|
|
|
|
|
disassemble_init_for_target (struct disassemble_info * info)
|
|
|
|
|
{
|
|
|
|
|
if (info == NULL)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
switch (info->arch)
|
|
|
|
|
{
|
|
|
|
|
#ifdef ARCH_arm
|
|
|
|
|
case bfd_arch_arm:
|
|
|
|
|
info->symbol_is_valid = arm_symbol_is_valid;
|
|
|
|
|
break;
|
2005-01-10 09:54:50 +00:00
|
|
|
#endif
|
|
|
|
|
#ifdef ARCH_ia64
|
|
|
|
|
case bfd_arch_ia64:
|
|
|
|
|
info->skip_zeroes = 16;
|
|
|
|
|
break;
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef ARCH_tic4x
|
|
|
|
|
case bfd_arch_tic4x:
|
|
|
|
|
info->skip_zeroes = 32;
|
2003-11-14 15:12:44 +00:00
|
|
|
#endif
|
|
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
