1999-04-27 01:26:45 +00:00
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/* Native definitions for Intel x86 running DJGPP.
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Copyright (C) 1997, 1998, 1999 Free Software Foundation, Inc.
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1999-07-07 20:19:36 +00:00
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This file is part of GDB.
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1999-04-27 01:26:45 +00:00
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1999-07-07 20:19:36 +00:00
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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1999-04-27 01:26:45 +00:00
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1999-07-07 20:19:36 +00:00
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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1999-04-27 01:26:45 +00:00
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1999-07-07 20:19:36 +00:00
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330,
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Boston, MA 02111-1307, USA. */
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1999-04-27 01:26:45 +00:00
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#define NO_PTRACE_H
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#include "i386/nm-i386v.h"
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#define TARGET_HAS_HARDWARE_WATCHPOINTS
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1999-08-23 22:40:00 +00:00
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/* Returns the number of hardware watchpoints of type TYPE that we can
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set. Value is positive if we can set CNT watchpoints, zero if
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setting watchpoints of type TYPE is not supported, and negative if
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CNT is more than the maximum number of watchpoints of type TYPE
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that we can support. TYPE is one of bp_hardware_watchpoint,
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bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint.
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CNT is the number of such watchpoints used so far (including this
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one). OTHERTYPE is non-zero if other types of watchpoints are
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currently enabled.
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We always return 1 here because we don't have enough information
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about possible overlap of addresses that they want to watch. As
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an extreme example, consider the case where all the watchpoints
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watch the same address and the same region length: then we can
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handle a virtually unlimited number of watchpoints, due to debug
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register sharing implemented via reference counts in go32-nat.c. */
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1999-04-27 01:26:45 +00:00
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#define TARGET_CAN_USE_HARDWARE_WATCHPOINT(type, cnt, ot) 1
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1999-08-23 22:40:00 +00:00
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/* Returns non-zero if we can use hardware watchpoints to watch a region
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whose address is ADDR and whose length is LEN. */
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#define TARGET_REGION_OK_FOR_HW_WATCHPOINT(addr,len) \
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go32_region_ok_for_watchpoint(addr,len)
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2000-02-29 08:16:40 +00:00
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extern int go32_region_ok_for_watchpoint (CORE_ADDR, int);
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1999-08-23 22:40:00 +00:00
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1999-04-27 01:26:45 +00:00
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/* After a watchpoint trap, the PC points to the instruction after the
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one that caused the trap. Therefore we don't need to step over it.
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But we do need to reset the status register to avoid another trap. */
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#define HAVE_CONTINUABLE_WATCHPOINT
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#define STOPPED_BY_WATCHPOINT(W) \
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1999-08-23 22:40:00 +00:00
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go32_stopped_by_watchpoint (inferior_pid, 0)
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#define target_stopped_data_address() \
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go32_stopped_by_watchpoint (inferior_pid, 1)
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2000-02-29 08:16:40 +00:00
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extern CORE_ADDR go32_stopped_by_watchpoint (int, int);
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1999-04-27 01:26:45 +00:00
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/* Use these macros for watchpoint insertion/removal. */
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#define target_insert_watchpoint(addr, len, type) \
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1999-08-23 22:40:00 +00:00
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go32_insert_watchpoint (inferior_pid, addr, len, type)
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2000-02-29 08:16:40 +00:00
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extern int go32_insert_watchpoint (int, CORE_ADDR, int, int);
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1999-04-27 01:26:45 +00:00
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#define target_remove_watchpoint(addr, len, type) \
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1999-08-23 22:40:00 +00:00
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go32_remove_watchpoint (inferior_pid, addr, len, type)
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2000-02-29 08:16:40 +00:00
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extern int go32_remove_watchpoint (int, CORE_ADDR, int, int);
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1999-04-27 01:26:45 +00:00
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#define target_insert_hw_breakpoint(addr, shadow) \
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go32_insert_hw_breakpoint(addr, shadow)
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2000-02-29 08:16:40 +00:00
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extern int go32_insert_hw_breakpoint (CORE_ADDR, void *);
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1999-07-07 20:19:36 +00:00
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1999-04-27 01:26:45 +00:00
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#define target_remove_hw_breakpoint(addr, shadow) \
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go32_remove_hw_breakpoint(addr, shadow)
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2000-02-29 08:16:40 +00:00
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extern int go32_remove_hw_breakpoint (CORE_ADDR, void *);
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1999-04-27 01:26:45 +00:00
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#define DECR_PC_AFTER_HW_BREAK 0
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