bfd:
* Makefile.am (ALL_MACHINES): Add cpu-tic6x.lo.
(ALL_MACHINES_CFILES): Add cpu-tic6x.c.
(BFD32_BACKENDS): Add elf32-tic6x.lo.
(BFD32_BACKENDS_CFILES): Add elf32-tic6x.c.
* Makefile.in: Regenerate.
* archures.c (bfd_arch_tic6x, bfd_tic6x_arch): New.
(bfd_archures_list): Update.
* config.bfd (tic6x-*-elf): New.
* configure.in (bfd_elf32_tic6x_be_vec, bfd_elf32_tic6x_le_vec):
New.
* configure: Regenerate.
* cpu-tic6x.c, elf32-tic6x.c: New.
* reloc.c (BFD_RELOC_C6000_PCR_S21, BFD_RELOC_C6000_PCR_S12,
BFD_RELOC_C6000_PCR_S10, BFD_RELOC_C6000_PCR_S7,
BFD_RELOC_C6000_ABS_S16, BFD_RELOC_C6000_ABS_L16,
BFD_RELOC_C6000_ABS_H16, BFD_RELOC_C6000_SBR_U15_B,
BFD_RELOC_C6000_SBR_U15_H, BFD_RELOC_C6000_SBR_U15_W,
BFD_RELOC_C6000_SBR_S16, BFD_RELOC_C6000_SBR_L16_B,
BFD_RELOC_C6000_SBR_L16_H, BFD_RELOC_C6000_SBR_L16_W,
BFD_RELOC_C6000_SBR_H16_B, BFD_RELOC_C6000_SBR_H16_H,
BFD_RELOC_C6000_SBR_H16_W, BFD_RELOC_C6000_SBR_GOT_U15_W,
BFD_RELOC_C6000_SBR_GOT_L16_W, BFD_RELOC_C6000_SBR_GOT_H16_W,
BFD_RELOC_C6000_DSBT_INDEX, BFD_RELOC_C6000_PREL31,
BFD_RELOC_C6000_COPY, BFD_RELOC_C6000_ALIGN,
BFD_RELOC_C6000_FPHEAD, BFD_RELOC_C6000_NOCMP): New.
* targets.c (bfd_elf32_tic6x_be_vec, bfd_elf32_tic6x_le_vec): New.
(_bfd_target_vector): Update.
* bfd-in2.h, libbfd.h: Regenerate.
binutils:
* MAINTAINERS: Add self as TI C6X maintainer.
* NEWS: Add news entry for TI C6X support.
* readelf.c: Include elf/tic6x.h.
(guess_is_rela): Handle EM_TI_C6000.
(dump_relocations): Likewise.
(get_tic6x_dynamic_type): New.
(get_dynamic_type): Call it.
(get_machine_flags): Handle EF_C6000_REL.
(get_osabi_name): Handle machine-specific values only for relevant
machines. Handle C6X values.
(get_tic6x_segment_type): New.
(get_segment_type): Call it.
(get_tic6x_section_type_name): New.
(get_section_type_name): Call it.
(is_32bit_abs_reloc, is_16bit_abs_reloc, is_none_reloc): Handle
EM_TI_C6000.
gas:
* Makefile.am (TARGET_CPU_CFILES): Add config/tc-tic6x.c.
(TARGET_CPU_HFILES): Add config/tc-tic6x.h.
* Makefile.in: Regenerate.
* NEWS: Add news entry for TI C6X support.
* app.c (do_scrub_chars): Handle "||^" for TI C6X. Handle
TC_PREDICATE_START_CHAR and TC_PREDICATE_END_CHAR. Keep spaces in
operands if TC_KEEP_OPERAND_SPACES.
* configure.tgt (tic6x-*-*): New.
* config/tc-ia64.h (TC_PREDICATE_START_CHAR,
TC_PREDICATE_END_CHAR): Define.
* config/tc-tic6x.c, config/tc-tic6x.h: New.
* doc/Makefile.am (CPU_DOCS): Add c-tic6x.texi.
* doc/Makefile.in: Regenerate.
* doc/all.texi (TIC6X): Define.
* doc/as.texinfo: Add TI C6X documentation. Include c-tic6x.texi.
* doc/c-tic6x.texi: New.
gas/testsuite:
* gas/tic6x: New directory and testcases.
include:
* dis-asm.h (print_insn_tic6x): Declare.
include/elf:
* common.h (ELFOSABI_C6000_ELFABI, ELFOSABI_C6000_LINUX): Define.
* tic6x.h: New.
include/opcode:
* tic6x-control-registers.h, tic6x-insn-formats.h,
tic6x-opcode-table.h, tic6x.h: New.
ld:
* Makefile.am (ALL_EMULATIONS): Add eelf32_tic6x_be.o and
eelf32_tic6x_le.o.
(eelf32_tic6x_be.c, eelf32_tic6x_le.c): New.
* NEWS: Add news entry for TI C6X support.
* configure.tgt (tic6x-*-*): New.
* emulparams/elf32_tic6x_be.sh, emulparams/elf32_tic6x_le.sh: New.
ld/testsuite:
* ld-elf/flags1.d, ld-elf/merge.d: XFAIL for tic6x-*-*.
* ld-elf/sec-to-seg.exp: Set B_test_same_seg to 0 for tic6x-*-*.
* ld-tic6x: New directory and testcases.
opcodes:
* Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
* Makefile.in: Regenerate.
* configure.in (bfd_tic6x_arch): New.
* configure: Regenerate.
* disassemble.c (ARCH_tic6x): Define if ARCH_all.
(disassembler): Handle TI C6X.
* tic6x-dis.c: New.
2010-03-25 21:12:36 +00:00
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/* TI C6X instruction format information.
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Copyright 2010
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Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
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MA 02110-1301, USA. */
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/* Define the FMT macro before including this file; it takes a name
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and the fields from tic6x_insn_format (defined in tic6x.h). */
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#define FLD(name, pos, width) { CONCAT2(tic6x_field_,name), (pos), (width) }
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#define CFLDS FLD(p, 0, 1), FLD(creg, 29, 3), FLD(z, 28, 1)
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#define CFLDS2(a, b) 5, { CFLDS, a, b }
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#define CFLDS3(a, b, c) 6, { CFLDS, a, b, c }
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#define CFLDS4(a, b, c, d) 7, { CFLDS, a, b, c, d }
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#define CFLDS5(a, b, c, d, e) 8, { CFLDS, a, b, c, d, e }
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#define CFLDS6(a, b, c, d, e, f) 9, { CFLDS, a, b, c, d, e, f }
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#define CFLDS7(a, b, c, d, e, f, g) 10, { CFLDS, a, b, c, d, e, f, g }
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#define CFLDS8(a, b, c, d, e, f, g, h) 11, { CFLDS, a, b, c, d, e, f, g, h }
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#define NFLDS FLD(p, 0, 1)
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#define NFLDS1(a) 2, { NFLDS, a }
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#define NFLDS2(a, b) 3, { NFLDS, a, b }
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#define NFLDS3(a, b, c) 4, { NFLDS, a, b, c }
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#define NFLDS5(a, b, c, d, e) 6, { NFLDS, a, b, c, d, e }
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#define NFLDS6(a, b, c, d, e, f) 7, { NFLDS, a, b, c, d, e, f }
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#define NFLDS7(a, b, c, d, e, f, g) 8, { NFLDS, a, b, c, d, e, f, g }
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/* These are in the order from SPRUFE8, appendices C-H. */
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/* Appendix C 32-bit formats. */
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FMT(d_1_or_2_src, 32, 0x40, 0x7c,
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CFLDS5(FLD(s, 1, 1), FLD(op, 7, 6), FLD(src1, 13, 5), FLD(src2, 18, 5),
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FLD(dst, 23, 5)))
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FMT(d_ext_1_or_2_src, 32, 0x830, 0xc3c,
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CFLDS6(FLD(s, 1, 1), FLD(op, 6, 4), FLD(x, 12, 1), FLD(src1, 13, 5),
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FLD(src2, 18, 5), FLD(dst, 23, 5)))
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FMT(d_load_store, 32, 0x4, 0xc,
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CFLDS8(FLD(s, 1, 1), FLD(op, 4, 3), FLD(y, 7, 1), FLD(r, 8, 1),
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FLD(mode, 9, 4), FLD(offsetR, 13, 5), FLD(baseR, 18, 5),
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FLD(srcdst, 23, 5)))
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/* The nonaligned loads and stores have the formats shown in the
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individual instruction descriptions; the appendix is incorrect. */
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FMT(d_load_nonaligned, 32, 0x124, 0x17c,
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CFLDS7(FLD(s, 1, 1), FLD(y, 7, 1), FLD(mode, 9, 4), FLD(offsetR, 13, 5),
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FLD(baseR, 18, 5), FLD(sc, 23, 1), FLD(dst, 24, 4)))
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FMT(d_store_nonaligned, 32, 0x174, 0x17c,
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CFLDS7(FLD(s, 1, 1), FLD(y, 7, 1), FLD(mode, 9, 4), FLD(offsetR, 13, 5),
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FLD(baseR, 18, 5), FLD(sc, 23, 1), FLD(src, 24, 4)))
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FMT(d_load_store_long, 32, 0xc, 0xc,
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CFLDS5(FLD(s, 1, 1), FLD(op, 4, 3), FLD(y, 7, 1), FLD(offsetR, 8, 15),
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FLD(dst, 23, 5)))
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FMT(d_adda_long, 32, 0x1000000c, 0xf000000c,
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NFLDS5(FLD(s, 1, 1), FLD(op, 4, 3), FLD(y, 7, 1), FLD(offsetR, 8, 15),
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FLD(dst, 23, 5)))
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/* Appendix C 16-bit formats will go here. */
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/* Appendix D 32-bit formats. */
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FMT(l_1_or_2_src, 32, 0x18, 0x1c,
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CFLDS6(FLD(s, 1, 1), FLD(op, 5, 7), FLD(x, 12, 1), FLD(src1, 13, 5),
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FLD(src2, 18, 5), FLD(dst, 23, 5)))
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FMT(l_1_or_2_src_noncond, 32, 0x10000018, 0xf000001c,
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NFLDS6(FLD(s, 1, 1), FLD(op, 5, 7), FLD(x, 12, 1), FLD(src1, 13, 5),
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FLD(src2, 18, 5), FLD(dst, 23, 5)))
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FMT(l_unary, 32, 0x358, 0xffc,
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CFLDS5(FLD(s, 1, 1), FLD(x, 12, 1), FLD(op, 13, 5), FLD(src2, 18, 5),
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FLD(dst, 23, 5)))
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/* Appendix D 16-bit formats will go here. */
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/* Appendix E 32-bit formats. */
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FMT(m_compound, 32, 0x30, 0x83c,
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CFLDS6(FLD(s, 1, 1), FLD(op, 6, 5), FLD(x, 12, 1), FLD(src1, 13, 5),
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FLD(src2, 18, 5), FLD(dst, 23, 5)))
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FMT(m_1_or_2_src, 32, 0x10000030, 0xf000083c,
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NFLDS6(FLD(s, 1, 1), FLD(op, 6, 5), FLD(x, 12, 1), FLD(src1, 13, 5),
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FLD(src2, 18, 5), FLD(dst, 23, 5)))
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/* Contrary to SPRUFE8, this does have predicate fields. */
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FMT(m_unary, 32, 0xf0, 0xffc,
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CFLDS5(FLD(s, 1, 1), FLD(x, 12, 1), FLD(op, 13, 5), FLD(src2, 18, 5),
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FLD(dst, 23, 5)))
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/* M-unit formats missing from Appendix E. */
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FMT(m_mpy, 32, 0x0, 0x7c,
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CFLDS6(FLD(s, 1, 1), FLD(op, 7, 5), FLD(x, 12, 1), FLD(src1, 13, 5),
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FLD(src2, 18, 5), FLD(dst, 23, 5)))
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/* Appendix E 16-bit formats will go here. */
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/* Appendix F 32-bit formats. */
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FMT(s_1_or_2_src, 32, 0x20, 0x3c,
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CFLDS6(FLD(s, 1, 1), FLD(op, 6, 6), FLD(x, 12, 1), FLD(src1, 13, 5),
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FLD(src2, 18, 5), FLD(dst, 23 ,5)))
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FMT(s_ext_1_or_2_src, 32, 0xc30, 0xc3c,
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CFLDS6(FLD(s, 1, 1), FLD(op, 6, 4), FLD(x, 12, 1), FLD(src1, 13, 5),
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FLD(src2, 18, 5), FLD(dst, 23, 5)))
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FMT(s_ext_1_or_2_src_noncond, 32, 0xc30, 0xe0000c3c,
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NFLDS7(FLD(s, 1, 1), FLD(op, 6, 4), FLD(x, 12, 1), FLD(src1, 13, 5),
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FLD(src2, 18, 5), FLD(dst, 23, 5), FLD(z, 28, 1)))
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FMT(s_unary, 32, 0xf20, 0xffc,
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CFLDS5(FLD(s, 1, 1), FLD(x, 12, 1), FLD(op, 13, 5), FLD(src2, 18, 5),
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FLD(dst, 23, 5)))
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FMT(s_ext_branch_cond_imm, 32, 0x10, 0x7c,
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CFLDS2(FLD(s, 1, 1), FLD(cst, 7, 21)))
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FMT(s_call_imm_nop, 32, 0x10, 0xe000007c,
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NFLDS3(FLD(s, 1, 1), FLD(cst, 7, 21), FLD(z, 28, 1)))
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FMT(s_branch_nop_cst, 32, 0x120, 0x1ffc,
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CFLDS3(FLD(s, 1, 1), FLD(src1, 13, 3), FLD(src2, 16, 12)))
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FMT(s_branch_nop_reg, 32, 0x800360, 0xf830ffc,
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CFLDS4(FLD(s, 1, 1), FLD(x, 12, 1), FLD(src1, 13, 3), FLD(src2, 18, 5)))
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2010-04-21 18:56:45 +00:00
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FMT(s_branch, 32, 0x360, 0xf83effc,
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bfd:
* Makefile.am (ALL_MACHINES): Add cpu-tic6x.lo.
(ALL_MACHINES_CFILES): Add cpu-tic6x.c.
(BFD32_BACKENDS): Add elf32-tic6x.lo.
(BFD32_BACKENDS_CFILES): Add elf32-tic6x.c.
* Makefile.in: Regenerate.
* archures.c (bfd_arch_tic6x, bfd_tic6x_arch): New.
(bfd_archures_list): Update.
* config.bfd (tic6x-*-elf): New.
* configure.in (bfd_elf32_tic6x_be_vec, bfd_elf32_tic6x_le_vec):
New.
* configure: Regenerate.
* cpu-tic6x.c, elf32-tic6x.c: New.
* reloc.c (BFD_RELOC_C6000_PCR_S21, BFD_RELOC_C6000_PCR_S12,
BFD_RELOC_C6000_PCR_S10, BFD_RELOC_C6000_PCR_S7,
BFD_RELOC_C6000_ABS_S16, BFD_RELOC_C6000_ABS_L16,
BFD_RELOC_C6000_ABS_H16, BFD_RELOC_C6000_SBR_U15_B,
BFD_RELOC_C6000_SBR_U15_H, BFD_RELOC_C6000_SBR_U15_W,
BFD_RELOC_C6000_SBR_S16, BFD_RELOC_C6000_SBR_L16_B,
BFD_RELOC_C6000_SBR_L16_H, BFD_RELOC_C6000_SBR_L16_W,
BFD_RELOC_C6000_SBR_H16_B, BFD_RELOC_C6000_SBR_H16_H,
BFD_RELOC_C6000_SBR_H16_W, BFD_RELOC_C6000_SBR_GOT_U15_W,
BFD_RELOC_C6000_SBR_GOT_L16_W, BFD_RELOC_C6000_SBR_GOT_H16_W,
BFD_RELOC_C6000_DSBT_INDEX, BFD_RELOC_C6000_PREL31,
BFD_RELOC_C6000_COPY, BFD_RELOC_C6000_ALIGN,
BFD_RELOC_C6000_FPHEAD, BFD_RELOC_C6000_NOCMP): New.
* targets.c (bfd_elf32_tic6x_be_vec, bfd_elf32_tic6x_le_vec): New.
(_bfd_target_vector): Update.
* bfd-in2.h, libbfd.h: Regenerate.
binutils:
* MAINTAINERS: Add self as TI C6X maintainer.
* NEWS: Add news entry for TI C6X support.
* readelf.c: Include elf/tic6x.h.
(guess_is_rela): Handle EM_TI_C6000.
(dump_relocations): Likewise.
(get_tic6x_dynamic_type): New.
(get_dynamic_type): Call it.
(get_machine_flags): Handle EF_C6000_REL.
(get_osabi_name): Handle machine-specific values only for relevant
machines. Handle C6X values.
(get_tic6x_segment_type): New.
(get_segment_type): Call it.
(get_tic6x_section_type_name): New.
(get_section_type_name): Call it.
(is_32bit_abs_reloc, is_16bit_abs_reloc, is_none_reloc): Handle
EM_TI_C6000.
gas:
* Makefile.am (TARGET_CPU_CFILES): Add config/tc-tic6x.c.
(TARGET_CPU_HFILES): Add config/tc-tic6x.h.
* Makefile.in: Regenerate.
* NEWS: Add news entry for TI C6X support.
* app.c (do_scrub_chars): Handle "||^" for TI C6X. Handle
TC_PREDICATE_START_CHAR and TC_PREDICATE_END_CHAR. Keep spaces in
operands if TC_KEEP_OPERAND_SPACES.
* configure.tgt (tic6x-*-*): New.
* config/tc-ia64.h (TC_PREDICATE_START_CHAR,
TC_PREDICATE_END_CHAR): Define.
* config/tc-tic6x.c, config/tc-tic6x.h: New.
* doc/Makefile.am (CPU_DOCS): Add c-tic6x.texi.
* doc/Makefile.in: Regenerate.
* doc/all.texi (TIC6X): Define.
* doc/as.texinfo: Add TI C6X documentation. Include c-tic6x.texi.
* doc/c-tic6x.texi: New.
gas/testsuite:
* gas/tic6x: New directory and testcases.
include:
* dis-asm.h (print_insn_tic6x): Declare.
include/elf:
* common.h (ELFOSABI_C6000_ELFABI, ELFOSABI_C6000_LINUX): Define.
* tic6x.h: New.
include/opcode:
* tic6x-control-registers.h, tic6x-insn-formats.h,
tic6x-opcode-table.h, tic6x.h: New.
ld:
* Makefile.am (ALL_EMULATIONS): Add eelf32_tic6x_be.o and
eelf32_tic6x_le.o.
(eelf32_tic6x_be.c, eelf32_tic6x_le.c): New.
* NEWS: Add news entry for TI C6X support.
* configure.tgt (tic6x-*-*): New.
* emulparams/elf32_tic6x_be.sh, emulparams/elf32_tic6x_le.sh: New.
ld/testsuite:
* ld-elf/flags1.d, ld-elf/merge.d: XFAIL for tic6x-*-*.
* ld-elf/sec-to-seg.exp: Set B_test_same_seg to 0 for tic6x-*-*.
* ld-tic6x: New directory and testcases.
opcodes:
* Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
* Makefile.in: Regenerate.
* configure.in (bfd_tic6x_arch): New.
* configure: Regenerate.
* disassemble.c (ARCH_tic6x): Define if ARCH_all.
(disassembler): Handle TI C6X.
* tic6x-dis.c: New.
2010-03-25 21:12:36 +00:00
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CFLDS3(FLD(s, 1, 1), FLD(x, 12, 1), FLD(src2, 18, 5)))
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FMT(s_mvk, 32, 0x28, 0x3c,
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CFLDS4(FLD(s, 1, 1), FLD(h, 6, 1), FLD(cst, 7, 16), FLD(dst, 23, 5)))
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FMT(s_field, 32, 0x8, 0x3c,
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CFLDS6(FLD(s, 1, 1), FLD(op, 6, 2), FLD(cstb, 8, 5), FLD(csta, 13, 5),
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FLD(src2, 18, 5), FLD(dst, 23, 5)))
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/* S-unit formats missing from Appendix F. */
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FMT(s_addk, 32, 0x50, 0x7c,
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CFLDS3(FLD(s, 1, 1), FLD(cst, 7, 16), FLD(dst, 23, 5)))
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FMT(s_addkpc, 32, 0x160, 0x1ffc,
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CFLDS4(FLD(s, 1, 1), FLD(src2, 13, 3), FLD(src1, 16, 7), FLD(dst, 23, 5)))
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FMT(s_b_irp, 32, 0x1800e0, 0x7feffc,
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CFLDS3(FLD(s, 1, 1), FLD(x, 12, 1), FLD(dst, 23, 5)))
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FMT(s_b_nrp, 32, 0x1c00e0, 0x7feffc,
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CFLDS3(FLD(s, 1, 1), FLD(x, 12, 1), FLD(dst, 23, 5)))
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FMT(s_bdec, 32, 0x1020, 0x1ffc,
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CFLDS3(FLD(s, 1, 1), FLD(src, 13, 10), FLD(dst, 23, 5)))
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FMT(s_bpos, 32, 0x20, 0x1ffc,
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CFLDS3(FLD(s, 1, 1), FLD(src, 13, 10), FLD(dst, 23, 5)))
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/* Appendix F 16-bit formats will go here. */
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/* Appendix G 16-bit formats will go here. */
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/* Appendix H 32-bit formats. */
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FMT(nfu_loop_buffer, 32, 0x00020000, 0x00021ffc,
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CFLDS4(FLD(s, 1, 1), FLD(op, 13, 4), FLD(csta, 18, 5), FLD(cstb, 23, 5)))
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/* Corrected relative to Appendix H. */
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FMT(nfu_nop_idle, 32, 0x00000000, 0xfffe1ffc,
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NFLDS2(FLD(s, 1, 1), FLD(op, 13, 4)))
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/* No-unit formats missing from Appendix H (given the NOP and IDLE
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correction). */
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FMT(nfu_dint, 32, 0x10004000, 0xfffffffc,
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NFLDS1(FLD(s, 1, 1)))
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FMT(nfu_rint, 32, 0x10006000, 0xfffffffc,
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NFLDS1(FLD(s, 1, 1)))
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FMT(nfu_swe, 32, 0x10000000, 0xfffffffc,
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NFLDS1(FLD(s, 1, 1)))
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FMT(nfu_swenr, 32, 0x10002000, 0xfffffffc,
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NFLDS1(FLD(s, 1, 1)))
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/* Although formally covered by the loop buffer format, the fields in
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that format are not useful for all such instructions and not all
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instructions can be predicated. */
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FMT(nfu_spkernel, 32, 0x00034000, 0xf03ffffc,
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NFLDS2(FLD(s, 1, 1), FLD(fstgfcyc, 22, 6)))
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FMT(nfu_spkernelr, 32, 0x00036000, 0xfffffffc,
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NFLDS1(FLD(s, 1, 1)))
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FMT(nfu_spmask, 32, 0x00020000, 0xfc021ffc,
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NFLDS3(FLD(s, 1, 1), FLD(op, 13, 4), FLD(mask, 18, 8)))
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/* Appendix H 16-bit formats will go here. */
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#undef FLD
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#undef CFLDS
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#undef CFLDS2
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#undef CFLDS3
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#undef CFLDS4
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#undef CFLDS5
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#undef CFLDS6
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#undef CFLDS7
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#undef CFLDS8
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#undef NFLDS
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#undef NFLDS1
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#undef NFLDS2
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#undef NFLDS3
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#undef NFLDS5
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#undef NFLDS6
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#undef NFLDS7
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