old-cross-binutils/ld/testsuite/ld-arm/armthumb-lib.d

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tmpdir/armthumb-lib.so: file format elf32-(little|big)arm
Fix tests when configured for arm-linux and arm-elf With this change all gas and most ld tests pass when configured for arm-linux. It doesn't look like these configurations have been tested in a long time but this attempts to stem the bit-rot slightly. gas/testsuite/ChangeLog: 2014-07-10 Will Newton <will.newton@linaro.org> * gas/arm/bl-local-2.d: Only enable the test on EABI and NaCl configurations. * gas/arm/bl-local-v4t.d: Likewise. * gas/arm/blx-local.d: Likewise. * gas/arm/branch-reloc.d: Likewise. ld/testsuite/ChangeLog: 2014-07-10 Will Newton <will.newton@linaro.org> * ld-arm/arm-elf.exp (armelftests_nonacl): Move Cortex-A8 fix tests, IFUNC tests and other EABI requiring tests to... (armeabitests_nonacl): ...here. * ld-arm/arm-app-abs32.d: Loosen regex for architecture type to allow test to pass on configurations without an attributes section. * ld-arm/arm-app.d: Likewise. * ld-arm/arm-lib-plt32.d: Likewise. * ld-arm/arm-lib.d: Likewise. * ld-arm/arm-static-app.d: Likewise. * ld-arm/armthumb-lib.d: Likewise. * ld-arm/cortex-a8-far.d: Likewise. * ld-arm/farcall-mixed-app.d: Likewise. * ld-arm/farcall-mixed-lib-v4t.d: Likewise. * ld-arm/farcall-mixed-lib.d: Likewise. * ld-arm/mixed-app-v5.d: Likewise. * ld-arm/mixed-app.d: Likewise. * ld-arm/mixed-lib.d: Likewise. * ld-arm/tls-app.d: Likewise. * ld-arm/tls-descrelax-be32.d: Likewise. * ld-arm/tls-descrelax.d: Likewise. * ld-arm/tls-descseq.d: Likewise. * ld-arm/tls-gdesc-got.d: Likewise. * ld-arm/tls-gdesc.d: Likewise. * ld-arm/tls-gdierelax.d: Likewise. * ld-arm/tls-gdierelax2.d: Likewise. * ld-arm/tls-gdlerelax.d: Likewise. * ld-arm/tls-lib-loc.d: Likewise. * ld-arm/tls-lib.d: Likewise. * ld-arm/tls-thumb1.d: Likewise.
2014-07-07 16:33:34 +00:00
architecture: arm.*, flags 0x00000150:
HAS_SYMS, DYNAMIC, D_PAGED
start address 0x.*
Disassembly of section .plt:
.* <app_func2@plt-0x14>:
.*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
.*: e59fe004 ldr lr, \[pc, #4\] ; .* <app_func2@plt-0x4>
.*: e08fe00e add lr, pc, lr
.*: e5bef008 ldr pc, \[lr, #8\]!
.*: .*
.* <app_func2@plt>:
.*: e28fc6.* add ip, pc, #.*
.*: e28cca.* add ip, ip, #.* ; 0x.*
.*: e5bcf.* ldr pc, \[ip, #.*\]!.*
Disassembly of section .text:
.* <lib_func1>:
.*: e1a0c00d mov ip, sp
.*: e92dd800 push {fp, ip, lr, pc}
.*: ebfffff. bl .* <app_func2@plt>
.*: e89d6800 ldm sp, {fp, sp, lr}
.*: e12fff1e bx lr
.*: e1a00000 nop ; \(mov r0, r0\)
.*: e1a00000 nop ; \(mov r0, r0\)
.*: e1a00000 nop ; \(mov r0, r0\)
.* <__real_lib_func2>:
.*: 4770 bx lr
.*: 46c0 nop ; \(mov r8, r8\)
.*: 46c0 nop ; \(mov r8, r8\)
.*: 46c0 nop ; \(mov r8, r8\)
.*: 46c0 nop ; \(mov r8, r8\)
.*: 46c0 nop ; \(mov r8, r8\)
.*: 46c0 nop ; \(mov r8, r8\)
.*: 46c0 nop ; \(mov r8, r8\)
.* <lib_func2>:
.*: e59fc004 ldr ip, \[pc, #4\] ; .* <lib_func2\+0xc>
.*: e08cc00f add ip, ip, pc
.*: e12fff1c bx ip
.*: ffffffe5 .*