255 lines
6.6 KiB
C
255 lines
6.6 KiB
C
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/* sim-ppc.h --- interface between PowerPC simulator and GDB.
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Copyright 2004 Free Software Foundation, Inc.
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Contributed by Red Hat.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
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02111-1307, USA. */
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#if !defined (SIM_PPC_H)
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#define SIM_PPC_H
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/* The register access functions, sim_fetch_register and
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sim_store_register, use the following numbering for PowerPC
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registers. */
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enum sim_ppc_regnum
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{
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/* General-purpose registers, r0 -- r31. */
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sim_ppc_r0_regnum,
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sim_ppc_r1_regnum,
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sim_ppc_r2_regnum,
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sim_ppc_r3_regnum,
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sim_ppc_r4_regnum,
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sim_ppc_r5_regnum,
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sim_ppc_r6_regnum,
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sim_ppc_r7_regnum,
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sim_ppc_r8_regnum,
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sim_ppc_r9_regnum,
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sim_ppc_r10_regnum,
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sim_ppc_r11_regnum,
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sim_ppc_r12_regnum,
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sim_ppc_r13_regnum,
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sim_ppc_r14_regnum,
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sim_ppc_r15_regnum,
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sim_ppc_r16_regnum,
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sim_ppc_r17_regnum,
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sim_ppc_r18_regnum,
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sim_ppc_r19_regnum,
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sim_ppc_r20_regnum,
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sim_ppc_r21_regnum,
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sim_ppc_r22_regnum,
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sim_ppc_r23_regnum,
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sim_ppc_r24_regnum,
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sim_ppc_r25_regnum,
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sim_ppc_r26_regnum,
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sim_ppc_r27_regnum,
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sim_ppc_r28_regnum,
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sim_ppc_r29_regnum,
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sim_ppc_r30_regnum,
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sim_ppc_r31_regnum,
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/* Floating-point registers, f0 -- f31. */
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sim_ppc_f0_regnum,
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sim_ppc_f1_regnum,
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sim_ppc_f2_regnum,
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sim_ppc_f3_regnum,
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sim_ppc_f4_regnum,
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sim_ppc_f5_regnum,
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sim_ppc_f6_regnum,
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sim_ppc_f7_regnum,
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sim_ppc_f8_regnum,
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sim_ppc_f9_regnum,
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sim_ppc_f10_regnum,
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sim_ppc_f11_regnum,
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sim_ppc_f12_regnum,
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sim_ppc_f13_regnum,
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sim_ppc_f14_regnum,
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sim_ppc_f15_regnum,
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sim_ppc_f16_regnum,
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sim_ppc_f17_regnum,
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sim_ppc_f18_regnum,
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sim_ppc_f19_regnum,
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sim_ppc_f20_regnum,
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sim_ppc_f21_regnum,
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sim_ppc_f22_regnum,
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sim_ppc_f23_regnum,
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sim_ppc_f24_regnum,
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sim_ppc_f25_regnum,
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sim_ppc_f26_regnum,
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sim_ppc_f27_regnum,
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sim_ppc_f28_regnum,
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sim_ppc_f29_regnum,
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sim_ppc_f30_regnum,
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sim_ppc_f31_regnum,
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/* Altivec vector registers, vr0 -- vr31. */
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sim_ppc_vr0_regnum,
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sim_ppc_vr1_regnum,
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sim_ppc_vr2_regnum,
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sim_ppc_vr3_regnum,
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sim_ppc_vr4_regnum,
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sim_ppc_vr5_regnum,
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sim_ppc_vr6_regnum,
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sim_ppc_vr7_regnum,
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sim_ppc_vr8_regnum,
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sim_ppc_vr9_regnum,
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sim_ppc_vr10_regnum,
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sim_ppc_vr11_regnum,
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sim_ppc_vr12_regnum,
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sim_ppc_vr13_regnum,
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sim_ppc_vr14_regnum,
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sim_ppc_vr15_regnum,
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sim_ppc_vr16_regnum,
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sim_ppc_vr17_regnum,
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sim_ppc_vr18_regnum,
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sim_ppc_vr19_regnum,
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sim_ppc_vr20_regnum,
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sim_ppc_vr21_regnum,
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sim_ppc_vr22_regnum,
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sim_ppc_vr23_regnum,
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sim_ppc_vr24_regnum,
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sim_ppc_vr25_regnum,
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sim_ppc_vr26_regnum,
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sim_ppc_vr27_regnum,
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sim_ppc_vr28_regnum,
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sim_ppc_vr29_regnum,
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sim_ppc_vr30_regnum,
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sim_ppc_vr31_regnum,
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/* SPE APU GPR upper halves. These are the upper 32 bits of the
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gprs; there is one upper-half register for each gpr, so it is
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appropriate to use sim_ppc_num_gprs for iterating through
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these. */
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sim_ppc_rh0_regnum,
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sim_ppc_rh1_regnum,
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sim_ppc_rh2_regnum,
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sim_ppc_rh3_regnum,
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sim_ppc_rh4_regnum,
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sim_ppc_rh5_regnum,
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sim_ppc_rh6_regnum,
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sim_ppc_rh7_regnum,
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sim_ppc_rh8_regnum,
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sim_ppc_rh9_regnum,
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sim_ppc_rh10_regnum,
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sim_ppc_rh11_regnum,
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sim_ppc_rh12_regnum,
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sim_ppc_rh13_regnum,
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sim_ppc_rh14_regnum,
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sim_ppc_rh15_regnum,
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sim_ppc_rh16_regnum,
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sim_ppc_rh17_regnum,
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sim_ppc_rh18_regnum,
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sim_ppc_rh19_regnum,
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sim_ppc_rh20_regnum,
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sim_ppc_rh21_regnum,
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sim_ppc_rh22_regnum,
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sim_ppc_rh23_regnum,
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sim_ppc_rh24_regnum,
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sim_ppc_rh25_regnum,
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sim_ppc_rh26_regnum,
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sim_ppc_rh27_regnum,
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sim_ppc_rh28_regnum,
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sim_ppc_rh29_regnum,
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sim_ppc_rh30_regnum,
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sim_ppc_rh31_regnum,
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/* SPE APU GPR full registers. Each of these registers is the
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64-bit concatenation of a 32-bit GPR (providing the lower bits)
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and a 32-bit upper-half register (providing the higher bits).
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As for the upper-half registers, it is appropriate to use
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sim_ppc_num_gprs with these. */
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sim_ppc_ev0_regnum,
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sim_ppc_ev1_regnum,
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sim_ppc_ev2_regnum,
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sim_ppc_ev3_regnum,
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sim_ppc_ev4_regnum,
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sim_ppc_ev5_regnum,
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sim_ppc_ev6_regnum,
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sim_ppc_ev7_regnum,
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sim_ppc_ev8_regnum,
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sim_ppc_ev9_regnum,
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sim_ppc_ev10_regnum,
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sim_ppc_ev11_regnum,
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sim_ppc_ev12_regnum,
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sim_ppc_ev13_regnum,
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sim_ppc_ev14_regnum,
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sim_ppc_ev15_regnum,
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sim_ppc_ev16_regnum,
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sim_ppc_ev17_regnum,
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sim_ppc_ev18_regnum,
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sim_ppc_ev19_regnum,
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sim_ppc_ev20_regnum,
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sim_ppc_ev21_regnum,
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sim_ppc_ev22_regnum,
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sim_ppc_ev23_regnum,
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sim_ppc_ev24_regnum,
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sim_ppc_ev25_regnum,
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sim_ppc_ev26_regnum,
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sim_ppc_ev27_regnum,
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sim_ppc_ev28_regnum,
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sim_ppc_ev29_regnum,
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sim_ppc_ev30_regnum,
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sim_ppc_ev31_regnum,
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/* Segment registers, sr0 -- sr15. */
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sim_ppc_sr0_regnum,
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sim_ppc_sr1_regnum,
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sim_ppc_sr2_regnum,
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sim_ppc_sr3_regnum,
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sim_ppc_sr4_regnum,
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sim_ppc_sr5_regnum,
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sim_ppc_sr6_regnum,
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sim_ppc_sr7_regnum,
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sim_ppc_sr8_regnum,
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sim_ppc_sr9_regnum,
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sim_ppc_sr10_regnum,
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sim_ppc_sr11_regnum,
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sim_ppc_sr12_regnum,
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sim_ppc_sr13_regnum,
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sim_ppc_sr14_regnum,
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sim_ppc_sr15_regnum,
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/* Miscellaneous --- but non-SPR --- registers. */
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sim_ppc_pc_regnum,
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sim_ppc_ps_regnum,
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sim_ppc_cr_regnum,
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sim_ppc_fpscr_regnum,
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sim_ppc_acc_regnum,
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sim_ppc_vscr_regnum,
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/* Special-purpose registers. Each SPR is given a number equal to
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its number in the ISA --- the number that appears in the mtspr
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/ mfspr instructions --- plus this constant. */
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sim_ppc_spr0_regnum
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};
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/* Sizes of various register sets. */
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enum
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{
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sim_ppc_num_gprs = 32,
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sim_ppc_num_fprs = 32,
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sim_ppc_num_vrs = 32,
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sim_ppc_num_srs = 16,
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sim_ppc_num_sprs = 1024,
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};
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#endif /* SIM_PPC_H */
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