1998-02-06 02:29:22 +00:00
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/* Copyright (C) 1998, Cygnus Solutions */
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1998-02-18 21:26:38 +00:00
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1998-02-11 19:42:15 +00:00
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/* Debugguing PKE? */
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#define PKE_DEBUG
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1998-02-18 21:26:38 +00:00
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1998-02-06 02:29:22 +00:00
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#include <stdlib.h>
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1998-02-07 00:12:14 +00:00
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#include "sky-pke.h"
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#include "sky-dma.h"
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1998-02-13 23:29:38 +00:00
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#include "sim-bits.h"
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1998-02-07 00:12:14 +00:00
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#include "sim-assert.h"
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#include "sky-vu0.h"
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#include "sky-vu1.h"
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#include "sky-gpuif.h"
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1998-02-06 02:29:22 +00:00
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1998-02-11 19:42:15 +00:00
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1998-02-06 02:29:22 +00:00
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/* Imported functions */
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void device_error (device *me, char* message); /* device.c */
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/* Internal function declarations */
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static int pke_io_read_buffer(device*, void*, int, address_word,
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unsigned, sim_cpu*, sim_cia);
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static int pke_io_write_buffer(device*, const void*, int, address_word,
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unsigned, sim_cpu*, sim_cia);
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1998-02-18 21:26:38 +00:00
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static void pke_issue(SIM_DESC, struct pke_device*);
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1998-02-07 00:12:14 +00:00
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static void pke_pc_advance(struct pke_device*, int num_words);
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1998-02-11 19:42:15 +00:00
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static unsigned_4* pke_pc_operand(struct pke_device*, int operand_num);
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1998-02-13 23:29:38 +00:00
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static unsigned_4 pke_pc_operand_bits(struct pke_device*, int bit_offset,
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int bit_width, unsigned_4* sourceaddr);
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1998-02-11 19:42:15 +00:00
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static struct fifo_quadword* pke_pc_fifo(struct pke_device*, int operand_num,
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unsigned_4** operand);
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1998-02-07 00:12:14 +00:00
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static int pke_track_write(struct pke_device*, const void* src, int len,
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address_word dest, unsigned_4 sourceaddr);
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static void pke_attach(SIM_DESC sd, struct pke_device* me);
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1998-02-11 19:42:15 +00:00
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enum pke_check_target { chk_vu, chk_path1, chk_path2, chk_path3 };
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static int pke_check_stall(struct pke_device* me, enum pke_check_target what);
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static void pke_flip_dbf(struct pke_device* me);
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/* PKEcode handlers */
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static void pke_code_nop(struct pke_device* me, unsigned_4 pkecode);
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static void pke_code_stcycl(struct pke_device* me, unsigned_4 pkecode);
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static void pke_code_offset(struct pke_device* me, unsigned_4 pkecode);
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static void pke_code_base(struct pke_device* me, unsigned_4 pkecode);
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static void pke_code_itop(struct pke_device* me, unsigned_4 pkecode);
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static void pke_code_stmod(struct pke_device* me, unsigned_4 pkecode);
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static void pke_code_mskpath3(struct pke_device* me, unsigned_4 pkecode);
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static void pke_code_pkemark(struct pke_device* me, unsigned_4 pkecode);
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static void pke_code_flushe(struct pke_device* me, unsigned_4 pkecode);
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static void pke_code_flush(struct pke_device* me, unsigned_4 pkecode);
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static void pke_code_flusha(struct pke_device* me, unsigned_4 pkecode);
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static void pke_code_pkemscal(struct pke_device* me, unsigned_4 pkecode);
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static void pke_code_pkemscnt(struct pke_device* me, unsigned_4 pkecode);
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static void pke_code_pkemscalf(struct pke_device* me, unsigned_4 pkecode);
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static void pke_code_stmask(struct pke_device* me, unsigned_4 pkecode);
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static void pke_code_strow(struct pke_device* me, unsigned_4 pkecode);
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static void pke_code_stcol(struct pke_device* me, unsigned_4 pkecode);
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static void pke_code_mpg(struct pke_device* me, unsigned_4 pkecode);
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static void pke_code_direct(struct pke_device* me, unsigned_4 pkecode);
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static void pke_code_directhl(struct pke_device* me, unsigned_4 pkecode);
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static void pke_code_unpack(struct pke_device* me, unsigned_4 pkecode);
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static void pke_code_error(struct pke_device* me, unsigned_4 pkecode);
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1998-02-07 00:12:14 +00:00
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1998-02-06 02:29:22 +00:00
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/* Static data */
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struct pke_device pke0_device =
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{
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{ "pke0", &pke_io_read_buffer, &pke_io_write_buffer }, /* device */
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0, 0, /* ID, flags */
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{}, /* regs */
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1998-02-13 23:29:38 +00:00
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{}, 0, /* FIFO write buffer */
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1998-02-06 02:29:22 +00:00
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NULL, 0, 0, NULL, /* FIFO */
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1998-02-07 00:12:14 +00:00
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0, 0 /* pc */
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1998-02-06 02:29:22 +00:00
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};
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struct pke_device pke1_device =
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{
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{ "pke1", &pke_io_read_buffer, &pke_io_write_buffer }, /* device */
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1, 0, /* ID, flags */
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{}, /* regs */
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1998-02-13 23:29:38 +00:00
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{}, 0, /* FIFO write buffer */
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1998-02-06 02:29:22 +00:00
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NULL, 0, 0, NULL, /* FIFO */
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1998-02-07 00:12:14 +00:00
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0, 0 /* pc */
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1998-02-06 02:29:22 +00:00
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};
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/* External functions */
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1998-02-07 00:12:14 +00:00
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/* Attach PKE addresses to main memory */
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1998-02-06 02:29:22 +00:00
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void
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pke0_attach(SIM_DESC sd)
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{
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1998-02-07 00:12:14 +00:00
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pke_attach(sd, & pke0_device);
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}
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1998-02-06 02:29:22 +00:00
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1998-02-07 00:12:14 +00:00
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void
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pke1_attach(SIM_DESC sd)
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{
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pke_attach(sd, & pke1_device);
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1998-02-06 02:29:22 +00:00
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}
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1998-02-07 00:12:14 +00:00
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/* Issue a PKE instruction if possible */
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1998-02-06 02:29:22 +00:00
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void
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1998-02-18 21:26:38 +00:00
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pke0_issue(SIM_DESC sd)
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1998-02-06 02:29:22 +00:00
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{
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1998-02-18 21:26:38 +00:00
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pke_issue(sd, & pke0_device);
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1998-02-07 00:12:14 +00:00
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}
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void
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1998-02-18 21:26:38 +00:00
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pke1_issue(SIM_DESC sd)
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1998-02-07 00:12:14 +00:00
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{
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1998-02-18 21:26:38 +00:00
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pke_issue(sd, & pke0_device);
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1998-02-07 00:12:14 +00:00
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}
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/* Internal functions */
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/* Attach PKE memory regions to simulator */
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void
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pke_attach(SIM_DESC sd, struct pke_device* me)
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{
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/* register file */
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1998-02-18 21:26:38 +00:00
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sim_core_attach (sd, NULL, 0, access_read_write, 0,
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1998-02-07 00:12:14 +00:00
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(me->pke_number == 0) ? PKE0_REGISTER_WINDOW_START : PKE1_REGISTER_WINDOW_START,
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1998-02-06 02:29:22 +00:00
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PKE_REGISTER_WINDOW_SIZE /*nr_bytes*/,
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0 /*modulo*/,
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1998-02-18 21:26:38 +00:00
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(device*) me,
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1998-02-06 02:29:22 +00:00
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NULL /*buffer*/);
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1998-02-07 00:12:14 +00:00
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/* FIFO port */
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1998-02-18 21:26:38 +00:00
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sim_core_attach (sd, NULL, 0, access_read_write, 0,
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1998-02-07 00:12:14 +00:00
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(me->pke_number == 0) ? PKE0_FIFO_ADDR : PKE1_FIFO_ADDR,
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1998-02-06 02:29:22 +00:00
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sizeof(quadword) /*nr_bytes*/,
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0 /*modulo*/,
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1998-02-18 21:26:38 +00:00
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(device*) me,
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1998-02-06 02:29:22 +00:00
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NULL /*buffer*/);
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1998-02-07 00:12:14 +00:00
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/* source-addr tracking word */
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1998-02-18 21:26:38 +00:00
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sim_core_attach (sd, NULL, 0, access_read_write, 0,
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1998-02-07 00:12:14 +00:00
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(me->pke_number == 0) ? PKE0_SRCADDR : PKE1_SRCADDR,
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sizeof(unsigned_4) /*nr_bytes*/,
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0 /*modulo*/,
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NULL,
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zalloc(sizeof(unsigned_4)) /*buffer*/);
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1998-02-18 21:26:38 +00:00
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/* attach to trace file if appropriate */
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{
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char trace_envvar[80];
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char* trace_filename = NULL;
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sprintf(trace_envvar, "VIF%d_TRACE_FILE", me->pke_number);
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trace_filename = getenv(trace_envvar);
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if(trace_filename != NULL)
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{
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me->fifo_trace_file = fopen(trace_filename, "w");
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if(me->fifo_trace_file == NULL)
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{
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perror("VIF FIFO trace error on fopen");
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}
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}
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}
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1998-02-06 02:29:22 +00:00
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}
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/* Handle a PKE read; return no. of bytes read */
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int
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pke_io_read_buffer(device *me_,
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void *dest,
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int space,
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address_word addr,
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unsigned nr_bytes,
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1998-02-07 00:12:14 +00:00
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sim_cpu *cpu,
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1998-02-06 02:29:22 +00:00
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sim_cia cia)
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{
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/* downcast to gather embedding pke_device struct */
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struct pke_device* me = (struct pke_device*) me_;
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1998-02-07 00:12:14 +00:00
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/* find my address ranges */
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address_word my_reg_start =
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(me->pke_number == 0) ? PKE0_REGISTER_WINDOW_START : PKE1_REGISTER_WINDOW_START;
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address_word my_fifo_addr =
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(me->pke_number == 0) ? PKE0_FIFO_ADDR : PKE1_FIFO_ADDR;
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1998-02-06 02:29:22 +00:00
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/* enforce that an access does not span more than one quadword */
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address_word low = ADDR_TRUNC_QW(addr);
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address_word high = ADDR_TRUNC_QW(addr + nr_bytes - 1);
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if(low != high)
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return 0;
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/* classify address & handle */
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1998-02-07 00:12:14 +00:00
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if((addr >= my_reg_start) && (addr < my_reg_start + PKE_REGISTER_WINDOW_SIZE))
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1998-02-06 02:29:22 +00:00
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{
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/* register bank */
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1998-02-07 00:12:14 +00:00
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int reg_num = ADDR_TRUNC_QW(addr - my_reg_start) >> 4;
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int reg_byte = ADDR_OFFSET_QW(addr); /* find byte-offset inside register bank */
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1998-02-06 02:29:22 +00:00
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int readable = 1;
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1998-02-07 00:12:14 +00:00
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quadword result;
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/* clear result */
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result[0] = result[1] = result[2] = result[3] = 0;
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1998-02-06 02:29:22 +00:00
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1998-02-07 00:12:14 +00:00
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/* handle reads to individual registers; clear `readable' on error */
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1998-02-06 02:29:22 +00:00
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switch(reg_num)
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{
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1998-02-07 00:12:14 +00:00
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/* handle common case of register reading, side-effect free */
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/* PKE1-only registers*/
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1998-02-06 02:29:22 +00:00
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case PKE_REG_BASE:
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case PKE_REG_OFST:
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case PKE_REG_TOPS:
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case PKE_REG_TOP:
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case PKE_REG_DBF:
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1998-02-07 00:12:14 +00:00
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if(me->pke_number == 0)
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1998-02-06 02:29:22 +00:00
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readable = 0;
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1998-02-07 00:12:14 +00:00
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/* fall through */
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/* PKE0 & PKE1 common registers*/
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case PKE_REG_STAT:
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case PKE_REG_ERR:
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case PKE_REG_MARK:
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case PKE_REG_CYCLE:
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case PKE_REG_MODE:
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case PKE_REG_NUM:
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case PKE_REG_MASK:
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case PKE_REG_CODE:
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case PKE_REG_ITOPS:
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case PKE_REG_ITOP:
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case PKE_REG_R0:
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case PKE_REG_R1:
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case PKE_REG_R2:
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case PKE_REG_R3:
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case PKE_REG_C0:
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case PKE_REG_C1:
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case PKE_REG_C2:
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case PKE_REG_C3:
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result[0] = me->regs[reg_num][0];
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break;
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/* handle common case of write-only registers */
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case PKE_REG_FBRST:
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readable = 0;
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break;
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default:
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ASSERT(0); /* test above should prevent this possibility */
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1998-02-06 02:29:22 +00:00
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}
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1998-02-07 00:12:14 +00:00
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/* perform transfer & return */
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1998-02-06 02:29:22 +00:00
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if(readable)
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{
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/* copy the bits */
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1998-02-07 00:12:14 +00:00
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memcpy(dest, ((unsigned_1*) &result) + reg_byte, nr_bytes);
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1998-02-06 02:29:22 +00:00
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/* okay */
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return nr_bytes;
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}
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else
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{
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/* error */
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return 0;
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}
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/* NOTREACHED */
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}
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1998-02-07 00:12:14 +00:00
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else if(addr >= my_fifo_addr &&
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addr < my_fifo_addr + sizeof(quadword))
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1998-02-06 02:29:22 +00:00
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{
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/* FIFO */
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1998-02-07 00:12:14 +00:00
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/* FIFO is not readable: return a word of zeroes */
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memset(dest, 0, nr_bytes);
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return nr_bytes;
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1998-02-06 02:29:22 +00:00
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}
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/* NOTREACHED */
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1998-02-07 00:12:14 +00:00
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return 0;
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1998-02-06 02:29:22 +00:00
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}
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/* Handle a PKE read; return no. of bytes written */
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int
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pke_io_write_buffer(device *me_,
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const void *src,
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int space,
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address_word addr,
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unsigned nr_bytes,
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1998-02-07 00:12:14 +00:00
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sim_cpu *cpu,
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1998-02-06 02:29:22 +00:00
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sim_cia cia)
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{
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|
|
/* downcast to gather embedding pke_device struct */
|
|
|
|
struct pke_device* me = (struct pke_device*) me_;
|
|
|
|
|
1998-02-07 00:12:14 +00:00
|
|
|
/* find my address ranges */
|
|
|
|
address_word my_reg_start =
|
|
|
|
(me->pke_number == 0) ? PKE0_REGISTER_WINDOW_START : PKE1_REGISTER_WINDOW_START;
|
|
|
|
address_word my_fifo_addr =
|
|
|
|
(me->pke_number == 0) ? PKE0_FIFO_ADDR : PKE1_FIFO_ADDR;
|
|
|
|
|
1998-02-06 02:29:22 +00:00
|
|
|
/* enforce that an access does not span more than one quadword */
|
|
|
|
address_word low = ADDR_TRUNC_QW(addr);
|
|
|
|
address_word high = ADDR_TRUNC_QW(addr + nr_bytes - 1);
|
|
|
|
if(low != high)
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
/* classify address & handle */
|
1998-02-07 00:12:14 +00:00
|
|
|
if((addr >= my_reg_start) && (addr < my_reg_start + PKE_REGISTER_WINDOW_SIZE))
|
1998-02-06 02:29:22 +00:00
|
|
|
{
|
|
|
|
/* register bank */
|
1998-02-07 00:12:14 +00:00
|
|
|
int reg_num = ADDR_TRUNC_QW(addr - my_reg_start) >> 4;
|
|
|
|
int reg_byte = ADDR_OFFSET_QW(addr); /* find byte-offset inside register bank */
|
1998-02-06 02:29:22 +00:00
|
|
|
int writeable = 1;
|
1998-02-07 00:12:14 +00:00
|
|
|
quadword input;
|
|
|
|
|
|
|
|
/* clear input */
|
|
|
|
input[0] = input[1] = input[2] = input[3] = 0;
|
1998-02-06 02:29:22 +00:00
|
|
|
|
1998-02-07 00:12:14 +00:00
|
|
|
/* write user-given bytes into input */
|
|
|
|
memcpy(((unsigned_1*) &input) + reg_byte, src, nr_bytes);
|
|
|
|
|
|
|
|
/* handle writes to individual registers; clear `writeable' on error */
|
1998-02-06 02:29:22 +00:00
|
|
|
switch(reg_num)
|
|
|
|
{
|
1998-02-07 00:12:14 +00:00
|
|
|
case PKE_REG_FBRST:
|
1998-02-11 19:42:15 +00:00
|
|
|
/* Order these tests from least to most overriding, in case
|
|
|
|
multiple bits are set. */
|
1998-02-07 00:12:14 +00:00
|
|
|
if(BIT_MASK_GET(input[0], 2, 2)) /* STC bit */
|
|
|
|
{
|
|
|
|
/* clear a bunch of status bits */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PSS, 0);
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PFS, 0);
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PIS, 0);
|
|
|
|
PKE_REG_MASK_SET(me, STAT, INT, 0);
|
|
|
|
PKE_REG_MASK_SET(me, STAT, ER0, 0);
|
|
|
|
PKE_REG_MASK_SET(me, STAT, ER1, 0);
|
1998-02-13 23:29:38 +00:00
|
|
|
me->flags &= ~PKE_FLAG_PENDING_PSS;
|
1998-02-07 00:12:14 +00:00
|
|
|
/* will allow resumption of possible stalled instruction */
|
|
|
|
}
|
1998-02-11 19:42:15 +00:00
|
|
|
if(BIT_MASK_GET(input[0], 2, 2)) /* STP bit */
|
|
|
|
{
|
1998-02-13 23:29:38 +00:00
|
|
|
me->flags |= PKE_FLAG_PENDING_PSS;
|
1998-02-11 19:42:15 +00:00
|
|
|
}
|
|
|
|
if(BIT_MASK_GET(input[0], 1, 1)) /* FBK bit */
|
|
|
|
{
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PFS, 1);
|
|
|
|
}
|
|
|
|
if(BIT_MASK_GET(input[0], 0, 0)) /* RST bit */
|
|
|
|
{
|
|
|
|
/* clear FIFO by skipping to word after PC: also
|
|
|
|
prevents re-execution attempt of possible stalled
|
|
|
|
instruction */
|
|
|
|
me->fifo_num_elements = me->fifo_pc;
|
1998-02-13 23:29:38 +00:00
|
|
|
/* clear registers, flag, other state */
|
1998-02-11 19:42:15 +00:00
|
|
|
memset(me->regs, 0, sizeof(me->regs));
|
1998-02-13 23:29:38 +00:00
|
|
|
me->fifo_qw_done = 0;
|
1998-02-11 19:42:15 +00:00
|
|
|
me->flags = 0;
|
|
|
|
me->qw_pc = 0;
|
|
|
|
}
|
1998-02-07 00:12:14 +00:00
|
|
|
break;
|
|
|
|
|
|
|
|
case PKE_REG_ERR:
|
|
|
|
/* copy bottom three bits */
|
|
|
|
BIT_MASK_SET(me->regs[PKE_REG_ERR][0], 0, 2, BIT_MASK_GET(input[0], 0, 2));
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PKE_REG_MARK:
|
|
|
|
/* copy bottom sixteen bits */
|
|
|
|
PKE_REG_MASK_SET(me, MARK, MARK, BIT_MASK_GET(input[0], 0, 15));
|
|
|
|
/* reset MRK bit in STAT */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, MRK, 0);
|
|
|
|
break;
|
|
|
|
|
|
|
|
/* handle common case of read-only registers */
|
|
|
|
/* PKE1-only registers - not really necessary to handle separately */
|
1998-02-06 02:29:22 +00:00
|
|
|
case PKE_REG_BASE:
|
|
|
|
case PKE_REG_OFST:
|
|
|
|
case PKE_REG_TOPS:
|
|
|
|
case PKE_REG_TOP:
|
|
|
|
case PKE_REG_DBF:
|
1998-02-07 00:12:14 +00:00
|
|
|
if(me->pke_number == 0)
|
1998-02-06 02:29:22 +00:00
|
|
|
writeable = 0;
|
1998-02-07 00:12:14 +00:00
|
|
|
/* fall through */
|
|
|
|
/* PKE0 & PKE1 common registers*/
|
|
|
|
case PKE_REG_STAT:
|
|
|
|
/* ignore FDR bit for PKE1_STAT -- simulator does not implement PKE->RAM transfers */
|
|
|
|
case PKE_REG_CYCLE:
|
|
|
|
case PKE_REG_MODE:
|
|
|
|
case PKE_REG_NUM:
|
|
|
|
case PKE_REG_MASK:
|
|
|
|
case PKE_REG_CODE:
|
|
|
|
case PKE_REG_ITOPS:
|
|
|
|
case PKE_REG_ITOP:
|
|
|
|
case PKE_REG_R0:
|
|
|
|
case PKE_REG_R1:
|
|
|
|
case PKE_REG_R2:
|
|
|
|
case PKE_REG_R3:
|
|
|
|
case PKE_REG_C0:
|
|
|
|
case PKE_REG_C1:
|
|
|
|
case PKE_REG_C2:
|
|
|
|
case PKE_REG_C3:
|
|
|
|
writeable = 0;
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
ASSERT(0); /* test above should prevent this possibility */
|
1998-02-06 02:29:22 +00:00
|
|
|
}
|
|
|
|
|
1998-02-07 00:12:14 +00:00
|
|
|
/* perform return */
|
|
|
|
if(writeable)
|
1998-02-06 02:29:22 +00:00
|
|
|
{
|
1998-02-07 00:12:14 +00:00
|
|
|
/* okay */
|
1998-02-06 02:29:22 +00:00
|
|
|
return nr_bytes;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* error */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* NOTREACHED */
|
|
|
|
}
|
1998-02-07 00:12:14 +00:00
|
|
|
else if(addr >= my_fifo_addr &&
|
|
|
|
addr < my_fifo_addr + sizeof(quadword))
|
1998-02-06 02:29:22 +00:00
|
|
|
{
|
|
|
|
/* FIFO */
|
1998-02-07 00:12:14 +00:00
|
|
|
struct fifo_quadword* fqw;
|
1998-02-13 23:29:38 +00:00
|
|
|
int fifo_byte = ADDR_OFFSET_QW(addr); /* find byte-offset inside fifo quadword */
|
1998-02-18 21:26:38 +00:00
|
|
|
unsigned_4 dma_tag_present = 0;
|
1998-02-13 23:29:38 +00:00
|
|
|
int i;
|
|
|
|
|
|
|
|
/* collect potentially-partial quadword in write buffer */
|
|
|
|
memcpy(((unsigned_1*)& me->fifo_qw_in_progress) + fifo_byte, src, nr_bytes);
|
|
|
|
/* mark bytes written */
|
|
|
|
for(i = fifo_byte; i < fifo_byte + nr_bytes; i++)
|
|
|
|
BIT_MASK_SET(me->fifo_qw_done, i, i, 1);
|
|
|
|
|
|
|
|
/* return if quadword not quite written yet */
|
|
|
|
if(BIT_MASK_GET(me->fifo_qw_done, 0, sizeof(quadword)-1) !=
|
1998-02-18 21:26:38 +00:00
|
|
|
BIT_MASK_BTW(0, sizeof(quadword)-1))
|
1998-02-13 23:29:38 +00:00
|
|
|
return nr_bytes;
|
1998-02-06 02:29:22 +00:00
|
|
|
|
1998-02-13 23:29:38 +00:00
|
|
|
/* all done - process quadword after clearing flag */
|
|
|
|
BIT_MASK_SET(me->fifo_qw_done, 0, sizeof(quadword)-1, 0);
|
1998-02-06 02:29:22 +00:00
|
|
|
|
|
|
|
/* ensure FIFO has enough elements */
|
|
|
|
if(me->fifo_num_elements == me->fifo_buffer_size)
|
|
|
|
{
|
|
|
|
/* time to grow */
|
|
|
|
int new_fifo_buffer_size = me->fifo_buffer_size + 20;
|
|
|
|
void* ptr = realloc((void*) me->fifo, new_fifo_buffer_size*sizeof(quadword));
|
1998-02-18 21:26:38 +00:00
|
|
|
|
1998-02-06 02:29:22 +00:00
|
|
|
if(ptr == NULL)
|
|
|
|
{
|
|
|
|
/* oops, cannot enlarge FIFO any more */
|
|
|
|
device_error(me_, "Cannot enlarge FIFO buffer\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
1998-02-18 21:26:38 +00:00
|
|
|
me->fifo = ptr;
|
1998-02-06 02:29:22 +00:00
|
|
|
me->fifo_buffer_size = new_fifo_buffer_size;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* add new quadword at end of FIFO */
|
1998-02-07 00:12:14 +00:00
|
|
|
fqw = & me->fifo[me->fifo_num_elements];
|
1998-02-18 21:26:38 +00:00
|
|
|
fqw->word_class[0] = fqw->word_class[1] =
|
|
|
|
fqw->word_class[2] = fqw->word_class[3] = wc_unknown;
|
1998-02-13 23:29:38 +00:00
|
|
|
memcpy((void*) fqw->data, me->fifo_qw_in_progress, sizeof(quadword));
|
1998-02-18 21:26:38 +00:00
|
|
|
ASSERT(sizeof(unsigned_4) == 4);
|
|
|
|
PKE_MEM_READ((SIM_ADDR) (me->pke_number == 0 ? DMA_D0_MADR : DMA_D1_MADR),
|
|
|
|
& fqw->source_address,
|
|
|
|
4);
|
|
|
|
PKE_MEM_READ((SIM_ADDR) (me->pke_number == 0 ? DMA_D0_PKTFLAG : DMA_D1_PKTFLAG),
|
|
|
|
& dma_tag_present,
|
|
|
|
4);
|
|
|
|
|
|
|
|
if(dma_tag_present)
|
|
|
|
{
|
|
|
|
/* lower two words are DMA tags */
|
|
|
|
fqw->word_class[0] = fqw->word_class[1] = wc_dma;
|
|
|
|
}
|
|
|
|
|
1998-02-07 00:12:14 +00:00
|
|
|
|
|
|
|
me->fifo_num_elements++;
|
|
|
|
|
|
|
|
/* set FQC to "1" as FIFO is now not empty */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, FQC, 1);
|
1998-02-06 02:29:22 +00:00
|
|
|
|
|
|
|
/* okay */
|
|
|
|
return nr_bytes;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* NOTREACHED */
|
1998-02-07 00:12:14 +00:00
|
|
|
return 0;
|
1998-02-06 02:29:22 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
1998-02-07 00:12:14 +00:00
|
|
|
/* Issue & swallow next PKE opcode if possible/available */
|
1998-02-06 02:29:22 +00:00
|
|
|
|
|
|
|
void
|
1998-02-18 21:26:38 +00:00
|
|
|
pke_issue(SIM_DESC sd, struct pke_device* me)
|
1998-02-06 02:29:22 +00:00
|
|
|
{
|
1998-02-07 00:12:14 +00:00
|
|
|
struct fifo_quadword* fqw;
|
|
|
|
unsigned_4 fw;
|
|
|
|
unsigned_4 cmd, intr, num;
|
|
|
|
unsigned_4 imm;
|
|
|
|
|
|
|
|
/* 1 -- test go / no-go for PKE execution */
|
|
|
|
|
1998-02-13 23:29:38 +00:00
|
|
|
/* switch on STAT:PSS if PSS-pending and in idle state */
|
|
|
|
if((PKE_REG_MASK_GET(me, STAT, PPS) == PKE_REG_STAT_PPS_IDLE) &&
|
|
|
|
(me->flags & PKE_FLAG_PENDING_PSS) != 0)
|
|
|
|
{
|
|
|
|
me->flags &= ~PKE_FLAG_PENDING_PSS;
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PSS, 1);
|
|
|
|
}
|
|
|
|
|
1998-02-07 00:12:14 +00:00
|
|
|
/* check for stall/halt control bits */
|
1998-02-13 23:29:38 +00:00
|
|
|
if(PKE_REG_MASK_GET(me, STAT, PFS) ||
|
|
|
|
PKE_REG_MASK_GET(me, STAT, PSS) || /* note special treatment below */
|
1998-02-11 19:42:15 +00:00
|
|
|
/* PEW bit not a reason to keep stalling - it's re-checked below */
|
|
|
|
/* PGW bit not a reason to keep stalling - it's re-checked below */
|
1998-02-07 00:12:14 +00:00
|
|
|
/* maskable stall controls: ER0, ER1, PIS */
|
|
|
|
(PKE_REG_MASK_GET(me, STAT, ER0) && !PKE_REG_MASK_GET(me, ERR, ME0)) ||
|
|
|
|
(PKE_REG_MASK_GET(me, STAT, ER1) && !PKE_REG_MASK_GET(me, ERR, ME1)) ||
|
|
|
|
(PKE_REG_MASK_GET(me, STAT, PIS) && !PKE_REG_MASK_GET(me, ERR, MII)))
|
|
|
|
{
|
1998-02-11 19:42:15 +00:00
|
|
|
/* try again next cycle; no state change */
|
|
|
|
return;
|
1998-02-07 00:12:14 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* confirm availability of new quadword of PKE instructions */
|
|
|
|
if(me->fifo_num_elements <= me->fifo_pc)
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
|
|
/* 2 -- fetch PKE instruction */
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* skip over DMA tag, if present */
|
|
|
|
pke_pc_advance(me, 0);
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* "fetch" instruction quadword and word */
|
|
|
|
fqw = & me->fifo[me->fifo_pc];
|
1998-02-07 00:12:14 +00:00
|
|
|
fw = fqw->data[me->qw_pc];
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* store word in PKECODE register */
|
1998-02-07 00:12:14 +00:00
|
|
|
me->regs[PKE_REG_CODE][0] = fw;
|
|
|
|
|
|
|
|
|
|
|
|
/* 3 -- decode PKE instruction */
|
|
|
|
|
|
|
|
/* PKE instruction format: [intr 0:0][pke-command 6:0][num 7:0][immediate 15:0],
|
|
|
|
so op-code is in top byte. */
|
|
|
|
intr = BIT_MASK_GET(fw, PKE_OPCODE_I_B, PKE_OPCODE_I_E);
|
|
|
|
cmd = BIT_MASK_GET(fw, PKE_OPCODE_CMD_B, PKE_OPCODE_CMD_E);
|
|
|
|
num = BIT_MASK_GET(fw, PKE_OPCODE_NUM_B, PKE_OPCODE_NUM_E);
|
|
|
|
imm = BIT_MASK_GET(fw, PKE_OPCODE_IMM_B, PKE_OPCODE_IMM_E);
|
|
|
|
|
|
|
|
if(intr)
|
|
|
|
{
|
|
|
|
/* set INT flag in STAT register */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, INT, 1);
|
1998-02-18 21:26:38 +00:00
|
|
|
/* XXX: send interrupt to 5900? */
|
1998-02-07 00:12:14 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/* decoding */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_DECODE);
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* decode & execute */
|
1998-02-07 00:12:14 +00:00
|
|
|
if(IS_PKE_CMD(cmd, PKENOP))
|
1998-02-11 19:42:15 +00:00
|
|
|
pke_code_nop(me, fw);
|
1998-02-07 00:12:14 +00:00
|
|
|
else if(IS_PKE_CMD(cmd, STCYCL))
|
1998-02-11 19:42:15 +00:00
|
|
|
pke_code_stcycl(me, fw);
|
1998-02-07 00:12:14 +00:00
|
|
|
else if(me->pke_number == 1 && IS_PKE_CMD(cmd, OFFSET))
|
1998-02-11 19:42:15 +00:00
|
|
|
pke_code_offset(me, fw);
|
1998-02-07 00:12:14 +00:00
|
|
|
else if(me->pke_number == 1 && IS_PKE_CMD(cmd, BASE))
|
1998-02-11 19:42:15 +00:00
|
|
|
pke_code_base(me, fw);
|
1998-02-07 00:12:14 +00:00
|
|
|
else if(IS_PKE_CMD(cmd, ITOP))
|
1998-02-11 19:42:15 +00:00
|
|
|
pke_code_itop(me, fw);
|
1998-02-07 00:12:14 +00:00
|
|
|
else if(IS_PKE_CMD(cmd, STMOD))
|
1998-02-11 19:42:15 +00:00
|
|
|
pke_code_stmod(me, fw);
|
|
|
|
else if(me->pke_number == 1 && IS_PKE_CMD(cmd, MSKPATH3))
|
|
|
|
pke_code_mskpath3(me, fw);
|
1998-02-07 00:12:14 +00:00
|
|
|
else if(IS_PKE_CMD(cmd, PKEMARK))
|
1998-02-11 19:42:15 +00:00
|
|
|
pke_code_pkemark(me, fw);
|
1998-02-07 00:12:14 +00:00
|
|
|
else if(IS_PKE_CMD(cmd, FLUSHE))
|
1998-02-11 19:42:15 +00:00
|
|
|
pke_code_flushe(me, fw);
|
1998-02-07 00:12:14 +00:00
|
|
|
else if(me->pke_number == 1 && IS_PKE_CMD(cmd, FLUSH))
|
1998-02-11 19:42:15 +00:00
|
|
|
pke_code_flush(me, fw);
|
|
|
|
else if(me->pke_number == 1 && IS_PKE_CMD(cmd, FLUSHA))
|
|
|
|
pke_code_flusha(me, fw);
|
|
|
|
else if(IS_PKE_CMD(cmd, PKEMSCAL))
|
|
|
|
pke_code_pkemscal(me, fw);
|
|
|
|
else if(IS_PKE_CMD(cmd, PKEMSCNT))
|
|
|
|
pke_code_pkemscnt(me, fw);
|
|
|
|
else if(me->pke_number == 1 && IS_PKE_CMD(cmd, PKEMSCALF))
|
|
|
|
pke_code_pkemscalf(me, fw);
|
|
|
|
else if(IS_PKE_CMD(cmd, STMASK))
|
|
|
|
pke_code_stmask(me, fw);
|
|
|
|
else if(IS_PKE_CMD(cmd, STROW))
|
|
|
|
pke_code_strow(me, fw);
|
|
|
|
else if(IS_PKE_CMD(cmd, STCOL))
|
|
|
|
pke_code_stcol(me, fw);
|
|
|
|
else if(IS_PKE_CMD(cmd, MPG))
|
|
|
|
pke_code_mpg(me, fw);
|
|
|
|
else if(IS_PKE_CMD(cmd, DIRECT))
|
|
|
|
pke_code_direct(me, fw);
|
|
|
|
else if(IS_PKE_CMD(cmd, DIRECTHL))
|
|
|
|
pke_code_directhl(me, fw);
|
|
|
|
else if(IS_PKE_CMD(cmd, UNPACK))
|
|
|
|
pke_code_unpack(me, fw);
|
1998-02-13 23:29:38 +00:00
|
|
|
/* ... no other commands ... */
|
1998-02-11 19:42:15 +00:00
|
|
|
else
|
|
|
|
pke_code_error(me, fw);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/* advance the PC by given number of data words; update STAT/FQC
|
1998-02-18 21:26:38 +00:00
|
|
|
field; assume FIFO is filled enough; classify passed-over words;
|
|
|
|
write FIFO trace line */
|
1998-02-11 19:42:15 +00:00
|
|
|
|
|
|
|
void
|
|
|
|
pke_pc_advance(struct pke_device* me, int num_words)
|
|
|
|
{
|
|
|
|
int num = num_words;
|
1998-02-18 21:26:38 +00:00
|
|
|
struct fifo_quadword* fq = NULL;
|
|
|
|
int skipped = 0;
|
|
|
|
ASSERT(num_words >= 0);
|
1998-02-11 19:42:15 +00:00
|
|
|
|
1998-02-18 21:26:38 +00:00
|
|
|
do
|
1998-02-07 00:12:14 +00:00
|
|
|
{
|
1998-02-18 21:26:38 +00:00
|
|
|
fq = & me->fifo[me->fifo_pc];
|
1998-02-11 19:42:15 +00:00
|
|
|
|
|
|
|
/* skip over DMA tag words if present in word 0 or 1 */
|
1998-02-18 21:26:38 +00:00
|
|
|
if(fq->word_class[me->qw_pc] == wc_dma)
|
1998-02-07 00:12:14 +00:00
|
|
|
{
|
1998-02-11 19:42:15 +00:00
|
|
|
/* skip by going around loop an extra time */
|
|
|
|
num ++;
|
1998-02-18 21:26:38 +00:00
|
|
|
skipped = 1;
|
1998-02-07 00:12:14 +00:00
|
|
|
}
|
1998-02-18 21:26:38 +00:00
|
|
|
else
|
|
|
|
skipped = 0;
|
|
|
|
|
|
|
|
if(num > 0) /* increment PC */
|
|
|
|
{
|
|
|
|
/* one word skipped */
|
|
|
|
num --;
|
|
|
|
|
|
|
|
/* point to next word */
|
|
|
|
me->qw_pc ++;
|
|
|
|
if(me->qw_pc == 4)
|
|
|
|
{
|
|
|
|
me->qw_pc = 0;
|
|
|
|
me->fifo_pc ++;
|
|
|
|
|
|
|
|
/* trace the consumption of this FIFO quadword */
|
|
|
|
if(me->fifo_trace_file != NULL)
|
|
|
|
{
|
|
|
|
/* assert complete classification */
|
|
|
|
ASSERT(fq->word_class[3] != wc_unknown);
|
|
|
|
ASSERT(fq->word_class[2] != wc_unknown);
|
|
|
|
ASSERT(fq->word_class[1] != wc_unknown);
|
|
|
|
ASSERT(fq->word_class[0] != wc_unknown);
|
|
|
|
|
|
|
|
/* print trace record */
|
|
|
|
fprintf(me->fifo_trace_file,
|
|
|
|
"%d 0x%ux_%ux_%ux_%ux 0x%ux %c%c%c%c\n",
|
|
|
|
(me->pke_number == 0 ? 0 : 1),
|
|
|
|
(unsigned) fq->data[3], (unsigned) fq->data[2],
|
|
|
|
(unsigned) fq->data[1], (unsigned) fq->data[0],
|
|
|
|
(unsigned) fq->source_address,
|
|
|
|
fq->word_class[3], fq->word_class[2],
|
|
|
|
fq->word_class[1], fq->word_class[0]);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* XXX: zap old entries in FIFO */
|
|
|
|
|
|
|
|
} /* next quadword */
|
|
|
|
} /* increment PC */
|
|
|
|
} /* eat num words */
|
|
|
|
while(num > 0 || skipped);
|
1998-02-11 19:42:15 +00:00
|
|
|
|
|
|
|
/* clear FQC if FIFO is now empty */
|
|
|
|
if(me->fifo_num_elements == me->fifo_pc)
|
1998-02-07 00:12:14 +00:00
|
|
|
{
|
1998-02-11 19:42:15 +00:00
|
|
|
PKE_REG_MASK_SET(me, STAT, FQC, 0);
|
1998-02-07 00:12:14 +00:00
|
|
|
}
|
1998-02-18 21:26:38 +00:00
|
|
|
else /* annote the word where the PC lands as an PKEcode */
|
|
|
|
{
|
|
|
|
ASSERT(fq->word_class[me->qw_pc] == wc_pkecode ||
|
|
|
|
fq->word_class[me->qw_pc] == wc_unknown);
|
|
|
|
fq->word_class[me->qw_pc] = wc_pkecode;
|
|
|
|
}
|
1998-02-11 19:42:15 +00:00
|
|
|
}
|
1998-02-07 00:12:14 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* Return pointer to FIFO quadword containing given operand# in FIFO.
|
|
|
|
`operand_num' starts at 1. Return pointer to operand word in last
|
|
|
|
argument, if non-NULL. If FIFO is not full enough, return 0.
|
|
|
|
Signal an ER0 indication upon skipping a DMA tag. */
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
struct fifo_quadword*
|
|
|
|
pke_pc_fifo(struct pke_device* me, int operand_num, unsigned_4** operand)
|
|
|
|
{
|
|
|
|
int num = operand_num;
|
|
|
|
int new_qw_pc, new_fifo_pc;
|
1998-02-18 21:26:38 +00:00
|
|
|
struct fifo_quadword* fq = NULL;
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
ASSERT(num > 0);
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* snapshot current pointers */
|
|
|
|
new_fifo_pc = me->fifo_pc;
|
|
|
|
new_qw_pc = me->qw_pc;
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-18 21:26:38 +00:00
|
|
|
do
|
1998-02-11 19:42:15 +00:00
|
|
|
{
|
|
|
|
/* one word skipped */
|
|
|
|
num --;
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* point to next word */
|
|
|
|
new_qw_pc ++;
|
|
|
|
if(new_qw_pc == 4)
|
1998-02-07 00:12:14 +00:00
|
|
|
{
|
1998-02-11 19:42:15 +00:00
|
|
|
new_qw_pc = 0;
|
|
|
|
new_fifo_pc ++;
|
1998-02-07 00:12:14 +00:00
|
|
|
}
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* check for FIFO underflow */
|
|
|
|
if(me->fifo_num_elements == new_fifo_pc)
|
1998-02-07 00:12:14 +00:00
|
|
|
{
|
1998-02-18 21:26:38 +00:00
|
|
|
fq = NULL;
|
1998-02-11 19:42:15 +00:00
|
|
|
break;
|
1998-02-07 00:12:14 +00:00
|
|
|
}
|
1998-02-11 19:42:15 +00:00
|
|
|
|
|
|
|
/* skip over DMA tag words if present in word 0 or 1 */
|
1998-02-18 21:26:38 +00:00
|
|
|
fq = & me->fifo[new_fifo_pc];
|
|
|
|
if(fq->word_class[new_qw_pc] == wc_dma)
|
1998-02-07 00:12:14 +00:00
|
|
|
{
|
1998-02-11 19:42:15 +00:00
|
|
|
/* mismatch error! */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, ER0, 1);
|
|
|
|
/* skip by going around loop an extra time */
|
|
|
|
num ++;
|
1998-02-07 00:12:14 +00:00
|
|
|
}
|
|
|
|
}
|
1998-02-18 21:26:38 +00:00
|
|
|
while(num > 0);
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* return pointer to operand word itself */
|
1998-02-18 21:26:38 +00:00
|
|
|
if(fq != NULL)
|
|
|
|
{
|
|
|
|
*operand = & fq->data[new_qw_pc];
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-18 21:26:38 +00:00
|
|
|
/* annote the word where the pseudo lands as an PKE operand */
|
|
|
|
ASSERT(fq->word_class[new_qw_pc] == wc_pkedata ||
|
|
|
|
fq->word_class[new_qw_pc] == wc_unknown);
|
|
|
|
fq->word_class[new_qw_pc] = wc_pkedata;
|
|
|
|
}
|
|
|
|
|
|
|
|
return fq;
|
1998-02-11 19:42:15 +00:00
|
|
|
}
|
1998-02-07 00:12:14 +00:00
|
|
|
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* Return pointer to given operand# in FIFO. `operand_num' starts at 1.
|
|
|
|
If FIFO is not full enough, return 0. Skip over DMA tags, but mark
|
|
|
|
them as an error (ER0). */
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
unsigned_4*
|
|
|
|
pke_pc_operand(struct pke_device* me, int operand_num)
|
|
|
|
{
|
|
|
|
unsigned_4* operand = NULL;
|
|
|
|
struct fifo_quadword* fifo_operand;
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
fifo_operand = pke_pc_fifo(me, operand_num, & operand);
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
if(fifo_operand == NULL)
|
|
|
|
ASSERT(operand == NULL); /* pke_pc_fifo() ought leave it untouched */
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
return operand;
|
|
|
|
}
|
1998-02-07 00:12:14 +00:00
|
|
|
|
|
|
|
|
1998-02-13 23:29:38 +00:00
|
|
|
/* Return a bit-field extract of given operand# in FIFO, and its
|
|
|
|
source-addr. `bit_offset' starts at 0, referring to LSB after PKE
|
|
|
|
instruction word. Width must be >0, <=32. Assume FIFO is full
|
|
|
|
enough. Skip over DMA tags, but mark them as an error (ER0). */
|
|
|
|
|
|
|
|
unsigned_4
|
|
|
|
pke_pc_operand_bits(struct pke_device* me, int bit_offset, int bit_width, unsigned_4* source_addr)
|
|
|
|
{
|
|
|
|
unsigned_4* word = NULL;
|
|
|
|
unsigned_4 value;
|
|
|
|
struct fifo_quadword* fifo_operand;
|
|
|
|
|
|
|
|
/* find operand word with bitfield */
|
|
|
|
fifo_operand = pke_pc_fifo(me, (bit_offset / 32) + 1, &word);
|
|
|
|
ASSERT(word != 0);
|
|
|
|
|
|
|
|
/* extract bitfield from word */
|
|
|
|
value = BIT_MASK_GET(*word, bit_offset % 32, bit_width);
|
|
|
|
|
|
|
|
/* extract source addr from fifo word */
|
|
|
|
*source_addr = fifo_operand->source_address;
|
|
|
|
|
|
|
|
return value;
|
|
|
|
}
|
|
|
|
|
1998-02-07 00:12:14 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* Write a bunch of bytes into simulator memory. Store the given source address into the
|
|
|
|
PKE sourceaddr tracking word. */
|
|
|
|
int
|
|
|
|
pke_track_write(struct pke_device* me, const void* src, int len,
|
|
|
|
address_word dest, unsigned_4 sourceaddr)
|
|
|
|
{
|
|
|
|
int rc;
|
|
|
|
unsigned_4 no_sourceaddr = 0;
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* write srcaddr into PKE srcaddr tracking */
|
|
|
|
sim_write(NULL,
|
|
|
|
(SIM_ADDR) (me->pke_number == 0) ? PKE0_SRCADDR : PKE1_SRCADDR,
|
|
|
|
(void*) & sourceaddr,
|
|
|
|
sizeof(unsigned_4));
|
|
|
|
|
|
|
|
/* write bytes into simulator */
|
|
|
|
rc = sim_write(NULL,
|
|
|
|
(SIM_ADDR) dest,
|
|
|
|
(void*) src,
|
|
|
|
len);
|
|
|
|
|
|
|
|
/* clear srcaddr from PKE srcaddr tracking */
|
|
|
|
sim_write(NULL,
|
|
|
|
(SIM_ADDR) (me->pke_number == 0) ? PKE0_SRCADDR : PKE1_SRCADDR,
|
|
|
|
(void*) & no_sourceaddr,
|
|
|
|
sizeof(unsigned_4));
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
/* check for stall conditions on indicated devices (path* only on PKE1), do not change status
|
|
|
|
return 0 iff no stall */
|
|
|
|
int
|
|
|
|
pke_check_stall(struct pke_device* me, enum pke_check_target what)
|
|
|
|
{
|
|
|
|
int any_stall = 0;
|
1998-02-18 21:26:38 +00:00
|
|
|
unsigned_4 cop2_stat, gpuif_stat;
|
1998-02-11 19:42:15 +00:00
|
|
|
|
1998-02-18 21:26:38 +00:00
|
|
|
/* read status words */
|
1998-02-11 19:42:15 +00:00
|
|
|
sim_read(NULL,
|
1998-02-13 23:29:38 +00:00
|
|
|
(SIM_ADDR) (GIF_REG_STAT),
|
|
|
|
(void*) & gpuif_stat,
|
1998-02-11 19:42:15 +00:00
|
|
|
sizeof(unsigned_4));
|
|
|
|
|
1998-02-18 21:26:38 +00:00
|
|
|
sim_read(NULL,
|
|
|
|
(SIM_ADDR) (COP2_REG_STAT_ADDR),
|
|
|
|
(void*) & cop2_stat,
|
|
|
|
sizeof(unsigned_4));
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* perform checks */
|
|
|
|
if(what == chk_vu)
|
|
|
|
{
|
1998-02-18 21:26:38 +00:00
|
|
|
if(me->pke_number == 0)
|
|
|
|
any_stall = BIT_MASK_GET(cop2_stat, COP2_REG_STAT_VBS0_B, COP2_REG_STAT_VBS0_E);
|
|
|
|
else /* if(me->pke_number == 1) */
|
|
|
|
any_stall = BIT_MASK_GET(cop2_stat, COP2_REG_STAT_VBS1_B, COP2_REG_STAT_VBS1_E);
|
1998-02-13 23:29:38 +00:00
|
|
|
}
|
|
|
|
else if(what == chk_path1) /* VU -> GPUIF */
|
|
|
|
{
|
|
|
|
if(BIT_MASK_GET(gpuif_stat, GPUIF_REG_STAT_APATH_B, GPUIF_REG_STAT_APATH_E) == 1)
|
1998-02-11 19:42:15 +00:00
|
|
|
any_stall = 1;
|
1998-02-07 00:12:14 +00:00
|
|
|
}
|
1998-02-13 23:29:38 +00:00
|
|
|
else if(what == chk_path2) /* PKE -> GPUIF */
|
1998-02-07 00:12:14 +00:00
|
|
|
{
|
1998-02-13 23:29:38 +00:00
|
|
|
if(BIT_MASK_GET(gpuif_stat, GPUIF_REG_STAT_APATH_B, GPUIF_REG_STAT_APATH_E) == 2)
|
|
|
|
any_stall = 1;
|
|
|
|
}
|
|
|
|
else if(what == chk_path3) /* DMA -> GPUIF */
|
|
|
|
{
|
|
|
|
if(BIT_MASK_GET(gpuif_stat, GPUIF_REG_STAT_APATH_B, GPUIF_REG_STAT_APATH_E) == 3)
|
1998-02-11 19:42:15 +00:00
|
|
|
any_stall = 1;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
1998-02-13 23:29:38 +00:00
|
|
|
/* invalid what */
|
|
|
|
ASSERT(0);
|
1998-02-11 19:42:15 +00:00
|
|
|
}
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* any stall reasons? */
|
|
|
|
return any_stall;
|
|
|
|
}
|
1998-02-07 00:12:14 +00:00
|
|
|
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* flip the DBF bit; recompute TOPS, ITOP & TOP */
|
|
|
|
void
|
|
|
|
pke_flip_dbf(struct pke_device* me)
|
|
|
|
{
|
|
|
|
/* flip DBF */
|
|
|
|
PKE_REG_MASK_SET(me, DBF, DF,
|
|
|
|
PKE_REG_MASK_GET(me, DBF, DF) ? 0 : 1);
|
|
|
|
PKE_REG_MASK_SET(me, STAT, DBF, PKE_REG_MASK_GET(me, DBF, DF));
|
|
|
|
/* compute new TOPS */
|
|
|
|
PKE_REG_MASK_SET(me, TOPS, TOPS,
|
|
|
|
(PKE_REG_MASK_GET(me, BASE, BASE) +
|
|
|
|
(PKE_REG_MASK_GET(me, DBF, DF) *
|
|
|
|
PKE_REG_MASK_GET(me, OFST, OFFSET))));
|
|
|
|
/* compute new ITOP and TOP */
|
|
|
|
PKE_REG_MASK_SET(me, ITOP, ITOP,
|
|
|
|
PKE_REG_MASK_GET(me, ITOPS, ITOPS));
|
|
|
|
PKE_REG_MASK_SET(me, TOP, TOP,
|
|
|
|
PKE_REG_MASK_GET(me, TOPS, TOPS));
|
|
|
|
}
|
1998-02-07 00:12:14 +00:00
|
|
|
|
|
|
|
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* PKEcode handler functions -- responsible for checking and
|
|
|
|
confirming old stall conditions, executing pkecode, updating PC and
|
|
|
|
status registers -- may assume being run on correct PKE unit */
|
|
|
|
|
|
|
|
void
|
|
|
|
pke_code_nop(struct pke_device* me, unsigned_4 pkecode)
|
|
|
|
{
|
|
|
|
/* done */
|
|
|
|
pke_pc_advance(me, 1);
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_IDLE);
|
|
|
|
}
|
1998-02-07 00:12:14 +00:00
|
|
|
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
void
|
|
|
|
pke_code_stcycl(struct pke_device* me, unsigned_4 pkecode)
|
|
|
|
{
|
|
|
|
int imm = BIT_MASK_GET(pkecode, PKE_OPCODE_IMM_B, PKE_OPCODE_IMM_E);
|
|
|
|
/* copy immediate value into CYCLE reg */
|
|
|
|
me->regs[PKE_REG_CYCLE][0] = imm;
|
|
|
|
/* done */
|
|
|
|
pke_pc_advance(me, 1);
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_IDLE);
|
|
|
|
}
|
1998-02-07 00:12:14 +00:00
|
|
|
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
void
|
|
|
|
pke_code_offset(struct pke_device* me, unsigned_4 pkecode)
|
|
|
|
{
|
|
|
|
int imm = BIT_MASK_GET(pkecode, PKE_OPCODE_IMM_B, PKE_OPCODE_IMM_E);
|
|
|
|
/* copy 10 bits to OFFSET field */
|
|
|
|
PKE_REG_MASK_SET(me, OFST, OFFSET, BIT_MASK_GET(imm, 0, 9));
|
|
|
|
/* clear DBF bit */
|
|
|
|
PKE_REG_MASK_SET(me, DBF, DF, 0);
|
|
|
|
/* clear other DBF bit */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, DBF, 0);
|
|
|
|
/* set TOPS = BASE */
|
|
|
|
PKE_REG_MASK_SET(me, TOPS, TOPS, PKE_REG_MASK_GET(me, BASE, BASE));
|
|
|
|
/* done */
|
|
|
|
pke_pc_advance(me, 1);
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_IDLE);
|
|
|
|
}
|
1998-02-07 00:12:14 +00:00
|
|
|
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
void
|
|
|
|
pke_code_base(struct pke_device* me, unsigned_4 pkecode)
|
|
|
|
{
|
|
|
|
int imm = BIT_MASK_GET(pkecode, PKE_OPCODE_IMM_B, PKE_OPCODE_IMM_E);
|
|
|
|
/* copy 10 bits to BASE field */
|
|
|
|
PKE_REG_MASK_SET(me, BASE, BASE, BIT_MASK_GET(imm, 0, 9));
|
|
|
|
/* clear DBF bit */
|
|
|
|
PKE_REG_MASK_SET(me, DBF, DF, 0);
|
|
|
|
/* clear other DBF bit */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, DBF, 0);
|
|
|
|
/* set TOPS = BASE */
|
|
|
|
PKE_REG_MASK_SET(me, TOPS, TOPS, PKE_REG_MASK_GET(me, BASE, BASE));
|
|
|
|
/* done */
|
|
|
|
pke_pc_advance(me, 1);
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_IDLE);
|
|
|
|
}
|
1998-02-07 00:12:14 +00:00
|
|
|
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
void
|
|
|
|
pke_code_itop(struct pke_device* me, unsigned_4 pkecode)
|
|
|
|
{
|
|
|
|
int imm = BIT_MASK_GET(pkecode, PKE_OPCODE_IMM_B, PKE_OPCODE_IMM_E);
|
|
|
|
/* copy 10 bits to ITOPS field */
|
|
|
|
PKE_REG_MASK_SET(me, ITOPS, ITOPS, BIT_MASK_GET(imm, 0, 9));
|
|
|
|
/* done */
|
|
|
|
pke_pc_advance(me, 1);
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_IDLE);
|
|
|
|
}
|
1998-02-07 00:12:14 +00:00
|
|
|
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
void
|
|
|
|
pke_code_stmod(struct pke_device* me, unsigned_4 pkecode)
|
|
|
|
{
|
|
|
|
int imm = BIT_MASK_GET(pkecode, PKE_OPCODE_IMM_B, PKE_OPCODE_IMM_E);
|
|
|
|
/* copy 2 bits to MODE register */
|
|
|
|
PKE_REG_MASK_SET(me, MODE, MDE, BIT_MASK_GET(imm, 0, 2));
|
|
|
|
/* done */
|
|
|
|
pke_pc_advance(me, 1);
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_IDLE);
|
|
|
|
}
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
|
|
|
|
void
|
|
|
|
pke_code_mskpath3(struct pke_device* me, unsigned_4 pkecode)
|
|
|
|
{
|
|
|
|
ASSERT(0);
|
1998-02-13 23:29:38 +00:00
|
|
|
/* XXX: no easy interface toward GPUIF for this purpose */
|
1998-02-11 19:42:15 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
pke_code_pkemark(struct pke_device* me, unsigned_4 pkecode)
|
|
|
|
{
|
|
|
|
int imm = BIT_MASK_GET(pkecode, PKE_OPCODE_IMM_B, PKE_OPCODE_IMM_E);
|
|
|
|
/* copy 16 bits to MARK register */
|
|
|
|
PKE_REG_MASK_SET(me, MARK, MARK, BIT_MASK_GET(imm, 0, 15));
|
|
|
|
/* set MRK bit in STAT register - CPU2 v2.1 docs incorrect */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, MRK, 1);
|
|
|
|
/* done */
|
|
|
|
pke_pc_advance(me, 1);
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_IDLE);
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
pke_code_flushe(struct pke_device* me, unsigned_4 pkecode)
|
|
|
|
{
|
|
|
|
/* compute next PEW bit */
|
|
|
|
if(pke_check_stall(me, chk_vu))
|
|
|
|
{
|
|
|
|
/* VU busy */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PEW, 1);
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_STALL);
|
|
|
|
/* try again next cycle */
|
1998-02-07 00:12:14 +00:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
1998-02-11 19:42:15 +00:00
|
|
|
/* VU idle */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PEW, 0);
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_IDLE);
|
1998-02-07 00:12:14 +00:00
|
|
|
pke_pc_advance(me, 1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
void
|
|
|
|
pke_code_flush(struct pke_device* me, unsigned_4 pkecode)
|
|
|
|
{
|
|
|
|
int something_busy = 0;
|
|
|
|
|
|
|
|
/* compute next PEW, PGW bits */
|
|
|
|
if(pke_check_stall(me, chk_vu))
|
|
|
|
{
|
|
|
|
something_busy = 1;
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PEW, 1);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PEW, 0);
|
1998-02-07 00:12:14 +00:00
|
|
|
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
if(pke_check_stall(me, chk_path1) ||
|
|
|
|
pke_check_stall(me, chk_path2))
|
|
|
|
{
|
|
|
|
something_busy = 1;
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PGW, 1);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PGW, 0);
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* go or no go */
|
|
|
|
if(something_busy)
|
|
|
|
{
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_WAIT);
|
|
|
|
/* try again next cycle */
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* all idle */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_IDLE);
|
|
|
|
pke_pc_advance(me, 1);
|
|
|
|
}
|
|
|
|
}
|
1998-02-07 00:12:14 +00:00
|
|
|
|
|
|
|
|
|
|
|
void
|
1998-02-11 19:42:15 +00:00
|
|
|
pke_code_flusha(struct pke_device* me, unsigned_4 pkecode)
|
1998-02-07 00:12:14 +00:00
|
|
|
{
|
1998-02-11 19:42:15 +00:00
|
|
|
int something_busy = 0;
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* compute next PEW, PGW bits */
|
|
|
|
if(pke_check_stall(me, chk_vu))
|
1998-02-07 00:12:14 +00:00
|
|
|
{
|
1998-02-11 19:42:15 +00:00
|
|
|
something_busy = 1;
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PEW, 1);
|
1998-02-07 00:12:14 +00:00
|
|
|
}
|
1998-02-11 19:42:15 +00:00
|
|
|
else
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PEW, 0);
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
|
|
|
|
if(pke_check_stall(me, chk_path1) ||
|
|
|
|
pke_check_stall(me, chk_path2) ||
|
|
|
|
pke_check_stall(me, chk_path3))
|
1998-02-07 00:12:14 +00:00
|
|
|
{
|
1998-02-11 19:42:15 +00:00
|
|
|
something_busy = 1;
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PGW, 1);
|
1998-02-07 00:12:14 +00:00
|
|
|
}
|
1998-02-11 19:42:15 +00:00
|
|
|
else
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PGW, 0);
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
if(something_busy)
|
|
|
|
{
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_WAIT);
|
|
|
|
/* try again next cycle */
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* all idle */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_IDLE);
|
|
|
|
pke_pc_advance(me, 1);
|
|
|
|
}
|
1998-02-07 00:12:14 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
void
|
|
|
|
pke_code_pkemscal(struct pke_device* me, unsigned_4 pkecode)
|
|
|
|
{
|
|
|
|
/* compute next PEW bit */
|
|
|
|
if(pke_check_stall(me, chk_vu))
|
|
|
|
{
|
|
|
|
/* VU busy */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PEW, 1);
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_STALL);
|
|
|
|
/* try again next cycle */
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
unsigned_4 vu_pc;
|
|
|
|
int imm = BIT_MASK_GET(pkecode, PKE_OPCODE_IMM_B, PKE_OPCODE_IMM_E);
|
|
|
|
|
|
|
|
/* VU idle */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PEW, 0);
|
|
|
|
|
|
|
|
/* flip DBF on PKE1 */
|
|
|
|
if(me->pke_number == 1)
|
|
|
|
pke_flip_dbf(me);
|
|
|
|
|
|
|
|
/* compute new PC for VU */
|
1998-02-13 23:29:38 +00:00
|
|
|
vu_pc = BIT_MASK_GET(imm, 0, 15);
|
1998-02-11 19:42:15 +00:00
|
|
|
/* write new PC; callback function gets VU running */
|
|
|
|
sim_write(NULL,
|
1998-02-18 21:26:38 +00:00
|
|
|
(SIM_ADDR) (me->pke_number == 0 ? VU0_CIA : VU1_CIA),
|
1998-02-11 19:42:15 +00:00
|
|
|
(void*) & vu_pc,
|
|
|
|
sizeof(unsigned_4));
|
|
|
|
|
|
|
|
/* done */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_IDLE);
|
|
|
|
pke_pc_advance(me, 1);
|
|
|
|
}
|
|
|
|
}
|
1998-02-07 00:12:14 +00:00
|
|
|
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
|
|
|
|
void
|
|
|
|
pke_code_pkemscnt(struct pke_device* me, unsigned_4 pkecode)
|
1998-02-07 00:12:14 +00:00
|
|
|
{
|
1998-02-11 19:42:15 +00:00
|
|
|
/* compute next PEW bit */
|
|
|
|
if(pke_check_stall(me, chk_vu))
|
|
|
|
{
|
|
|
|
/* VU busy */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PEW, 1);
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_STALL);
|
|
|
|
/* try again next cycle */
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
unsigned_4 vu_pc;
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* VU idle */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PEW, 0);
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* flip DBF on PKE1 */
|
|
|
|
if(me->pke_number == 1)
|
|
|
|
pke_flip_dbf(me);
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* read old PC */
|
|
|
|
sim_read(NULL,
|
1998-02-18 21:26:38 +00:00
|
|
|
(SIM_ADDR) (me->pke_number == 0 ? VU0_CIA : VU1_CIA),
|
1998-02-11 19:42:15 +00:00
|
|
|
(void*) & vu_pc,
|
|
|
|
sizeof(unsigned_4));
|
|
|
|
|
|
|
|
/* rewrite new PC; callback function gets VU running */
|
|
|
|
sim_write(NULL,
|
1998-02-18 21:26:38 +00:00
|
|
|
(SIM_ADDR) (me->pke_number == 0 ? VU0_CIA : VU1_CIA),
|
1998-02-11 19:42:15 +00:00
|
|
|
(void*) & vu_pc,
|
|
|
|
sizeof(unsigned_4));
|
|
|
|
|
|
|
|
/* done */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_IDLE);
|
|
|
|
pke_pc_advance(me, 1);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
pke_code_pkemscalf(struct pke_device* me, unsigned_4 pkecode)
|
|
|
|
{
|
|
|
|
int something_busy = 0;
|
|
|
|
|
|
|
|
/* compute next PEW, PGW bits */
|
|
|
|
if(pke_check_stall(me, chk_vu))
|
1998-02-07 00:12:14 +00:00
|
|
|
{
|
1998-02-11 19:42:15 +00:00
|
|
|
something_busy = 1;
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PEW, 1);
|
1998-02-07 00:12:14 +00:00
|
|
|
}
|
1998-02-11 19:42:15 +00:00
|
|
|
else
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PEW, 0);
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
|
|
|
|
if(pke_check_stall(me, chk_path1) ||
|
|
|
|
pke_check_stall(me, chk_path2) ||
|
|
|
|
pke_check_stall(me, chk_path3))
|
|
|
|
{
|
|
|
|
something_busy = 1;
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PGW, 1);
|
|
|
|
}
|
1998-02-07 00:12:14 +00:00
|
|
|
else
|
1998-02-11 19:42:15 +00:00
|
|
|
PKE_REG_MASK_SET(me, STAT, PGW, 0);
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* go or no go */
|
|
|
|
if(something_busy)
|
|
|
|
{
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_WAIT);
|
|
|
|
/* try again next cycle */
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
unsigned_4 vu_pc;
|
|
|
|
int imm = BIT_MASK_GET(pkecode, PKE_OPCODE_IMM_B, PKE_OPCODE_IMM_E);
|
|
|
|
|
|
|
|
/* flip DBF on PKE1 */
|
|
|
|
if(me->pke_number == 1)
|
|
|
|
pke_flip_dbf(me);
|
|
|
|
|
|
|
|
/* compute new PC for VU */
|
1998-02-13 23:29:38 +00:00
|
|
|
vu_pc = BIT_MASK_GET(imm, 0, 15);
|
1998-02-11 19:42:15 +00:00
|
|
|
/* write new PC; callback function gets VU running */
|
|
|
|
sim_write(NULL,
|
1998-02-18 21:26:38 +00:00
|
|
|
(SIM_ADDR) (me->pke_number == 0 ? VU0_CIA : VU1_CIA),
|
1998-02-11 19:42:15 +00:00
|
|
|
(void*) & vu_pc,
|
|
|
|
sizeof(unsigned_4));
|
|
|
|
|
|
|
|
/* done */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_IDLE);
|
|
|
|
pke_pc_advance(me, 1);
|
|
|
|
}
|
1998-02-07 00:12:14 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
void
|
|
|
|
pke_code_stmask(struct pke_device* me, unsigned_4 pkecode)
|
|
|
|
{
|
|
|
|
/* check that FIFO has one more word for STMASK operand */
|
|
|
|
unsigned_4* mask;
|
|
|
|
|
|
|
|
mask = pke_pc_operand(me, 1);
|
|
|
|
if(mask != NULL)
|
|
|
|
{
|
|
|
|
/* "transferring" operand */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_XFER);
|
1998-02-13 23:29:38 +00:00
|
|
|
|
|
|
|
/* set NUM */
|
|
|
|
PKE_REG_MASK_SET(me, NUM, NUM, 1);
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* fill the register */
|
|
|
|
PKE_REG_MASK_SET(me, MASK, MASK, *mask);
|
1998-02-13 23:29:38 +00:00
|
|
|
|
|
|
|
/* set NUM */
|
|
|
|
PKE_REG_MASK_SET(me, NUM, NUM, 0);
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* done */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_IDLE);
|
1998-02-18 21:26:38 +00:00
|
|
|
pke_pc_advance(me, 2);
|
1998-02-11 19:42:15 +00:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* need to wait for another word */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_WAIT);
|
|
|
|
/* try again next cycle */
|
|
|
|
}
|
|
|
|
}
|
1998-02-07 00:12:14 +00:00
|
|
|
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
void
|
|
|
|
pke_code_strow(struct pke_device* me, unsigned_4 pkecode)
|
1998-02-07 00:12:14 +00:00
|
|
|
{
|
1998-02-11 19:42:15 +00:00
|
|
|
/* check that FIFO has four more words for STROW operand */
|
|
|
|
unsigned_4* last_op;
|
|
|
|
|
|
|
|
last_op = pke_pc_operand(me, 4);
|
|
|
|
if(last_op != NULL)
|
|
|
|
{
|
|
|
|
/* "transferring" operand */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_XFER);
|
|
|
|
|
1998-02-13 23:29:38 +00:00
|
|
|
/* set NUM */
|
|
|
|
PKE_REG_MASK_SET(me, NUM, NUM, 1);
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* copy ROW registers: must all exist if 4th operand exists */
|
|
|
|
me->regs[PKE_REG_R0][0] = * pke_pc_operand(me, 1);
|
|
|
|
me->regs[PKE_REG_R1][0] = * pke_pc_operand(me, 2);
|
|
|
|
me->regs[PKE_REG_R2][0] = * pke_pc_operand(me, 3);
|
|
|
|
me->regs[PKE_REG_R3][0] = * pke_pc_operand(me, 4);
|
|
|
|
|
1998-02-13 23:29:38 +00:00
|
|
|
/* set NUM */
|
|
|
|
PKE_REG_MASK_SET(me, NUM, NUM, 0);
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* done */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_IDLE);
|
|
|
|
pke_pc_advance(me, 5);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* need to wait for another word */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_WAIT);
|
|
|
|
/* try again next cycle */
|
|
|
|
}
|
|
|
|
}
|
1998-02-06 02:29:22 +00:00
|
|
|
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
void
|
|
|
|
pke_code_stcol(struct pke_device* me, unsigned_4 pkecode)
|
|
|
|
{
|
|
|
|
/* check that FIFO has four more words for STCOL operand */
|
|
|
|
unsigned_4* last_op;
|
|
|
|
|
|
|
|
last_op = pke_pc_operand(me, 4);
|
|
|
|
if(last_op != NULL)
|
1998-02-07 00:12:14 +00:00
|
|
|
{
|
1998-02-11 19:42:15 +00:00
|
|
|
/* "transferring" operand */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_XFER);
|
|
|
|
|
1998-02-13 23:29:38 +00:00
|
|
|
/* set NUM */
|
|
|
|
PKE_REG_MASK_SET(me, NUM, NUM, 1);
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* copy COL registers: must all exist if 4th operand exists */
|
|
|
|
me->regs[PKE_REG_C0][0] = * pke_pc_operand(me, 1);
|
|
|
|
me->regs[PKE_REG_C1][0] = * pke_pc_operand(me, 2);
|
|
|
|
me->regs[PKE_REG_C2][0] = * pke_pc_operand(me, 3);
|
|
|
|
me->regs[PKE_REG_C3][0] = * pke_pc_operand(me, 4);
|
|
|
|
|
1998-02-13 23:29:38 +00:00
|
|
|
/* set NUM */
|
|
|
|
PKE_REG_MASK_SET(me, NUM, NUM, 0);
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* done */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_IDLE);
|
|
|
|
pke_pc_advance(me, 5);
|
1998-02-07 00:12:14 +00:00
|
|
|
}
|
|
|
|
else
|
1998-02-11 19:42:15 +00:00
|
|
|
{
|
|
|
|
/* need to wait for another word */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_WAIT);
|
|
|
|
/* try again next cycle */
|
|
|
|
}
|
|
|
|
}
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
|
|
|
|
void
|
|
|
|
pke_code_mpg(struct pke_device* me, unsigned_4 pkecode)
|
|
|
|
{
|
|
|
|
unsigned_4* last_mpg_word;
|
|
|
|
int num = BIT_MASK_GET(pkecode, PKE_OPCODE_NUM_B, PKE_OPCODE_NUM_E);
|
|
|
|
int imm = BIT_MASK_GET(pkecode, PKE_OPCODE_IMM_B, PKE_OPCODE_IMM_E);
|
|
|
|
|
|
|
|
/* map zero to max+1 */
|
|
|
|
if(num==0) num=0x100;
|
|
|
|
|
|
|
|
/* check that FIFO has a few more words for MPG operand */
|
|
|
|
last_mpg_word = pke_pc_operand(me, num*2); /* num: number of 64-bit words */
|
|
|
|
if(last_mpg_word != NULL)
|
|
|
|
{
|
|
|
|
/* perform implied FLUSHE */
|
1998-02-13 23:29:38 +00:00
|
|
|
if(pke_check_stall(me, chk_vu))
|
1998-02-11 19:42:15 +00:00
|
|
|
{
|
|
|
|
/* VU idle */
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* "transferring" operand */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_XFER);
|
|
|
|
|
|
|
|
/* transfer VU instructions, one word per iteration */
|
|
|
|
for(i=0; i<num*2; i++)
|
|
|
|
{
|
|
|
|
address_word vu_addr_base, vu_addr;
|
|
|
|
address_word vutrack_addr_base, vutrack_addr;
|
|
|
|
unsigned_4* operand;
|
|
|
|
struct fifo_quadword* fq = pke_pc_fifo(me, num, & operand);
|
|
|
|
|
1998-02-13 23:29:38 +00:00
|
|
|
/* set NUM */
|
|
|
|
PKE_REG_MASK_SET(me, NUM, NUM, (num*2 - i) / 2);
|
1998-02-11 19:42:15 +00:00
|
|
|
|
1998-02-13 23:29:38 +00:00
|
|
|
/* imm: in 64-bit units for MPG instruction */
|
1998-02-11 19:42:15 +00:00
|
|
|
/* VU*_MEM0 : instruction memory */
|
|
|
|
vu_addr_base = (me->pke_number == 0) ?
|
|
|
|
VU0_MEM0_WINDOW_START : VU0_MEM0_WINDOW_START;
|
|
|
|
vu_addr = vu_addr_base + (imm*2) + i;
|
|
|
|
|
|
|
|
/* VU*_MEM0_TRACK : source-addr tracking table */
|
|
|
|
vutrack_addr_base = (me->pke_number == 0) ?
|
|
|
|
VU0_MEM0_SRCADDR_START : VU1_MEM0_SRCADDR_START;
|
|
|
|
vutrack_addr = vu_addr_base + (imm*2) + i;
|
|
|
|
|
|
|
|
/* write data into VU memory */
|
|
|
|
pke_track_write(me, operand, sizeof(unsigned_4),
|
|
|
|
vu_addr, fq->source_address);
|
|
|
|
|
|
|
|
/* write srcaddr into VU srcaddr tracking table */
|
|
|
|
sim_write(NULL,
|
|
|
|
(SIM_ADDR) vutrack_addr,
|
|
|
|
(void*) & fq->source_address,
|
|
|
|
sizeof(unsigned_4));
|
|
|
|
} /* VU xfer loop */
|
1998-02-13 23:29:38 +00:00
|
|
|
|
|
|
|
/* check NUM */
|
|
|
|
ASSERT(PKE_REG_MASK_GET(me, NUM, NUM) == 0);
|
1998-02-11 19:42:15 +00:00
|
|
|
|
|
|
|
/* done */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_IDLE);
|
|
|
|
pke_pc_advance(me, 1 + num*2);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* VU busy */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_STALL);
|
|
|
|
/* retry this instruction next clock */
|
|
|
|
}
|
|
|
|
} /* if FIFO full enough */
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* need to wait for another word */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_WAIT);
|
|
|
|
/* retry this instruction next clock */
|
|
|
|
}
|
1998-02-06 02:29:22 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
void
|
|
|
|
pke_code_direct(struct pke_device* me, unsigned_4 pkecode)
|
|
|
|
{
|
|
|
|
/* check that FIFO has a few more words for DIRECT operand */
|
|
|
|
unsigned_4* last_direct_word;
|
|
|
|
int imm = BIT_MASK_GET(pkecode, PKE_OPCODE_IMM_B, PKE_OPCODE_IMM_E);
|
|
|
|
int num = BIT_MASK_GET(pkecode, PKE_OPCODE_NUM_B, PKE_OPCODE_NUM_E);
|
|
|
|
|
|
|
|
/* map zero to max+1 */
|
|
|
|
if(imm==0) imm=0x10000;
|
|
|
|
|
|
|
|
last_direct_word = pke_pc_operand(me, imm*4); /* num: number of 128-bit words */
|
|
|
|
if(last_direct_word != NULL)
|
|
|
|
{
|
|
|
|
/* VU idle */
|
|
|
|
int i;
|
|
|
|
quadword fifo_data;
|
|
|
|
|
|
|
|
/* "transferring" operand */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_XFER);
|
|
|
|
|
|
|
|
/* transfer GPUIF quadwords, one word per iteration */
|
|
|
|
for(i=0; i<imm*4; i++)
|
|
|
|
{
|
|
|
|
unsigned_4* operand;
|
|
|
|
struct fifo_quadword* fq = pke_pc_fifo(me, num, &operand);
|
|
|
|
|
|
|
|
/* collect word into quadword */
|
|
|
|
fifo_data[i%4] = *operand;
|
|
|
|
|
|
|
|
/* write to GPUIF FIFO only with full word */
|
|
|
|
if(i%4 == 3)
|
|
|
|
{
|
1998-02-13 23:29:38 +00:00
|
|
|
address_word gpuif_fifo = GIF_PATH2_FIFO_ADDR+(i/4);
|
1998-02-11 19:42:15 +00:00
|
|
|
pke_track_write(me, fifo_data, sizeof(quadword),
|
|
|
|
(SIM_ADDR) gpuif_fifo, fq->source_address);
|
|
|
|
} /* write collected quadword */
|
|
|
|
|
|
|
|
} /* GPUIF xfer loop */
|
|
|
|
|
|
|
|
/* done */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_IDLE);
|
|
|
|
pke_pc_advance(me, 1 + imm*4);
|
|
|
|
} /* if FIFO full enough */
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* need to wait for another word */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_WAIT);
|
|
|
|
/* retry this instruction next clock */
|
|
|
|
}
|
|
|
|
}
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
|
|
|
|
void
|
|
|
|
pke_code_directhl(struct pke_device* me, unsigned_4 pkecode)
|
1998-02-07 00:12:14 +00:00
|
|
|
{
|
1998-02-11 19:42:15 +00:00
|
|
|
/* treat the same as DIRECTH */
|
|
|
|
pke_code_direct(me, pkecode);
|
|
|
|
}
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
|
|
|
|
void
|
|
|
|
pke_code_unpack(struct pke_device* me, unsigned_4 pkecode)
|
|
|
|
{
|
|
|
|
int imm = BIT_MASK_GET(pkecode, PKE_OPCODE_IMM_B, PKE_OPCODE_IMM_E);
|
|
|
|
int cmd = BIT_MASK_GET(pkecode, PKE_OPCODE_CMD_B, PKE_OPCODE_CMD_E);
|
|
|
|
int num = BIT_MASK_GET(pkecode, PKE_OPCODE_NUM_B, PKE_OPCODE_NUM_E);
|
1998-02-13 23:29:38 +00:00
|
|
|
short vn = BIT_MASK_GET(cmd, 2, 3); /* unpack shape controls */
|
1998-02-11 19:42:15 +00:00
|
|
|
short vl = BIT_MASK_GET(cmd, 0, 1);
|
|
|
|
int m = BIT_MASK_GET(cmd, 4, 4);
|
1998-02-13 23:29:38 +00:00
|
|
|
short cl = PKE_REG_MASK_GET(me, CYCLE, CL); /* cycle controls */
|
1998-02-11 19:42:15 +00:00
|
|
|
short wl = PKE_REG_MASK_GET(me, CYCLE, WL);
|
1998-02-13 23:29:38 +00:00
|
|
|
int r = BIT_MASK_GET(imm, 15, 15); /* indicator bits in imm value */
|
|
|
|
int sx = BIT_MASK_GET(imm, 14, 14);
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
int n, num_operands;
|
|
|
|
unsigned_4* last_operand_word;
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* map zero to max+1 */
|
|
|
|
if(num==0) num=0x100;
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* compute PKEcode length, as given in CPU2 spec, v2.1 pg. 11 */
|
|
|
|
if(wl <= cl)
|
|
|
|
n = num;
|
|
|
|
else
|
|
|
|
n = cl * (num/wl) + PKE_LIMIT(num % wl, cl);
|
1998-02-18 21:26:38 +00:00
|
|
|
num_operands = ((32 >> vl) * (vn+1) * n)/32;
|
1998-02-11 19:42:15 +00:00
|
|
|
|
|
|
|
/* confirm that FIFO has enough words in it */
|
|
|
|
last_operand_word = pke_pc_operand(me, num_operands);
|
|
|
|
if(last_operand_word != NULL)
|
|
|
|
{
|
|
|
|
address_word vu_addr_base;
|
1998-02-13 23:29:38 +00:00
|
|
|
int vector_num;
|
1998-02-11 19:42:15 +00:00
|
|
|
|
|
|
|
/* "transferring" operand */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_XFER);
|
|
|
|
|
|
|
|
/* don't check whether VU is idle */
|
1998-02-13 23:29:38 +00:00
|
|
|
|
|
|
|
/* compute VU address base */
|
1998-02-11 19:42:15 +00:00
|
|
|
if(me->pke_number == 0)
|
|
|
|
vu_addr_base = VU0_MEM1_WINDOW_START + BIT_MASK_GET(imm, 0, 9);
|
|
|
|
else
|
|
|
|
{
|
|
|
|
vu_addr_base = VU1_MEM1_WINDOW_START + BIT_MASK_GET(imm, 0, 9);
|
1998-02-13 23:29:38 +00:00
|
|
|
if(r) vu_addr_base += PKE_REG_MASK_GET(me, TOPS, TOPS);
|
1998-02-11 19:42:15 +00:00
|
|
|
}
|
1998-02-13 23:29:38 +00:00
|
|
|
|
|
|
|
/* set NUM */
|
|
|
|
PKE_REG_MASK_SET(me, NUM, NUM, num);
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* transfer given number of vectors */
|
1998-02-13 23:29:38 +00:00
|
|
|
vector_num = 0; /* output vector number being processed */
|
|
|
|
do
|
1998-02-11 19:42:15 +00:00
|
|
|
{
|
|
|
|
quadword vu_old_data;
|
|
|
|
quadword vu_new_data;
|
|
|
|
quadword unpacked_data;
|
|
|
|
address_word vu_addr;
|
1998-02-13 23:29:38 +00:00
|
|
|
unsigned_4 source_addr = 0;
|
1998-02-11 19:42:15 +00:00
|
|
|
int i;
|
|
|
|
|
1998-02-13 23:29:38 +00:00
|
|
|
/* decrement NUM */
|
|
|
|
PKE_REG_MASK_SET(me, NUM, NUM,
|
|
|
|
PKE_REG_MASK_GET(me, NUM, NUM) - 1);
|
|
|
|
|
1998-02-11 19:42:15 +00:00
|
|
|
/* compute VU destination address, as bytes in R5900 memory */
|
|
|
|
if(cl >= wl)
|
|
|
|
{
|
|
|
|
/* map zero to max+1 */
|
|
|
|
if(wl == 0) wl = 0x0100;
|
|
|
|
vu_addr = vu_addr_base + 16*(cl*(vector_num/wl) + (vector_num%wl));
|
|
|
|
}
|
|
|
|
else
|
|
|
|
vu_addr = vu_addr_base + 16*vector_num;
|
1998-02-13 23:29:38 +00:00
|
|
|
|
|
|
|
/* XXX: can vu_addr overflow? */
|
1998-02-11 19:42:15 +00:00
|
|
|
|
|
|
|
/* read old VU data word at address */
|
|
|
|
sim_read(NULL, (SIM_ADDR) vu_addr, (void*) & vu_old_data, sizeof(vu_old_data));
|
|
|
|
|
|
|
|
/* For cyclic unpack, next operand quadword may come from instruction stream
|
|
|
|
or be zero. */
|
|
|
|
if((cl < wl) && ((vector_num % wl) >= cl)) /* wl != 0, set above */
|
|
|
|
{
|
|
|
|
/* clear operand - used only in a "indeterminate" state */
|
|
|
|
for(i = 0; i < 4; i++)
|
|
|
|
unpacked_data[i] = 0;
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
1998-02-13 23:29:38 +00:00
|
|
|
/* compute packed vector dimensions */
|
|
|
|
int vectorbits, unitbits;
|
|
|
|
|
|
|
|
if(vl < 3) /* PKE_UNPACK_*_{32,16,8} */
|
1998-02-11 19:42:15 +00:00
|
|
|
{
|
1998-02-13 23:29:38 +00:00
|
|
|
unitbits = (32 >> vl);
|
|
|
|
vectorbits = unitbits * (vn+1);
|
|
|
|
}
|
|
|
|
else if(vl == 3 && vn == 3) /* PKE_UNPACK_V4_5 */
|
|
|
|
{
|
|
|
|
unitbits = 5;
|
|
|
|
vectorbits = 16;
|
|
|
|
}
|
|
|
|
else /* illegal unpack variant */
|
|
|
|
{
|
|
|
|
/* treat as illegal instruction */
|
|
|
|
pke_code_error(me, pkecode);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* loop over columns */
|
|
|
|
for(i=0; i<=vn; i++)
|
|
|
|
{
|
|
|
|
unsigned_4 operand;
|
1998-02-07 00:12:14 +00:00
|
|
|
|
1998-02-13 23:29:38 +00:00
|
|
|
/* offset in bits in current operand word */
|
|
|
|
int bitoffset =
|
|
|
|
(vector_num * vectorbits) + (i * unitbits); /* # of bits from PKEcode */
|
1998-02-11 19:42:15 +00:00
|
|
|
|
1998-02-13 23:29:38 +00:00
|
|
|
/* last unit of V4_5 is only one bit wide */
|
|
|
|
if(vl == 3 && vn == 3 && i == 3) /* PKE_UNPACK_V4_5 */
|
|
|
|
unitbits = 1;
|
|
|
|
|
|
|
|
/* fetch bitfield operand */
|
|
|
|
operand = pke_pc_operand_bits(me, bitoffset, unitbits, & source_addr);
|
|
|
|
|
|
|
|
/* selectively sign-extend; not for V4_5 1-bit value */
|
|
|
|
if(sx && unitbits > 0)
|
|
|
|
unpacked_data[i] = SEXT32(operand, unitbits-1);
|
|
|
|
else
|
|
|
|
unpacked_data[i] = operand;
|
1998-02-11 19:42:15 +00:00
|
|
|
}
|
1998-02-13 23:29:38 +00:00
|
|
|
} /* unpack word from instruction operand */
|
1998-02-11 19:42:15 +00:00
|
|
|
|
1998-02-13 23:29:38 +00:00
|
|
|
/* compute replacement word */
|
1998-02-11 19:42:15 +00:00
|
|
|
if(m) /* use mask register? */
|
|
|
|
{
|
|
|
|
/* compute index into mask register for this word */
|
|
|
|
int mask_index = PKE_LIMIT(vector_num % wl, 3); /* wl != 0, set above */
|
|
|
|
|
|
|
|
for(i=0; i<3; i++) /* loop over columns */
|
|
|
|
{
|
|
|
|
int mask_op = PKE_MASKREG_GET(me, mask_index, i);
|
|
|
|
unsigned_4* masked_value = NULL;
|
|
|
|
unsigned_4 zero = 0;
|
|
|
|
|
|
|
|
switch(mask_op)
|
|
|
|
{
|
|
|
|
case PKE_MASKREG_INPUT:
|
|
|
|
/* for vn == 0, all columns are copied from column 0 */
|
|
|
|
if(vn == 0)
|
|
|
|
masked_value = & unpacked_data[0];
|
|
|
|
else if(i > vn)
|
|
|
|
masked_value = & zero; /* arbitrary data: undefined in spec */
|
|
|
|
else
|
|
|
|
masked_value = & unpacked_data[i];
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PKE_MASKREG_ROW: /* exploit R0..R3 contiguity */
|
|
|
|
masked_value = & me->regs[PKE_REG_R0 + i][0];
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PKE_MASKREG_COLUMN: /* exploit C0..C3 contiguity */
|
|
|
|
masked_value = & me->regs[PKE_REG_C0 + PKE_LIMIT(vector_num,3)][0];
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PKE_MASKREG_NOTHING:
|
|
|
|
/* "write inhibit" by re-copying old data */
|
|
|
|
masked_value = & vu_old_data[i];
|
|
|
|
break;
|
|
|
|
|
|
|
|
default:
|
|
|
|
ASSERT(0);
|
|
|
|
/* no other cases possible */
|
|
|
|
}
|
|
|
|
|
|
|
|
/* copy masked value for column */
|
1998-02-13 23:29:38 +00:00
|
|
|
vu_new_data[i] = *masked_value;
|
1998-02-11 19:42:15 +00:00
|
|
|
} /* loop over columns */
|
1998-02-13 23:29:38 +00:00
|
|
|
} /* mask */
|
1998-02-11 19:42:15 +00:00
|
|
|
else
|
|
|
|
{
|
|
|
|
/* no mask - just copy over entire unpacked quadword */
|
|
|
|
memcpy(vu_new_data, unpacked_data, sizeof(unpacked_data));
|
|
|
|
}
|
|
|
|
|
|
|
|
/* process STMOD register for accumulation operations */
|
|
|
|
switch(PKE_REG_MASK_GET(me, MODE, MDE))
|
|
|
|
{
|
|
|
|
case PKE_MODE_ADDROW: /* add row registers to output data */
|
|
|
|
for(i=0; i<4; i++)
|
|
|
|
/* exploit R0..R3 contiguity */
|
|
|
|
vu_new_data[i] += me->regs[PKE_REG_R0 + i][0];
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PKE_MODE_ACCROW: /* add row registers to output data; accumulate */
|
|
|
|
for(i=0; i<4; i++)
|
|
|
|
{
|
|
|
|
/* exploit R0..R3 contiguity */
|
|
|
|
vu_new_data[i] += me->regs[PKE_REG_R0 + i][0];
|
|
|
|
me->regs[PKE_REG_R0 + i][0] = vu_new_data[i];
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
|
|
|
|
case PKE_MODE_INPUT: /* pass data through */
|
|
|
|
default:
|
|
|
|
;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* write replacement word */
|
|
|
|
pke_track_write(me, vu_new_data, sizeof(vu_new_data),
|
1998-02-13 23:29:38 +00:00
|
|
|
(SIM_ADDR) vu_addr, source_addr);
|
1998-02-11 19:42:15 +00:00
|
|
|
|
|
|
|
/* next vector please */
|
|
|
|
vector_num ++;
|
|
|
|
} /* vector transfer loop */
|
1998-02-13 23:29:38 +00:00
|
|
|
while(PKE_REG_MASK_GET(me, NUM, NUM) > 0);
|
1998-02-11 19:42:15 +00:00
|
|
|
|
|
|
|
/* done */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_IDLE);
|
1998-02-18 21:26:38 +00:00
|
|
|
pke_pc_advance(me, 1 + num_operands);
|
1998-02-11 19:42:15 +00:00
|
|
|
} /* PKE FIFO full enough */
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* need to wait for another word */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_WAIT);
|
|
|
|
/* retry this instruction next clock */
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
void
|
|
|
|
pke_code_error(struct pke_device* me, unsigned_4 pkecode)
|
|
|
|
{
|
|
|
|
/* set ER1 flag in STAT register */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, ER1, 1);
|
|
|
|
/* advance over faulty word */
|
|
|
|
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_IDLE);
|
|
|
|
pke_pc_advance(me, 1);
|
1998-02-07 00:12:14 +00:00
|
|
|
}
|