906 lines
24 KiB
C
906 lines
24 KiB
C
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/* CPU family header for m32r.
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Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
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This file is part of the GNU Simulators.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef CPU_M32R_H
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#define CPU_M32R_H
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/* Maximum number of instructions that are fetched at a time.
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This is for LIW type instructions sets (e.g. m32r). */
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#define MAX_LIW_INSNS 2
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/* Maximum number of instructions that can be executed in parallel. */
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#define MAX_PARALLEL_INSNS 1
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/* CPU state information. */
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typedef struct {
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/* Hardware elements. */
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struct {
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/* program counter */
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USI h_pc;
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#define GET_H_PC() CPU (h_pc)
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#define SET_H_PC(x) (CPU (h_pc) = (x))
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/* general registers */
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SI h_gr[16];
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#define GET_H_GR(a1) CPU (h_gr)[a1]
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#define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
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/* control registers */
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SI h_cr[7];
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#define GET_H_CR(a1) CPU (h_cr)[a1]
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#define SET_H_CR(a1, x) (CPU (h_cr)[a1] = (x))
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/* accumulator */
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DI h_accum;
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#define GET_H_ACCUM() CPU (h_accum)
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#define SET_H_ACCUM(x) (CPU (h_accum) = (x))
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/* condition bit */
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UBI h_cond;
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#define GET_H_COND() CPU (h_cond)
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#define SET_H_COND(x) (CPU (h_cond) = (x))
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/* sm */
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UBI h_sm;
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#define GET_H_SM() CPU (h_sm)
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#define SET_H_SM(x) (CPU (h_sm) = (x))
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/* bsm */
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UBI h_bsm;
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#define GET_H_BSM() CPU (h_bsm)
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#define SET_H_BSM(x) (CPU (h_bsm) = (x))
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/* ie */
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UBI h_ie;
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#define GET_H_IE() CPU (h_ie)
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#define SET_H_IE(x) (CPU (h_ie) = (x))
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/* bie */
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UBI h_bie;
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#define GET_H_BIE() CPU (h_bie)
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#define SET_H_BIE(x) (CPU (h_bie) = (x))
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/* bcond */
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UBI h_bcond;
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#define GET_H_BCOND() CPU (h_bcond)
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#define SET_H_BCOND(x) (CPU (h_bcond) = (x))
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/* bpc */
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SI h_bpc;
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#define GET_H_BPC() CPU (h_bpc)
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#define SET_H_BPC(x) (CPU (h_bpc) = (x))
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} hardware;
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#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
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/* CPU profiling state information. */
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struct {
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/* general registers */
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unsigned long h_gr;
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} profile;
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#define CPU_CGEN_PROFILE(cpu) (& (cpu)->cpu_data.profile)
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} M32R_CPU_DATA;
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/* FIXME: length parm to decode() is currently unneeded. */
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extern DECODE *m32r_decode (SIM_CPU *, insn_t /*, int*/);
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/* The ARGBUF struct. */
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struct argbuf {
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/* These are the baseclass definitions. */
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unsigned int length;
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PCADDR addr;
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const struct cgen_insn *opcode;
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/* unsigned long insn; - no longer needed */
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/* cpu specific data follows */
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union {
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struct { /* e.g. add $dr,$sr */
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SI * f_r1;
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SI * f_r2;
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} fmt_0_add;
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struct { /* e.g. add3 $dr,$sr,$slo16 */
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SI * f_r1;
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SI * f_r2;
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HI f_simm16;
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} fmt_1_add3;
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struct { /* e.g. and3 $dr,$sr,$uimm16 */
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SI * f_r1;
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SI * f_r2;
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USI f_uimm16;
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} fmt_2_and3;
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struct { /* e.g. or3 $dr,$sr,$ulo16 */
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SI * f_r1;
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SI * f_r2;
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UHI f_uimm16;
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} fmt_3_or3;
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struct { /* e.g. addi $dr,$simm8 */
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SI * f_r1;
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SI f_simm8;
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} fmt_4_addi;
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struct { /* e.g. addv3 $dr,$sr,$simm16 */
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SI * f_r1;
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SI * f_r2;
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SI f_simm16;
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} fmt_5_addv3;
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struct { /* e.g. addx $dr,$sr */
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SI * f_r1;
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SI * f_r2;
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} fmt_6_addx;
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struct { /* e.g. bc $disp8 */
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IADDR f_disp8;
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} fmt_7_bc8;
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struct { /* e.g. bc $disp24 */
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IADDR f_disp24;
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} fmt_8_bc24;
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struct { /* e.g. beq $src1,$src2,$disp16 */
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SI * f_r1;
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SI * f_r2;
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IADDR f_disp16;
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} fmt_9_beq;
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struct { /* e.g. beqz $src2,$disp16 */
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SI * f_r2;
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IADDR f_disp16;
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} fmt_10_beqz;
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struct { /* e.g. bl $disp8 */
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IADDR f_disp8;
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} fmt_11_bl8;
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struct { /* e.g. bl $disp24 */
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IADDR f_disp24;
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} fmt_12_bl24;
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struct { /* e.g. bra $disp8 */
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IADDR f_disp8;
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} fmt_13_bra8;
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struct { /* e.g. bra $disp24 */
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IADDR f_disp24;
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} fmt_14_bra24;
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struct { /* e.g. cmp $src1,$src2 */
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SI * f_r1;
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SI * f_r2;
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} fmt_15_cmp;
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struct { /* e.g. cmpi $src2,$simm16 */
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SI * f_r2;
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SI f_simm16;
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} fmt_16_cmpi;
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struct { /* e.g. cmpui $src2,$uimm16 */
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SI * f_r2;
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USI f_uimm16;
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} fmt_17_cmpui;
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struct { /* e.g. div $dr,$sr */
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SI * f_r1;
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SI * f_r2;
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} fmt_18_div;
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struct { /* e.g. jl $sr */
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SI * f_r2;
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} fmt_19_jl;
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struct { /* e.g. jmp $sr */
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SI * f_r2;
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} fmt_20_jmp;
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struct { /* e.g. ld $dr,@$sr */
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SI * f_r1;
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SI * f_r2;
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} fmt_21_ld;
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struct { /* e.g. ld $dr,@($slo16,$sr) */
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SI * f_r1;
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SI * f_r2;
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HI f_simm16;
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} fmt_22_ld_d;
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struct { /* e.g. ldb $dr,@$sr */
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SI * f_r1;
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SI * f_r2;
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} fmt_23_ldb;
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struct { /* e.g. ldb $dr,@($slo16,$sr) */
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SI * f_r1;
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SI * f_r2;
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HI f_simm16;
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} fmt_24_ldb_d;
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struct { /* e.g. ldh $dr,@$sr */
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SI * f_r1;
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SI * f_r2;
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} fmt_25_ldh;
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struct { /* e.g. ldh $dr,@($slo16,$sr) */
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SI * f_r1;
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SI * f_r2;
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HI f_simm16;
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} fmt_26_ldh_d;
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struct { /* e.g. ld24 $dr,$uimm24 */
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SI * f_r1;
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ADDR f_uimm24;
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} fmt_27_ld24;
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struct { /* e.g. ldi $dr,$simm8 */
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SI * f_r1;
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SI f_simm8;
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} fmt_28_ldi8;
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struct { /* e.g. ldi $dr,$slo16 */
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SI * f_r1;
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HI f_simm16;
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} fmt_29_ldi16;
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struct { /* e.g. machi $src1,$src2 */
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SI * f_r1;
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SI * f_r2;
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} fmt_30_machi;
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struct { /* e.g. mv $dr,$sr */
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SI * f_r1;
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SI * f_r2;
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} fmt_31_mv;
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struct { /* e.g. mvfachi $dr */
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SI * f_r1;
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} fmt_32_mvfachi;
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struct { /* e.g. mvfc $dr,$scr */
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SI * f_r1;
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UINT f_r2;
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} fmt_33_mvfc;
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struct { /* e.g. mvtachi $src1 */
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SI * f_r1;
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} fmt_34_mvtachi;
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struct { /* e.g. mvtc $sr,$dcr */
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UINT f_r1;
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SI * f_r2;
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} fmt_35_mvtc;
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struct { /* e.g. nop */
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int empty;
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} fmt_36_nop;
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struct { /* e.g. rac */
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int empty;
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} fmt_37_rac;
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struct { /* e.g. seth $dr,$hi16 */
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SI * f_r1;
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UHI f_hi16;
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} fmt_38_seth;
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struct { /* e.g. slli $dr,$uimm5 */
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SI * f_r1;
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USI f_uimm5;
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} fmt_39_slli;
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struct { /* e.g. st $src1,@($slo16,$src2) */
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SI * f_r1;
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SI * f_r2;
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HI f_simm16;
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} fmt_40_st_d;
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struct { /* e.g. trap $uimm4 */
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USI f_uimm4;
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} fmt_41_trap;
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} fields;
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#if 1 || WITH_PROFILE_MODEL_P /*FIXME:wip*/
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unsigned long h_gr_get;
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unsigned long h_gr_set;
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#endif
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};
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/* A cached insn.
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This is also used in the non-scache case. In this situation we assume
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the cache size is 1, and do a few things a little differently. */
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struct scache {
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IADDR next;
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union {
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#if ! WITH_SEM_SWITCH_FULL
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SEMANTIC_FN *sem_fn;
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#endif
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#if ! WITH_SEM_SWITCH_FAST
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#if WITH_SCACHE
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SEMANTIC_CACHE_FN *sem_fast_fn;
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#else
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SEMANTIC_FN *sem_fast_fn;
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#endif
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#endif
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#if WITH_SEM_SWITCH_FULL || WITH_SEM_SWITCH_FAST
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#ifdef __GNUC__
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void *sem_case;
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#else
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int sem_case;
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#endif
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#endif
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} semantic;
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struct argbuf argbuf;
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};
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/* Macros to simplify extraction, reading and semantic code.
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These define and assign the local vars that contain the insn's fields. */
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#define EXTRACT_FMT_0_ADD_VARS \
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/* Instruction fields. */ \
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UINT f_op1; \
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
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unsigned int length;
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#define EXTRACT_FMT_0_ADD_CODE \
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length = 2; \
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f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
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f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
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f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
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f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
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#define EXTRACT_FMT_1_ADD3_VARS \
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/* Instruction fields. */ \
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UINT f_op1; \
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
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int f_simm16; \
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unsigned int length;
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#define EXTRACT_FMT_1_ADD3_CODE \
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length = 4; \
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f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
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f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
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f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
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f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
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f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
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#define EXTRACT_FMT_2_AND3_VARS \
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/* Instruction fields. */ \
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UINT f_op1; \
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
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UINT f_uimm16; \
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unsigned int length;
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#define EXTRACT_FMT_2_AND3_CODE \
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length = 4; \
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f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
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f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
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f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
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f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
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f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
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#define EXTRACT_FMT_3_OR3_VARS \
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/* Instruction fields. */ \
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UINT f_op1; \
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
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UINT f_uimm16; \
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unsigned int length;
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#define EXTRACT_FMT_3_OR3_CODE \
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length = 4; \
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f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
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f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
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f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
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f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
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f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
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#define EXTRACT_FMT_4_ADDI_VARS \
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/* Instruction fields. */ \
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UINT f_op1; \
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UINT f_r1; \
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int f_simm8; \
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unsigned int length;
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#define EXTRACT_FMT_4_ADDI_CODE \
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length = 2; \
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f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
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f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
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f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
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#define EXTRACT_FMT_5_ADDV3_VARS \
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/* Instruction fields. */ \
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UINT f_op1; \
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UINT f_r1; \
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UINT f_op2; \
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UINT f_r2; \
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int f_simm16; \
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unsigned int length;
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#define EXTRACT_FMT_5_ADDV3_CODE \
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length = 4; \
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f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
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f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
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f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
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f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
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f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
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||
|
#define EXTRACT_FMT_6_ADDX_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
UINT f_op2; \
|
||
|
UINT f_r2; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_6_ADDX_CODE \
|
||
|
length = 2; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||
|
|
||
|
#define EXTRACT_FMT_7_BC8_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
int f_disp8; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_7_BC8_CODE \
|
||
|
length = 2; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||
|
f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
|
||
|
|
||
|
#define EXTRACT_FMT_8_BC24_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
int f_disp24; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_8_BC24_CODE \
|
||
|
length = 4; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
||
|
f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
|
||
|
|
||
|
#define EXTRACT_FMT_9_BEQ_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
UINT f_op2; \
|
||
|
UINT f_r2; \
|
||
|
int f_disp16; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_9_BEQ_CODE \
|
||
|
length = 4; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
||
|
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
|
||
|
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
||
|
f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2; \
|
||
|
|
||
|
#define EXTRACT_FMT_10_BEQZ_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
UINT f_op2; \
|
||
|
UINT f_r2; \
|
||
|
int f_disp16; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_10_BEQZ_CODE \
|
||
|
length = 4; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
||
|
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
|
||
|
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
||
|
f_disp16 = EXTRACT_SIGNED (insn, 32, 16, 16) << 2; \
|
||
|
|
||
|
#define EXTRACT_FMT_11_BL8_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
int f_disp8; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_11_BL8_CODE \
|
||
|
length = 2; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||
|
f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
|
||
|
|
||
|
#define EXTRACT_FMT_12_BL24_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
int f_disp24; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_12_BL24_CODE \
|
||
|
length = 4; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
||
|
f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
|
||
|
|
||
|
#define EXTRACT_FMT_13_BRA8_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
int f_disp8; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_13_BRA8_CODE \
|
||
|
length = 2; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||
|
f_disp8 = EXTRACT_SIGNED (insn, 16, 8, 8) << 2; \
|
||
|
|
||
|
#define EXTRACT_FMT_14_BRA24_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
int f_disp24; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_14_BRA24_CODE \
|
||
|
length = 4; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
||
|
f_disp24 = EXTRACT_SIGNED (insn, 32, 8, 24) << 2; \
|
||
|
|
||
|
#define EXTRACT_FMT_15_CMP_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
UINT f_op2; \
|
||
|
UINT f_r2; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_15_CMP_CODE \
|
||
|
length = 2; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||
|
|
||
|
#define EXTRACT_FMT_16_CMPI_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
UINT f_op2; \
|
||
|
UINT f_r2; \
|
||
|
int f_simm16; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_16_CMPI_CODE \
|
||
|
length = 4; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
||
|
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
|
||
|
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
||
|
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
|
||
|
|
||
|
#define EXTRACT_FMT_17_CMPUI_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
UINT f_op2; \
|
||
|
UINT f_r2; \
|
||
|
UINT f_uimm16; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_17_CMPUI_CODE \
|
||
|
length = 4; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
||
|
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
|
||
|
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
||
|
f_uimm16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
|
||
|
|
||
|
#define EXTRACT_FMT_18_DIV_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
UINT f_op2; \
|
||
|
UINT f_r2; \
|
||
|
int f_simm16; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_18_DIV_CODE \
|
||
|
length = 4; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
||
|
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
|
||
|
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
||
|
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
|
||
|
|
||
|
#define EXTRACT_FMT_19_JL_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
UINT f_op2; \
|
||
|
UINT f_r2; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_19_JL_CODE \
|
||
|
length = 2; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||
|
|
||
|
#define EXTRACT_FMT_20_JMP_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
UINT f_op2; \
|
||
|
UINT f_r2; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_20_JMP_CODE \
|
||
|
length = 2; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||
|
|
||
|
#define EXTRACT_FMT_21_LD_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
UINT f_op2; \
|
||
|
UINT f_r2; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_21_LD_CODE \
|
||
|
length = 2; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||
|
|
||
|
#define EXTRACT_FMT_22_LD_D_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
UINT f_op2; \
|
||
|
UINT f_r2; \
|
||
|
int f_simm16; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_22_LD_D_CODE \
|
||
|
length = 4; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
||
|
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
|
||
|
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
||
|
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
|
||
|
|
||
|
#define EXTRACT_FMT_23_LDB_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
UINT f_op2; \
|
||
|
UINT f_r2; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_23_LDB_CODE \
|
||
|
length = 2; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||
|
|
||
|
#define EXTRACT_FMT_24_LDB_D_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
UINT f_op2; \
|
||
|
UINT f_r2; \
|
||
|
int f_simm16; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_24_LDB_D_CODE \
|
||
|
length = 4; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
||
|
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
|
||
|
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
||
|
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
|
||
|
|
||
|
#define EXTRACT_FMT_25_LDH_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
UINT f_op2; \
|
||
|
UINT f_r2; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_25_LDH_CODE \
|
||
|
length = 2; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||
|
|
||
|
#define EXTRACT_FMT_26_LDH_D_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
UINT f_op2; \
|
||
|
UINT f_r2; \
|
||
|
int f_simm16; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_26_LDH_D_CODE \
|
||
|
length = 4; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
||
|
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
|
||
|
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
||
|
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
|
||
|
|
||
|
#define EXTRACT_FMT_27_LD24_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
UINT f_uimm24; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_27_LD24_CODE \
|
||
|
length = 4; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
||
|
f_uimm24 = EXTRACT_UNSIGNED (insn, 32, 8, 24); \
|
||
|
|
||
|
#define EXTRACT_FMT_28_LDI8_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
int f_simm8; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_28_LDI8_CODE \
|
||
|
length = 2; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||
|
f_simm8 = EXTRACT_SIGNED (insn, 16, 8, 8); \
|
||
|
|
||
|
#define EXTRACT_FMT_29_LDI16_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
UINT f_op2; \
|
||
|
UINT f_r2; \
|
||
|
int f_simm16; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_29_LDI16_CODE \
|
||
|
length = 4; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
||
|
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
|
||
|
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
||
|
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
|
||
|
|
||
|
#define EXTRACT_FMT_30_MACHI_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
UINT f_op2; \
|
||
|
UINT f_r2; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_30_MACHI_CODE \
|
||
|
length = 2; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||
|
|
||
|
#define EXTRACT_FMT_31_MV_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
UINT f_op2; \
|
||
|
UINT f_r2; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_31_MV_CODE \
|
||
|
length = 2; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||
|
|
||
|
#define EXTRACT_FMT_32_MVFACHI_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
UINT f_op2; \
|
||
|
UINT f_r2; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_32_MVFACHI_CODE \
|
||
|
length = 2; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||
|
|
||
|
#define EXTRACT_FMT_33_MVFC_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
UINT f_op2; \
|
||
|
UINT f_r2; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_33_MVFC_CODE \
|
||
|
length = 2; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||
|
|
||
|
#define EXTRACT_FMT_34_MVTACHI_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
UINT f_op2; \
|
||
|
UINT f_r2; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_34_MVTACHI_CODE \
|
||
|
length = 2; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||
|
|
||
|
#define EXTRACT_FMT_35_MVTC_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
UINT f_op2; \
|
||
|
UINT f_r2; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_35_MVTC_CODE \
|
||
|
length = 2; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||
|
|
||
|
#define EXTRACT_FMT_36_NOP_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
UINT f_op2; \
|
||
|
UINT f_r2; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_36_NOP_CODE \
|
||
|
length = 2; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||
|
|
||
|
#define EXTRACT_FMT_37_RAC_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
UINT f_op2; \
|
||
|
UINT f_r2; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_37_RAC_CODE \
|
||
|
length = 2; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||
|
f_r2 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||
|
|
||
|
#define EXTRACT_FMT_38_SETH_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
UINT f_op2; \
|
||
|
UINT f_r2; \
|
||
|
UINT f_hi16; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_38_SETH_CODE \
|
||
|
length = 4; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
||
|
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
|
||
|
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
||
|
f_hi16 = EXTRACT_UNSIGNED (insn, 32, 16, 16); \
|
||
|
|
||
|
#define EXTRACT_FMT_39_SLLI_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
UINT f_shift_op2; \
|
||
|
UINT f_uimm5; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_39_SLLI_CODE \
|
||
|
length = 2; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||
|
f_shift_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 3); \
|
||
|
f_uimm5 = EXTRACT_UNSIGNED (insn, 16, 11, 5); \
|
||
|
|
||
|
#define EXTRACT_FMT_40_ST_D_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
UINT f_op2; \
|
||
|
UINT f_r2; \
|
||
|
int f_simm16; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_40_ST_D_CODE \
|
||
|
length = 4; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 32, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 32, 4, 4); \
|
||
|
f_op2 = EXTRACT_UNSIGNED (insn, 32, 8, 4); \
|
||
|
f_r2 = EXTRACT_UNSIGNED (insn, 32, 12, 4); \
|
||
|
f_simm16 = EXTRACT_SIGNED (insn, 32, 16, 16); \
|
||
|
|
||
|
#define EXTRACT_FMT_41_TRAP_VARS \
|
||
|
/* Instruction fields. */ \
|
||
|
UINT f_op1; \
|
||
|
UINT f_r1; \
|
||
|
UINT f_op2; \
|
||
|
UINT f_uimm4; \
|
||
|
unsigned int length;
|
||
|
#define EXTRACT_FMT_41_TRAP_CODE \
|
||
|
length = 2; \
|
||
|
f_op1 = EXTRACT_UNSIGNED (insn, 16, 0, 4); \
|
||
|
f_r1 = EXTRACT_UNSIGNED (insn, 16, 4, 4); \
|
||
|
f_op2 = EXTRACT_UNSIGNED (insn, 16, 8, 4); \
|
||
|
f_uimm4 = EXTRACT_UNSIGNED (insn, 16, 12, 4); \
|
||
|
|
||
|
#endif /* CPU_M32R_H */
|