273 lines
9.3 KiB
Text
273 lines
9.3 KiB
Text
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@c Copyright (C) 1991, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
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@c This is part of the GAS manual.
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@c For copying conditions, see the file as.texinfo.
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@page
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@node H8/500-Dependent
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@chapter H8/500 Dependent Features
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@cindex H8/500 support
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@menu
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* H8/500 Options:: Options
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* H8/500 Syntax:: Syntax
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* H8/500 Floating Point:: Floating Point
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* H8/500 Directives:: H8/500 Machine Directives
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* H8/500 Opcodes:: Opcodes
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@end menu
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@node H8/500 Options
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@section Options
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@cindex H8/500 options (none)
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@cindex options, H8/500 (none)
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@code{@value{AS}} has no additional command-line options for the Hitachi
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H8/500 family.
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@node H8/500 Syntax
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@section Syntax
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@menu
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* H8/500-Chars:: Special Characters
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* H8/500-Regs:: Register Names
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* H8/500-Addressing:: Addressing Modes
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@end menu
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@node H8/500-Chars
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@subsection Special Characters
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@cindex line comment character, H8/500
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@cindex H8/500 line comment character
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@samp{!} is the line comment character.
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@cindex line separator, H8/500
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@cindex statement separator, H8/500
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@cindex H8/500 line separator
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@samp{;} can be used instead of a newline to separate statements.
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@cindex symbol names, @samp{$} in
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@cindex @code{$} in symbol names
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Since @samp{$} has no special meaning, you may use it in symbol names.
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@node H8/500-Regs
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@subsection Register Names
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@cindex H8/500 registers
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@cindex registers, H8/500
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You can use the predefined symbols @samp{r0}, @samp{r1}, @samp{r2},
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@samp{r3}, @samp{r4}, @samp{r5}, @samp{r6}, and @samp{r7} to refer to
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the H8/500 registers.
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The H8/500 also has these control registers:
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@table @code
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@item cp
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code pointer
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@item dp
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data pointer
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@item bp
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base pointer
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@item tp
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stack top pointer
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@item ep
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extra pointer
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@item sr
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status register
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@item ccr
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condition code register
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@end table
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All registers are 16 bits long. To represent 32 bit numbers, use two
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adjacent registers; for distant memory addresses, use one of the segment
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pointers (@code{cp} for the program counter; @code{dp} for
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@code{r0}--@code{r3}; @code{ep} for @code{r4} and @code{r5}; and
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@code{tp} for @code{r6} and @code{r7}.
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@node H8/500-Addressing
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@subsection Addressing Modes
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@cindex addressing modes, H8/500
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@cindex H8/500 addressing modes
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@value{AS} understands the following addressing modes for the H8/500:
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@table @code
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@item R@var{n}
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Register direct
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@item @@R@var{n}
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Register indirect
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@item @@(d:8, R@var{n})
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Register indirect with 8 bit signed displacement
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@item @@(d:16, R@var{n})
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Register indirect with 16 bit signed displacement
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@item @@-R@var{n}
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Register indirect with pre-decrement
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@item @@R@var{n}+
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Register indirect with post-increment
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@item @@@var{aa}:8
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8 bit absolute address
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@item @@@var{aa}:16
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16 bit absolute address
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@item #@var{xx}:8
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8 bit immediate
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@item #@var{xx}:16
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16 bit immediate
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@end table
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@node H8/500 Floating Point
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@section Floating Point
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@cindex floating point, H8/500 (@sc{ieee})
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@cindex H8/500 floating point (@sc{ieee})
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The H8/500 family has no hardware floating point, but the @code{.float}
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directive generates @sc{ieee} floating-point numbers for compatibility
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with other development tools.
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@node H8/500 Directives
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@section H8/500 Machine Directives
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@cindex H8/500 machine directives (none)
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@cindex machine directives, H8/500 (none)
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@cindex @code{word} directive, H8/500
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@cindex @code{int} directive, H8/500
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@code{@value{AS}} has no machine-dependent directives for the H8/500.
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However, on this platform the @samp{.int} and @samp{.word} directives
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generate 16-bit numbers.
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@node H8/500 Opcodes
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@section Opcodes
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@cindex H8/500 opcode summary
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@cindex opcode summary, H8/500
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@cindex mnemonics, H8/500
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@cindex instruction summary, H8/500
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For detailed information on the H8/500 machine instruction set, see
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@cite{H8/500 Series Programming Manual} (Hitachi M21T001).
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@code{@value{AS}} implements all the standard H8/500 opcodes. No additional
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pseudo-instructions are needed on this family.
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@ifset SMALL
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@c this table, due to the multi-col faking and hardcoded order, looks silly
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@c except in smallbook. See comments below "@set SMALL" near top of this file.
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The following table summarizes H8/500 opcodes and their operands:
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@c Use @group if it ever works, instead of @page
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@page
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@smallexample
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@i{Legend:}
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abs8 @r{8-bit absolute address}
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abs16 @r{16-bit absolute address}
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abs24 @r{24-bit absolute address}
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crb @r{@code{ccr}, @code{br}, @code{ep}, @code{dp}, @code{tp}, @code{dp}}
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disp8 @r{8-bit displacement}
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ea @r{@code{rn}, @code{@@rn}, @code{@@(d:8, rn)}, @code{@@(d:16, rn)},}
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@r{@code{@@-rn}, @code{@@rn+}, @code{@@aa:8}, @code{@@aa:16},}
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@r{@code{#xx:8}, @code{#xx:16}}
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ea_mem @r{@code{@@rn}, @code{@@(d:8, rn)}, @code{@@(d:16, rn)},}
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@r{@code{@@-rn}, @code{@@rn+}, @code{@@aa:8}, @code{@@aa:16}}
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ea_noimm @r{@code{rn}, @code{@@rn}, @code{@@(d:8, rn)}, @code{@@(d:16, rn)},}
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@r{@code{@@-rn}, @code{@@rn+}, @code{@@aa:8}, @code{@@aa:16}}
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fp r6
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imm4 @r{4-bit immediate data}
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imm8 @r{8-bit immediate data}
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imm16 @r{16-bit immediate data}
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pcrel8 @r{8-bit offset from program counter}
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pcrel16 @r{16-bit offset from program counter}
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qim @r{@code{-2}, @code{-1}, @code{1}, @code{2}}
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rd @r{any register}
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rs @r{a register distinct from rd}
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rlist @r{comma-separated list of registers in parentheses;}
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@r{register ranges @code{rd-rs} are allowed}
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sp @r{stack pointer (@code{r7})}
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sr @r{status register}
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sz @r{size; @samp{.b} or @samp{.w}. If omitted, default @samp{.w}}
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ldc[.b] ea,crb bcc[.w] pcrel16
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ldc[.w] ea,sr bcc[.b] pcrel8
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add[:q] sz qim,ea_noimm bhs[.w] pcrel16
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add[:g] sz ea,rd bhs[.b] pcrel8
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adds sz ea,rd bcs[.w] pcrel16
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addx sz ea,rd bcs[.b] pcrel8
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and sz ea,rd blo[.w] pcrel16
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andc[.b] imm8,crb blo[.b] pcrel8
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andc[.w] imm16,sr bne[.w] pcrel16
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bpt bne[.b] pcrel8
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bra[.w] pcrel16 beq[.w] pcrel16
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bra[.b] pcrel8 beq[.b] pcrel8
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bt[.w] pcrel16 bvc[.w] pcrel16
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bt[.b] pcrel8 bvc[.b] pcrel8
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brn[.w] pcrel16 bvs[.w] pcrel16
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brn[.b] pcrel8 bvs[.b] pcrel8
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bf[.w] pcrel16 bpl[.w] pcrel16
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bf[.b] pcrel8 bpl[.b] pcrel8
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bhi[.w] pcrel16 bmi[.w] pcrel16
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bhi[.b] pcrel8 bmi[.b] pcrel8
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bls[.w] pcrel16 bge[.w] pcrel16
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bls[.b] pcrel8 bge[.b] pcrel8
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@page
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blt[.w] pcrel16 mov[:g][.b] imm8,ea_mem
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blt[.b] pcrel8 mov[:g][.w] imm16,ea_mem
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bgt[.w] pcrel16 movfpe[.b] ea,rd
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bgt[.b] pcrel8 movtpe[.b] rs,ea_noimm
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ble[.w] pcrel16 mulxu sz ea,rd
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ble[.b] pcrel8 neg sz ea
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bclr sz imm4,ea_noimm nop
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bclr sz rs,ea_noimm not sz ea
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bnot sz imm4,ea_noimm or sz ea,rd
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bnot sz rs,ea_noimm orc[.b] imm8,crb
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bset sz imm4,ea_noimm orc[.w] imm16,sr
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bset sz rs,ea_noimm pjmp abs24
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bsr[.b] pcrel8 pjmp @@rd
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bsr[.w] pcrel16 pjsr abs24
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btst sz imm4,ea_noimm pjsr @@rd
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btst sz rs,ea_noimm prtd imm8
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clr sz ea prtd imm16
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cmp[:e][.b] imm8,rd prts
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cmp[:i][.w] imm16,rd rotl sz ea
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cmp[:g].b imm8,ea_noimm rotr sz ea
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cmp[:g][.w] imm16,ea_noimm rotxl sz ea
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Cmp[:g] sz ea,rd rotxr sz ea
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dadd rs,rd rtd imm8
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divxu sz ea,rd rtd imm16
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dsub rs,rd rts
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exts[.b] rd scb/f rs,pcrel8
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extu[.b] rd scb/ne rs,pcrel8
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jmp @@rd scb/eq rs,pcrel8
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jmp @@(imm8,rd) shal sz ea
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jmp @@(imm16,rd) shar sz ea
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jmp abs16 shll sz ea
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jsr @@rd shlr sz ea
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jsr @@(imm8,rd) sleep
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jsr @@(imm16,rd) stc[.b] crb,ea_noimm
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jsr abs16 stc[.w] sr,ea_noimm
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ldm @@sp+,(rlist) stm (rlist),@@-sp
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link fp,imm8 sub sz ea,rd
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link fp,imm16 subs sz ea,rd
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mov[:e][.b] imm8,rd subx sz ea,rd
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mov[:i][.w] imm16,rd swap[.b] rd
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mov[:l][.w] abs8,rd tas[.b] ea
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mov[:l].b abs8,rd trapa imm4
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mov[:s][.w] rs,abs8 trap/vs
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mov[:s].b rs,abs8 tst sz ea
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mov[:f][.w] @@(disp8,fp),rd unlk fp
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mov[:f][.w] rs,@@(disp8,fp) xch[.w] rs,rd
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mov[:f].b @@(disp8,fp),rd xor sz ea,rd
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mov[:f].b rs,@@(disp8,fp) xorc.b imm8,crb
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mov[:g] sz rs,ea_mem xorc.w imm16,sr
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mov[:g] sz ea,rd
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@end smallexample
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@end ifset
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