old-cross-binutils/ld/testsuite/ld-arc/nps-1a.d

#source: nps-1.s
#as: -mcpu=nps400
#ld: -defsym=foo=0x57f03000
#objdump: -d

.*: +file format .*arc.*

Disassembly of section .text:

[0-9a-f]+ <.*>:
 *[0-9a-f]+:	5948 3000           	xldb	r10,\[0x57f03000\]
 *[0-9a-f]+:	5949 3000           	xldw	r10,\[0x57f03000\]
 *[0-9a-f]+:	594a 3000           	xld	r10,\[0x57f03000\]
 *[0-9a-f]+:	594c 3000           	xstb	r10,\[0x57f03000\]
 *[0-9a-f]+:	594d 3000           	xstw	r10,\[0x57f03000\]
 *[0-9a-f]+:	594e 3000           	xst	r10,\[0x57f03000\]
arc/nps400 : New cmem instructions and associated relocation Add support for arc/nps400 cmem instructions, these load and store instructions are hard-wired to access "0x57f00000 + 16-bit-offset". Supporting this relocation required some additions to the arc relocation handling in the bfd library, as well as the standard changes required to add a new relocation type. There's a test of the new instructions in the assembler, and a test of the relocation in the linker. bfd/ChangeLog: * reloc.c: Add BFD_RELOC_ARC_NPS_CMEM16 entry. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. * elf32-arc.c: Add 'opcode/arc.h' include. (struct arc_relocation_data): Add symbol_name. (arc_special_overflow_checks): New function. (arc_do_relocation): Use arc_special_overflow_checks, reindent as required, add an extra comment. (elf_arc_relocate_section): Setup symbol_name in reloc_data. gas/ChangeLog: * testsuite/gas/arc/nps400-3.d: New file. * testsuite/gas/arc/nps400-3.s: New file. include/ChangeLog: * elf/arc-reloc.def: Add ARC_NPS_CMEM16 reloc. * opcode/arc.h (NPS_CMEM_HIGH_VALUE): Define. ld/ChangeLog: * testsuite/ld-arc/arc.exp: New file. * testsuite/ld-arc/nps-1.s: New file. * testsuite/ld-arc/nps-1a.d: New file. * testsuite/ld-arc/nps-1b.d: New file. * testsuite/ld-arc/nps-1b.err: New file. opcodes/ChangeLog: * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst instructions. * arc-opc.c (insert_nps_cmem_uimm16): New function. (extract_nps_cmem_uimm16): New function. (arc_operands): Add NPS_XLDST_UIMM16 operand. 2016-03-29 23:02:19 +00:00			`#source: nps-1.s`
			`#as: -mcpu=nps400`
			`#ld: -defsym=foo=0x57f03000`
			`#objdump: -d`

			`.: +file format .arc.*`

			`Disassembly of section .text:`

			`[0-9a-f]+ <.*>:`
			`*[0-9a-f]+: 5948 3000 xldb r10,\[0x57f03000\]`
			`*[0-9a-f]+: 5949 3000 xldw r10,\[0x57f03000\]`
			`*[0-9a-f]+: 594a 3000 xld r10,\[0x57f03000\]`
			`*[0-9a-f]+: 594c 3000 xstb r10,\[0x57f03000\]`
			`*[0-9a-f]+: 594d 3000 xstw r10,\[0x57f03000\]`
			`*[0-9a-f]+: 594e 3000 xst r10,\[0x57f03000\]`