old-cross-binutils/ld/testsuite/ld-arm/jump-reloc-veneers-long.d


.*:     file format.*


Disassembly of section destsect:

09000000 <[^>]*>:
 9000000:	e7fe      	b.n	9000000 <dest>

Disassembly of section .text:

000080.. <[^>]*>:
    80..:	b802f000 	.word	0xb802f000
    80..:	00000000 	andeq	r0, r0, r0

000080.. <[^>]*>:
    80..:	4778      	bx	pc
    80..:	46c0      	nop			; \(mov r8, r8\)
    80..:	e59fc000 	ldr	ip, \[pc\]	; 80.. <__dest_veneer\+0xc>
    80..:	e12fff1c 	bx	ip
    80..:	09000001 	.word	0x09000001
Fix testsuite for Thumb2 jump reloc veneers. 2010-02-01 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * ld-arm/jump-reloc-veneers-long.d: New test. * ld-arm/jump-reloc-veneers-short1.d: Likewise. * ld-arm/jump-reloc-veneers-short2.d: Likewise. * ld-arm/jump-reloc-veneers.s: Likewise. * ld-arm/arm-elf.exp (armelftests): Run them. 2010-02-01 10:33:16 +00:00
			`.: file format.`


			`Disassembly of section destsect:`

			`09000000 <[^>]*>:`
			`9000000: e7fe b.n 9000000 <dest>`

			`Disassembly of section .text:`

2010-02-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * ld-arm/jump-reloc-veneers-long.d: Correct testcase for arm-none-eabi target. * ld-arm/jump-reloc-veneers-short1.d: Likewise * ld-arm/jump-reloc-veneers-short2.d: Likewise 2010-02-16 19:02:59 +00:00			`000080.. <[^>]*>:`
			`80..: b802f000 .word 0xb802f000`
			`80..: 00000000 andeq r0, r0, r0`
Fix testsuite for Thumb2 jump reloc veneers. 2010-02-01 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * ld-arm/jump-reloc-veneers-long.d: New test. * ld-arm/jump-reloc-veneers-short1.d: Likewise. * ld-arm/jump-reloc-veneers-short2.d: Likewise. * ld-arm/jump-reloc-veneers.s: Likewise. * ld-arm/arm-elf.exp (armelftests): Run them. 2010-02-01 10:33:16 +00:00
2010-02-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * ld-arm/jump-reloc-veneers-long.d: Correct testcase for arm-none-eabi target. * ld-arm/jump-reloc-veneers-short1.d: Likewise * ld-arm/jump-reloc-veneers-short2.d: Likewise 2010-02-16 19:02:59 +00:00			`000080.. <[^>]*>:`
			`80..: 4778 bx pc`
			`80..: 46c0 nop ; \(mov r8, r8\)`
gas/ * config/tc-arm.c (parse_address_main): Handle -0 offsets. (encode_arm_addr_mode_2): Set default sign of zero here ... (encode_arm_addr_mode_3): ... and here. (encode_arm_cp_address): ... and here. (md_apply_fix): Use default sign of zero here. gas/testsuite/ * gas/arm/inst.d: Adjust for signed zero offsets. * gas/arm/ldst-offset0.d: New test. * gas/arm/ldst-offset0.s: New test. * gas/arm/offset-1.d: New test. * gas/arm/offset-1.s: New test. ld/testsuite/ Adjust tests for zero offset formatting. * ld-arm/cortex-a8-fix-bcc-plt.d: Adjust. * ld-arm/farcall-arm-arm-pic-veneer.d: Adjust. * ld-arm/farcall-arm-thumb.d: Adjust. * ld-arm/farcall-group-size2.d: Adjust. * ld-arm/farcall-group.d: Adjust. * ld-arm/farcall-mix.d: Adjust. * ld-arm/farcall-mix2.d: Adjust. * ld-arm/farcall-mixed-lib-v4t.d: Adjust. * ld-arm/farcall-mixed-lib.d: Adjust. * ld-arm/farcall-thumb-arm-blx-pic-veneer.d: Adjust. * ld-arm/farcall-thumb-arm-pic-veneer.d: Adjust. * ld-arm/farcall-thumb-thumb.d: Adjust. * ld-arm/ifunc-10.dd: Adjust. * ld-arm/ifunc-3.dd: Adjust. * ld-arm/ifunc-4.dd: Adjust. * ld-arm/ifunc-5.dd: Adjust. * ld-arm/ifunc-6.dd: Adjust. * ld-arm/ifunc-7.dd: Adjust. * ld-arm/ifunc-8.dd: Adjust. * ld-arm/jump-reloc-veneers-long.d: Adjust. * ld-arm/tls-longplt-lib.d: Adjust. * ld-arm/tls-thumb1.d: Adjust. opcodes/ * arm-dis.c (print_insn_coprocessor): Explicitly print #-0 as address offset. (print_arm_address): Likewise. Elide positive #0 appropriately. (print_insn_arm): Likewise. 2011-06-02 15:32:10 +00:00			`80..: e59fc000 ldr ip, \[pc\] ; 80.. <__dest_veneer\+0xc>`
2010-02-15 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * ld-arm/jump-reloc-veneers-long.d: Correct testcase for arm-none-eabi target. * ld-arm/jump-reloc-veneers-short1.d: Likewise * ld-arm/jump-reloc-veneers-short2.d: Likewise 2010-02-16 19:02:59 +00:00			`80..: e12fff1c bx ip`
			`80..: 09000001 .word 0x09000001`