259 lines
6.5 KiB
C
259 lines
6.5 KiB
C
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/* m32r simulator support code
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Copyright (C) 1996, 1997 Free Software Foundation, Inc.
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Contributed by Cygnus Support.
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This file is part of GDB, the GNU debugger.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#define WANT_CPU
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#define WANT_CPU_M32R
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#include "sim-main.h"
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#include <signal.h>
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#include "libiberty.h"
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#include "bfd.h"
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/* FIXME: need to provide general mechanism for accessing target files
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these. For now this is a hack to avoid getting the host version. */
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#include "../../libgloss/m32r/sys/syscall.h"
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#include "targ-vals.h"
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/* The contents of BUF are in target byte order. */
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void
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m32r_fetch_register (sd, rn, buf)
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SIM_DESC sd;
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int rn;
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unsigned char *buf;
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{
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SIM_CPU *current_cpu = STATE_CPU (sd, 0);
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if (rn < 16)
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SETTWI (buf, GET_H_GR (rn));
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else if (rn < 21)
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SETTWI (buf, GET_H_CR (rn - 16));
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else switch (rn) {
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case PC_REGNUM:
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SETTWI (buf, GET_H_PC ());
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break;
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case ACCL_REGNUM:
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SETTWI (buf, GETLODI (GET_H_ACCUM ()));
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break;
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case ACCH_REGNUM:
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SETTWI (buf, GETHIDI (GET_H_ACCUM ()));
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break;
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#if 0
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case 23: *reg = STATE_CPU_CPU (sd, 0)->h_cond; break;
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case 24: *reg = STATE_CPU_CPU (sd, 0)->h_sm; break;
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case 25: *reg = STATE_CPU_CPU (sd, 0)->h_bsm; break;
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case 26: *reg = STATE_CPU_CPU (sd, 0)->h_ie; break;
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case 27: *reg = STATE_CPU_CPU (sd, 0)->h_bie; break;
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case 28: *reg = STATE_CPU_CPU (sd, 0)->h_bcarry; break; /* rename: bc */
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case 29: memcpy (buf, &STATE_CPU_CPU (sd, 0)->h_bpc, sizeof(WI)); break; /* duplicate */
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#endif
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default: abort ();
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}
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}
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/* The contents of BUF are in target byte order. */
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void
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m32r_store_register (sd, rn, buf)
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SIM_DESC sd;
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int rn;
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unsigned char *buf;
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{
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SIM_CPU *current_cpu = STATE_CPU (sd, 0);
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if (rn < 16)
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SET_H_GR (rn, GETTWI (buf));
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else if (rn < 21)
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SET_H_CR (rn - 16, GETTWI (buf));
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else switch (rn) {
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case PC_REGNUM:
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SET_H_PC (GETTWI (buf));
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break;
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case ACCL_REGNUM:
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SETLODI (CPU (h_accum), GETTWI (buf));
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break;
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case ACCH_REGNUM:
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SETHIDI (CPU (h_accum), GETTWI (buf));
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break;
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#if 0
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case 23: STATE_CPU_CPU (sd, 0)->h_cond = *reg; break;
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case 24: STATE_CPU_CPU (sd, 0)->h_sm = *reg; break;
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case 25: STATE_CPU_CPU (sd, 0)->h_bsm = *reg; break;
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case 26: STATE_CPU_CPU (sd, 0)->h_ie = *reg; break;
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case 27: STATE_CPU_CPU (sd, 0)->h_bie = *reg; break;
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case 28: STATE_CPU_CPU (sd, 0)->h_bcarry = *reg; break; /* rename: bc */
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case 29: memcpy (&STATE_CPU_CPU (sd, 0)->h_bpc, buf, sizeof(DI)); break; /* duplicate */
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#endif
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}
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}
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/* Handling the MSPR register is done by creating a device in the core
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mapping that winds up here. */
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device m32r_mspr_device;
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int
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device_io_read_buffer (device *me, const void *source, int space,
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address_word addr, unsigned nr_bytes,
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SIM_CPU *cpu, sim_cia cia)
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{
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abort ();
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}
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int
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device_io_write_buffer (device *me, const void *source, int space,
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address_word addr, unsigned nr_bytes,
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SIM_CPU *cpu, sim_cia cia)
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{
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#if WITH_SCACHE
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if (addr == MSPR_ADDR
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&& (*(char *) source & 1) != 0)
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scache_flush (CPU_STATE (cpu));
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#endif
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return nr_bytes;
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}
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void device_error () {}
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#if WITH_PROFILE_MODEL_P
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void
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m32r_model_mark_get_h_gr (SIM_CPU *cpu, ARGBUF *abuf)
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{
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if ((CPU_CGEN_PROFILE (cpu)->h_gr & abuf->h_gr_get) != 0)
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{
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PROFILE_MODEL_LOAD_STALL_COUNT (CPU_PROFILE_DATA (cpu)) += 2;
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if (TRACE_INSN_P (cpu))
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cgen_trace_printf (cpu, " ; Load stall of 2 cycles.");
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}
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}
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void
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m32r_model_mark_set_h_gr (SIM_CPU *cpu, ARGBUF *abuf)
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{
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}
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void
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m32r_model_mark_busy_reg (SIM_CPU *cpu, ARGBUF *abuf)
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{
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CPU_CGEN_PROFILE (cpu)->h_gr = abuf->h_gr_set;
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}
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void
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m32r_model_mark_unbusy_reg (SIM_CPU *cpu, ARGBUF *abuf)
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{
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CPU_CGEN_PROFILE (cpu)->h_gr = 0;
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}
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#endif /* WITH_PROFILE_MODEL_P */
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USI
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m32r_h_cr_get (SIM_CPU *current_cpu, UINT cr)
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{
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/* FIXME: Create enums H_CR_FOO, etc. */
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switch (cr)
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{
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case 0 : /* psw */
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return ((CPU (h_bsm) << 15)
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| (CPU (h_bie) << 14)
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| (CPU (h_bcond) << 8)
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| (CPU (h_sm) << 7)
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| (CPU (h_ie) << 6)
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| (CPU (h_cond) << 0));
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case 1 : /* condition bit */
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return CPU (h_cond);
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case 2 : /* interrupt stack pointer */
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if (! CPU (h_sm))
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return CPU (h_gr[15]);
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else
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return CPU (h_cr[2]);
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case 3 : /* user stack pointer */
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if (CPU (h_sm))
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return CPU (h_gr[15]);
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else
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return CPU (h_cr[3]);
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case 6 : /* backup pc */
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/* ??? We don't really support this yet. */
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case 4 : /* unused */
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case 5 : /* unused */
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return CPU (h_cr[cr]);
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default :
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return 0;
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}
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}
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void
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m32r_h_cr_set (SIM_CPU *current_cpu, UINT cr, USI newval)
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{
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/* FIXME: Create enums H_CR_FOO, etc. */
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switch (cr)
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{
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case 0 : /* psw */
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{
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int old_sm = CPU (h_sm);
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CPU (h_bsm) = (newval & (1 << 15)) != 0;
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CPU (h_bie) = (newval & (1 << 14)) != 0;
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CPU (h_bcond) = (newval & (1 << 8)) != 0;
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CPU (h_sm) = (newval & (1 << 7)) != 0;
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CPU (h_ie) = (newval & (1 << 6)) != 0;
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CPU (h_cond) = (newval & (1 << 0)) != 0;
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/* When switching stack modes, update the registers. */
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if (old_sm != CPU (h_sm))
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{
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if (old_sm)
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{
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/* Switching user -> system. */
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CPU (h_cr[3]) = CPU (h_gr[15]);
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CPU (h_gr[15]) = CPU (h_cr[2]);
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}
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else
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{
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/* Switching system -> user. */
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CPU (h_cr[2]) = CPU (h_gr[15]);
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CPU (h_gr[15]) = CPU (h_cr[3]);
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}
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}
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break;
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}
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case 1 : /* condition bit */
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CPU (h_cond) = (newval & 1) != 0;
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break;
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case 2 : /* interrupt stack pointer */
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if (! CPU (h_sm))
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CPU (h_gr[15]) = newval;
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else
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CPU (h_cr[2]) = newval;
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break;
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case 3 : /* user stack pointer */
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if (CPU (h_sm))
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CPU (h_gr[15]) = newval;
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else
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CPU (h_cr[3]) = newval;
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break;
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case 4 : /* unused */
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case 5 : /* unused */
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case 6 : /* backup pc */
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CPU (h_cr[cr]) = newval;
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break;
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default :
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/* ignore */
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break;
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}
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}
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