115 lines
4.2 KiB
C
115 lines
4.2 KiB
C
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/****************************************************************************/
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/* */
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/* Sony Computer Entertainment CONFIDENTIAL */
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/* (C) 1997 Sony Computer Entertainment Inc. All Rights Reserved */
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/* */
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/* VU simulator global definitions */
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/* */
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/****************************************************************************/
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#include <stdio.h>
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#include <sys/types.h>
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#include <strings.h>
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#include <math.h>
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typedef struct {
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int no; /* destination register number VF:0-31 VI:32-47*/
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int mask; /* specify which units calculate */
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float vf[4]; /* calculated value */
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int flag; /*0: empty in this pipeline stage,
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1: write value to reg,
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2: store value from reg,
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3: write value to I-reg ( not used ),
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4: write only status to statusflag,
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5: write only clip value to clipflag,
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6: move value from EFU reg */
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u_long status; /* calculation unit status */
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u_long addr; /* store address ( store operation )*/
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char code[32]; /* instruction */
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} PIPELINE; /* pipeline stage specification for FMAC, Ld/St, RANDU, FDIV */
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typedef struct {
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int no; /* destination register number VI:0-15 */
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short vi; /* calculated value */
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int flag; /* 0: empty in this pipeline stage,
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1: write value to reg */
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char code[32]; /* instruction */
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} IPIPELINE; /* pipeline stage specification for IALU */
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typedef struct {
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int flag; /* 0: empty in this pipeline stage,
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1: write value to I-reg */
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float val; /* calculated value */
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} LOIPIPELINE; /* pipeline stage specification for I bit */
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typedef struct {
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int mask; /* specify which units calculate */
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float acc[4]; /* calculated value */
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int flag; /* 0: empty in this pipeline stage,
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1: write value to ACC */
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} APIPELINE; /* accumulator pipeline stage specification */
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typedef struct {
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int no; /* left stage count of pipeline */
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float vn; /* calculated value */
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int flag; /* 0: move to VN[4]
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1: move to VN[0] (not used)*/
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} SUPIPELINE;
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u_long instbuf[2]; /* instruction buffer. instbuf[0]:Upper, instbuf[1]:Lower*/
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u_long pc, opc; /* pc is next PC, opc is executed PC. see fetch_inst() */
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u_long jaddr; /* branch address */
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float VF[32][4]; /* VF registers */
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/* VF[?][0] = x, VF[?][1] = y, VF[?][2] = z, VF[?][3] = w */
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short VI[16]; /* VI registers */
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float ACC[4]; /* accumulator registers */
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float Q; /* FDIV register */
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float I; /* I register */
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u_long R; /* RANDU register */
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float VN[32]; /* EFU registers */
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u_long MACflag;
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u_long statusflag;
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u_long clipflag;
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u_long MEM[4096][4]; /* VU (data) memory */
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u_long uMEM[1024][2]; /* Micro (instruction) memory */
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PIPELINE pipe[4][2]; /* FMAC, Ld/St, RANDU piepline */
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PIPELINE qpipe[7]; /* FDIV(DIV,DQRT) pipeline */
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PIPELINE rqpipe[13]; /*FDIV(RSQRT) pipeline */
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IPIPELINE ipipe[2]; /* IALU pipeline */
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APIPELINE apipe; /* ACC pipeline stage */
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SUPIPELINE spipe; /* EFU pipeline stage */
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LOIPIPELINE Ipipe; /* I-bit pipeline stage */
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int eflag, jflag, peflag, sflag;
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/* eflag: E-bit detect flag
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0: not detect, 1: detect, -1: fetch stage terminate
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jflag: branch detect flag
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0: not detect, 1: detect
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peflag: end delay slot execute flag
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0: not execute, 1: execute, -1: finished ececution
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sflag: data hazard stall flag
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0: not stall, 1: stall */
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u_long bp; /* break point address */
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u_long ecount; /* end counter */
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int intr_mode; /* interactive mode enable */
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int verb_mode; /* verbose mode enable */
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int dpr_mode; /* PRT (debug print) instruction enable */
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u_long all_count; /* amount of executed cycles */
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u_long hc_count; /* amount of hazard stall cycles */
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extern int _GIF_SIM_OFF; /* internal GPUIF simulator disable */
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extern int _GIF_BUSY; /* external GPUIF simulator is BUSY flag,
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this flag uses when _GIF_SIM_OFF = 1 */
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extern int _GIF_VUCALL; /* XGKICK instruction detect flag,
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this flag uses when _GIF_SIM_OFF = 1 */
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extern int _GIF_VUADDR; /* appointed address by XGKICK instruction,
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this flag uses when _GIF_SIM_OFF = 1 */
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#define DEST_X 0x8
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#define DEST_Y 0x4
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#define DEST_Z 0x2
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#define DEST_W 0x1
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